>From [log in to unmask] Fri Mar 29 11:21:49 1996 Return-Path: <[log in to unmask]> Received: from hoppy by schooner (4.1/SMI-4.1) id AA17545; Fri, 29 Mar 96 11:21:48 EST Received: from kodakt.kodak.com by hoppy (5.x/SMI-SVR4) id AA18394; Fri, 29 Mar 1996 11:21:47 -0500 Received: from uu3.psi.com (uu3.psi.com [38.145.250.2]) by kodakt.kodak.com (8.7.4/8.7.3) with SMTP id LAA03933 for <[log in to unmask]>; Fri, 29 Mar 1996 11:26:51 -0500 (EST) Received: from carp.UUCP by uu3.psi.com (5.65b/4.0.940727-PSI/PSINet) via UUCP; id AA18145 for ; Fri, 29 Mar 96 11:17:08 -0500 Received: by ipc.com (5.0/SMI-SVR4) id AB11265; Fri, 29 Mar 1996 10:44:35 +0500 Date: Fri, 29 Mar 1996 10:44:35 +0500 From: [log in to unmask] (Mail Delivery Subsystem) Subject: Returned mail: User unknown Message-Id: <9603291544.AB11265@ ipc.com> To: [log in to unmask] Content-Length: 5297 X-Lines: 107 Status: RO ----- Transcript of session follows ----- 550 TechNet... User unknown ----- Unsent message follows ----- Received: by ipc.com (5.0/SMI-SVR4) id AA11263; Fri, 29 Mar 1996 10:44:35 +0500 Errors-To: [log in to unmask] >Received: from kodakr.kodak.com by uu3.psi.com (5.65b/4.0.940727-PSI/PSINet) via SMTP; Response to: ================================================================= Is there a Standard amount of Test Point Coverage at the PCB Bare Board Supplier during Electrical Test in which an NRE setup and 100% Electrical Test of PCB's was charged. What is the chance of Escape associated with Electrical Test? Thanks in advance for any help given. [log in to unmask] ================================================================= Nancy those are good questions. I would like to see all the responses to your questions. Although I have been in the bare board manufacturing the and PCB design business for more that 25 years I can't answer your specific questions. The following is just my engineering opinions. First and formost is you get what you specifically ask for and you pay for all of it. If you specifically ask for electrical testing of a Bare PCB, you should contact the supplier to understand the limitations of their board board tester prior to designing your PCB and understand the coverage vs cost for various guaranteed reliability levels of product. Assume that you want to test 100% of all unique printed circuit features on one finished bare PCB for all possible shorts and opens conditions. Certainly you want each bare board to pass this test. You must design the PCB such that the Bare board tester can reliably contact ALL ends of All discrete printed circuit voltage, ground and signal nets simultaneously. This can be costly and would limit your design density to the tester probe to probe minimum grid and maximum number of probes allowed by the test equipment. Any design that does not allow for this complete coverage leaves some % posibility of defect detection escapes. The answer is one of statistics for the specific board design in question. Each net has the risk of shorts and / or opens along it's entire path. Which other nets it has a risk to short with is a function of the routing path that that specific net takes. The amount of risk is a function of the length and spacing of each net to the other. Net to net shorts risk sites go up as the length that nets run adjacent to each other on any metal plane level in the bare board increases. You can see that the % of coverage and % of potential escapes is very dependant on the specific test and tester that the bare board fabricator uses. As the PCB is designed with thiner printed circuit lines the risk of pc net opens goes up. As the PCB is designed with closer line to line spacings the risk of pc shorts goes up. Manufacturing test engineers for bare board products need to calculate the % coverage and % defect escapes vs the risk and cost factors for their business. NRE will be charged for any unique software or hardware that is needed for testing your bare board. The rest of the cost for testing should be buried in the unit cost of the bare board. I know that I did not answer any of your specific questions but as I suggested, contact each bare board manufacturer to get the specifics on their definition of "100% Electrical Test". 100% electrical test might mean 100% of all possible shorts and opens were tested for on some statistically significant sample size of each lot of PCBs produced and shipped. The remainder of the PCBs in the lot might have had optical inspection only. Bare board testing for net to net shorts is sometimes done at the assembler prior to component attachment processes but this would add cost that you (the customer) would like to eliminate. The major assumption you have to make with all bare board testing is that your bare board manufacturer has qualified their processes and product to be reliable after stress testing. Stress testing must simulate the subsequent manufacturing and functional usage conditions that the bare board is subjected to in it's product life. Bare boards are not stress tested as part of the normal manufacturing process. If you don't specify the type and extent of testing you want on a PCB you will get only what the PCB manufacturer can afford and still be competitive in their industry. Sorry if this is no help to you, but who said that electronic packaging engineering is simple.