John, Good to see you back on-line. Here's the info you 're looking for. Regards, Tom -- [ From: cirworld * EMC.Ver #2.5.02 ] -- CirWorld News - June 1996 An email newsletter from CircuitWorld Online Services - Gateway to Electronics Manufacturing - http://www.circuitworld.com ---------------------------------------------------------------------- ------ -------------------------------------------------------------- A BREAKTHROUGH CONTACTLESS TEST TECHNOLOGY FOR PRINTED CIRCUIT BOARDS ---------------------------------------------------------------------- ------ --------------------------------------------------------------- Cirlog Corporation, located in Winnipeg, Canada, has developed a contactless test technology for printed circuit boards based on electromagnetic principles. Cirlog's Patented technology effectively finds open circuit and short circuit faults on innerlayer and bare printed circuit boards. It provides a technique that does not require direct electrical contact with the Board Under Test (BUT). The features of Cirlog's technology include: detecting open and short circuit faults without contacting the BUT, no damage to the BUT because of the contactless nature of the test, fast setup time since no test programs or special fixtures are required, fast measuring time, automated operation can be achieved, no limits on the pattern pitch and pattern width since the BUT is scanned not probed and low system cost. The technology is based on electromagnetic principles and thus gives insight into the electrical characteristics of the BUT. Fault detection is based on comparisons to data from known good boards and fault location can be displayed for reference. Our contactless test technology provides numerous advantages over current bare PCB test techniques, namely automated optical inspection (AOI) and electrical testing. AOI test systems are very expensive and no insight to electrical characteristics is obtained. Electrical test systems, which use a bed-of-nails or a flying probe, directly probe the surface of the BUT and faults can be introduced by touching the BUT with the contact probes. Setting up electrical tests requires special fixturing and generation of test programs, which requires information on the connectivity of the BUT from CAD or Gerber data. If modifications are made to a board layout it is difficult and time consuming to adapt the electrical test to the changes. Furthermore, the tighter tolerances on today's PCBs makes it difficult to reliably hit specified points to test the BUT. Our technology is implemented with a multilayer PCB board design, the required mechanical arrangements and a computer workstation. By scanning across the entire surface of the BUT, a displacement current signature of the BUT is obtained. A fault recognition system compares the pattern of the BUT with a known or desired pattern of an identical, non-faulty BUT. The location of faults is given by x-y coordinates which can also be superimposed on the displacement current image of the BUT for reference. Currently, Cirlog Corporation has a joint venture with a Japanese company to develop a test system based on this technology and expects to have a fully functional pre-production model in September of this year. We may be interested in a similar arrangement with a North American company to develop the system for the North American market. We are also continuing to examine other applications for this unique technology. editor: In an effort to gain some additional details, I directed some questions to Mr. Soiferman, President of the Cirlog Corporation, about this new technology. I have included these questions and answers below. ********************************************************************** ****** **************** CWN - Will the unit be capable of importing CAD netlist data for comparison or will it use only the "golden board" method of setup? JS - Currently the test system uses the gold board method of setup. We are planning to implement CAD data as a means to display the fault on screen in the near future. ********************************************************************** ****** **************** CWN - What are the projected cycle times for testing a typical board configuration? JS - We can scan a 650mm by 650mm panel in approximately 7 seconds with a 0. 25mm step size. The smallest step size is about 0.01mm. ********************************************************************** ****** **************** CWN - What is the projected setup time? JS - Setting up and scanning a gold board should take less than one hour. ********************************************************************** ****** **************** CWN - Will it be able to generate specific fault locations? JS - In most cases it will find the specific fault location or to within a close proximity. ********************************************************************** ****** **************** CWN - How will it respond to defects such as trace narrowing, near shorts (spacing violations), and partial voids in plated through holes? JS - It will detect large trace narrowing, spacing violations and large voids in plated through holes. ********************************************************************** ****** **************** CWN - Will the electromagnetic attributes of a pcb vary with plating thickness, soldermask, use of alternative coatings? JS - The attributes will vary. However our fault detection algorithms account for these types of variations so that faults are not masked out. We also have algorithms that will indicate the changes caused by different thicknesses and coating materials if required. ********************************************************************** ****** **************** For further information contact Jacob Soiferman at Cirlog Corporation by phone at (204) 949-0519 or e-mail at [log in to unmask] ______________________________ Reply Separator _________________________________ Subject: FAB: Cirlog Author: [log in to unmask] at INTERNET_GATEWAY Date: 10/9/96 1:46 PM Address, I am looking for the phone number to Cirlog in Winnipeg, Canada. I would like further information on their Contactless Test Technology for PCBs that was breifly discussed several months ago. In addition to this, has anyone determined if the technology can be used with assembled cards. Please advise. Thank you John Gulley Inet Inc. - A Smarter Vision Plano, TX 972-578-3928 ********************************************************************** ***** * TechNet mail list is provided as a service by IPC using SmartList v3.05 * ********************************************************************** ***** * To unsubscribe from this list at any time, send a message to: * * [log in to unmask] with <subject: unsubscribe> and no text. * ********************************************************************** ***** *************************************************************************** * TechNet mail list is provided as a service by IPC using SmartList v3.05 * *************************************************************************** * To unsubscribe from this list at any time, send a message to: * * [log in to unmask] with <subject: unsubscribe> and no text. * ***************************************************************************