Flux will definitely affect bridging. I have no experience with OA or noclean, but higher gravity rosin flux will prevent bridges. Lower gravity will decrease skips on SMT chips. Allen Ahlert [log in to unmask] ______________________________ Reply Separator _________________________________ Subject: Re[3]: Solder Bridges on SMT SOIC's Author: [log in to unmask] at halsic_ccsmtp Date: 8/4/95 7:46 AM As per my last request for information on solder bridges on SOIC's, Thank you very much for the input. I have another question for yuuuz guys ?? 1. Will the use of a different solder help to reduce the Solder Bridging on Wave Soldered SOIC's (We are planning to change from Kester Ultra-pure to Alpha Hi-Flo). 2 Will the use of a different Flux or type of flux help reduce the same problem ie: from OA water soluble to no clean. Or even a different manufacture ( we are currently using Alpha 857, Water Soluble OA - Alcohol based flux). Any input would be great. As ELVIS would say " THANK YOU VERY MUUUUUCH!!) Eric Bernal, Manufact. Engineer Pragmatech, Sunnyvale, CA [log in to unmask] ______________________________ Reply Separator _________________________________ Subject: Re[2]: Solder Bridges on SMT SOIC's Author: [log in to unmask] at ~INTERNET Date: 8/3/95 3:05 PM Received: by ccmail Received: from netcomsv by pragma.com (UUPC/extended 1.11) with UUCP; Thu, 03 Aug 1995 15:03:48 PDT Received: from miso.wwa.com by netcomsv.netcom.com with SMTP (8.6.12/SMI-4.1) id OAA15966; Thu, 3 Aug 1995 14:34:45 -0700 Resent-Date: Thu, 3 Aug 1995 14:34:45 -0700 Received: from ipc by miso.wwa.com with uucp (Smail3.1.28.1 #8) id m0se7wM-000FUGC; Thu, 3 Aug 95 16:36 CDT Received: by ipchq.com (Smail3.1.28.1 #2) id m0se7Or-0000GlC; Thu, 3 Aug 95 16:01 CDT Old-Return-Path: <miso!pragma.pragma.com!cwu> From: [log in to unmask] X-ccAdmin: postmaster@netcomsv Date: Thu, 03 Aug 95 12:56:07 Encoding: 2749 Text Message-Id: <[log in to unmask]> To: [log in to unmask] To: [log in to unmask] Cc: [log in to unmask] Subject: Re[2]: Solder Bridges on SMT SOIC's Resent-Message-ID: <"Yt64a3.0.ADH.1bJ8m"@ipc> Resent-From: [log in to unmask] X-ccAdmin: postmaster@netcomsv X-Mailing-List: <[log in to unmask]> archive/latest/786 X-Loop: [log in to unmask] Precedence: list Resent-Sender: [log in to unmask] Andy, We have the same problem on the solder bridges at SOICs. We are going toward select soldering since even there is no bridge, there is a big chance of getting excessive solder/ no stress relief on the last two pins. I have the following questions if you don't mind: (1). What is your average defect rate? (2). What kind of OA flux is the best based on your experience? (3). Do you think low viscosity solder will help? Cherng Wu [log in to unmask] Pragmatech Inc. ______________________________ Reply Separator _________________________________ Subject: re: Solder Bridges on SMT SOIC's Author: [log in to unmask] To: [log in to unmask] Cc: [log in to unmask] at ~INTERNET Date: 7/31/95 8:32 AM Received: by ccmail Received: from netcomsv by pragma.com (UUPC/extended 1.11) with UUCP; Mon, 31 Jul 1995 08:31:59 PDT Received: from miso.wwa.com by netcomsv.netcom.com with SMTP (8.6.12/SMI-4.1) id IAA15210; Mon, 31 Jul 1995 08:02:57 -0700 Resent-Date: Mon, 31 Jul 1995 08:02:57 -0700 Received: from ipc by miso.wwa.com with uucp (Smail3.1.28.1 #8) id m0scwOa-000FS5C; Mon, 31 Jul 95 10:04 CDT Received: by ipchq.com (Smail3.1.28.1 #2) id m0scvL7-0000GmC; Mon, 31 Jul 95 08:57 CDT Old-Return-Path: <miso!cd4202.genrad.co.uk!richardsona> Date: Mon, 31 Jul 1995 08:33:21 GMT From: ANDY RICHARDSON <[log in to unmask]> X-ccAdmin: postmaster@netcomsv Reply-To: [log in to unmask] To: [log in to unmask] Cc: [log in to unmask] Message-Id: <[log in to unmask]> Subject: re: Solder Bridges on SMT SOIC's Resent-Message-ID: <"EPKSC3.0.CCB.l4E7m"@ipc> Resent-From: [log in to unmask] X-ccAdmin: postmaster@netcomsv X-Mailing-List: <[log in to unmask]> archive/latest/763 X-Loop: [log in to unmask] Precedence: list Resent-Sender: [log in to unmask] **ERROR** LONG FROM FIELD. FIELD WAS CUT. OLD FIELD WAS: [log in to unmask] To: [log in to unmask] Cc: [log in to unmask] Message-Id: <[log in to unmask]>Ref e-mail from Eric Bernal at Pragmatech, Sunnyvale, Ca Eric, We at GenRad us the solder thief technique whereby and extra set of SOIC solder pads are added to the last set of pads to see the solder wave. If all your IC's are flowed in the same direction (i.e. the wave should pass along the length of the IC) it then becomes a case of pads sizes and flux selection. We use the IPC standard pad sizes for most devices including SOIC's which seem to work. Good luck! Andy Richardson GenRad UK