Via plugging is an ugly process that should be designed out as soon as possible. While it does seal the via, it is an extra process and can create a whole new set of problems. Problems that we've seen with via plugging include solder volcanoes (lengthy description available if requested) and bumps of epoxy on the surface of the board. The epoxy bumps wreak havoc on the stencil process if they're located anywhere near 20-mil pitch SMT devices. We have designed out all epoxy plugs. 100% of our new boards have been LPI for the last 2 years. Our test fixtures are mechanical. We use a no-clean process, so entrapped fluxes are not an issue. The majority of our new products utilize OSP or ni/au, so entrapped chemistry from HASL is not an issue. For the occasional via that requires better protection to prevent shorting (beneath crystal cans, or metal body connectors, for example), we will use the white epoxy nomenclature ink to cover the via hole. Nomenclature is already on the board, and thus costs nothing to add occasional via coverage. -Jeff Deeney- [log in to unmask] Hewlett Packard Co. Computer Interconnect Operation Fort Collins, CO