I have a requirement to  investigate the definition of the maximum 
chip ceramic capacitor footprint which can be used with various 
substrate materials - FR4 PCB, ceramic, and aluminium-core materials. 
The application is for output filtering in SMPS circuits. I wish to 
use leadless capacitors. I am mainly concerned with the TCE mismatch 
between the materials and the resulting stress levels which may cause 
cracking. I am assuming that the placement and IR reflow process and 
handling procedures will be under control and will not caus any damage.

Is there any studies/technical literature available on this subject?

I understand there is a move in the industry to larger capacitance 
values in smaller footprints - how significant is this in terms of
capacitance value versus size?  Any assistance/direction would be 
appreaciated. Cian O Mathuna. 
Dr. Sean Cian O Mathuna                                             
Applications Director/Centre Manager                                                                             
Power Electronics Ireland,                                                                                                 
National Microelectronics Research Centre,
University College, Cork,
Ireland.

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