Hi Jerry, >For those readers involved in SMT board level assembly, I have a question. >.As a "benchmark", your opinions are solicited. At my Company, we assemble >PWA's with dominantly SM packages. Our projected number one product for >next year is a PCI format (about 6.6" x 3.6" exclusive of the gold fingers) >board with SMT parts both sides (print paste, place, reflow; repeat for >other side). Typically, a defective unit may have one or more defects. However, the traditional data collection on defective percentage does not take into account the number of opportunities for defect to occur. Defect opportunity is the possibility of inducing a defect or non conformance in a unit of product at a manufacturing operation. As a benchmark, I think you should use your own historic data to estimate the DPMO of each individual package. >The board is populated with 205 total devices including 167 discretes, 18 >0.05" pitch parts, and 20 fine pitch parts. There are 1,948 total SM solder >joints and 1,276 of these will be fine pitch (mostly 0.5 mm). No through >hole devices on this assembly (yay!). EXAMPLE: >From your historic data, you know that your DPMO to reflow discrete parts on top side are 10. Quantity 167 Total Oppor. Per Unit (TOPU) 668 Defects Per Unit (DPU) 0.00668 Expected Defects Per Million (PPM) 6680 Process Capability (Cp) 1.42 Expected First Pass Yield 99.33 By summing up all your ppm from each package, you should get a pretty good estimate on the projected defect rate based on your past performance. This way, you can set your projected rate as target yield. >What would you suggest is a reasonable target solder defect rate for this >product (ppm) assuming modern stencil printing and placement techniques? In the long run, six-sigma should be your utilmate target. Please refer to Quality Process, June 1993 for more detail. Michael Yuen Process Engineer [log in to unmask] EAC- A Plexus company Neenah, WI