----- Begin Included Message ----- >From sauter@sauter Fri Sep 1 10:02 PDT 1995 Date: Fri, 1 Sep 1995 10:02:11 +0800 From: sauter@sauter (Karl Sauter) To: [log in to unmask] Subject: Thermal Relief on Vias Cc: [log in to unmask] Does there remain any reason to have thermal reliefs on vias (ie: drilled hole size less than 0.016" diameter) ? Process improvements at our major suppliers have greatly reduced the incidence of "pink ring", and generally improved the quality of the adhesion between internal copper layers and the epoxy laminate. I would appreciate comments on any potential small hole reliability issues with eliminating thermal reliefs on: - standard vias (DHS < 0.015" diameter). - "probe/test point" vias which are required to be solder- filled where there are no/few adjacent power/ground plane clearances. Thanks, Karl Sauter Staff Engineer, Sun Microsystems, Inc. [log in to unmask] ----- End Included Message -----