Dell - Internal Use - Confidential Joyce, Thank you very much for your input/experience. Very enlightening....... Victor, -----Original Message----- From: TechNet [mailto:[log in to unmask]] On Behalf Of Yuan-chia Joyce Koo Sent: Friday, April 6, 2018 8:19 AM To: [log in to unmask] Subject: Re: [TN] FW: IPC-A-610G, section 5.2.9,, Solder anomalies-Fractured solder, Defect 1, 2, 3 (Axial leaded device) as I said before, the 20% is not universal applicable. you need to have data to back up why it is 20%... (for smaller BGA, I would do 10% max). IMHO. On Apr 6, 2018, at 8:55 AM, <[log in to unmask]> <[log in to unmask]> wrote: > Dell - Internal Use - Confidential > > Joyce, > > Is there supported documentation for the Post Sequential Test > allowable percentage (20% max.)? > > Victor, > > -----Original Message----- > From: Yuan-chia Joyce Koo [mailto:[log in to unmask]] > Sent: Friday, April 6, 2018 7:43 AM > To: TechNet E-Mail Forum <[log in to unmask]>; Hernandez, Victor G > <[log in to unmask]> > Subject: Re: [TN] FW: IPC-A-610G, section 5.2.9,, Solder anomalies- > Fractured solder, Defect 1, 2, 3 (Axial leaded device) > > at time zero - as out of factory - no fracture allowed - if you have > fracture at BGA solder mask area, you got crack initiation site - you > need to change solder mask openning to avoid such a fault IMHO. > > At end of sequential test (vib, thermal shock, drop/impact), 20% > max.... Noted in qual report for review as item of susceptibility of > overall system design - program manager have to sign up for knowingly > accept the reliability risk. > > If it is go to sky or some places that repair and overhaul are not > allowed, you have to have redundancy exist to avoid potential failure > risk. 20% is based on electrical design and thermal design > requirements for device under overall assembly level design... not > cast in stone and not universal (23% was maximum based on FEM and > design assessment of worst case performance in this case to derive to > 20%, for example, max environmental temp plus assembly add on > operational temperature for signal current carrying capability and > thermal conduction capability - special attention to the power and > ground..etc.etc)... for example. > hopefully, it helps. > jk > On Apr 6, 2018, at 6:53 AM, <[log in to unmask]> wrote: > >> Fellow TechNetters: >> >> I was surprised that very little input was provided. >> Therefore, since it Friday Elements QUIZ day. I will take advantage >> of the high volume traffic day. >> >> Victor, >> >> From: Hernandez, Victor G >> Sent: Thursday, April 5, 2018 10:22 AM >> To: TechNet E-Mail Forum <[log in to unmask]> >> Cc: Hernandez, Victor G <[log in to unmask]> >> Subject: IPC-A-610G, section 5.2.9,, Solder anomalies-Fractured >> solder, Defect 1, 2, 3 (Axial leaded device) >> >> Fellow TechNetters: >> >> Is there a percentage associated with the statement "Fractured >> Solder" in the above stated IPC STD section? >> I did not a similar statement, Fractured Solder, for Surface Mount >> Devices and Surface Mount Area. >> Is there an acceptable percentage of the solder joint lead interface >> that can be fractured? >> >> >> Victor, >