Jose de Rios provided an important consideration, but it might have gotten overlooked. Some of the Bare Board Acceptability requirements are phrased in a form similar to: "shall not exceed 50% of the distance from board edge to nearest conductor" If your designers are reducing that space (between edge and conductors) then it increases the chance of rejecting perfectly good boards. I have heard that some fabricators refuse a job that is less than 11 mils clearance unless you make an agreement about the acceptability requirements with them in advance Jack . On Mon, 14 Nov 2016 00:14:33 +0200, Yehuda Weisz <[log in to unmask]> wrote: >Hello Technetters, >For the beginning of the week I have a question to you that occupies me more >and more lately, and it concerns one of the design guidelines - "distance of >copper to edge". > >IPC-2221 specifies the minimum distance by design as 20 mils and raises this >value as the voltage drop increases. >Well, as PCBs become more and more dense, it becomes a very challenging task >to convince designers to give up real-estate along the edges of the board. >Their claim - if the manufacturer can work with a tolerance of +/-0.1mm, why >do I need to keep a clearance of 0.5 mm along the edges. >Most of the boards we are dealing with are for high reliability customers >(class 2, class 3 type guys) and from what I have heard from other designers >- no one goes below 20 mil. Some even keep a minimum of 40 mil along the >edges. > >So - my question to you is simply - WHY ??? >Why did the spec. call for 20 mil minimum clearance?? >I do give reasons to the designers, involving reliability and so on but I >feel that I might be missing the real point (or the fundamental reason). > >Could any/some of you, knowledgeable people, help me out on this?? > >Thanks, >Yehuda Weisz