One more valuable link: Although the subject of this thread was was voltage separation in the z-axis of a PCB, I did find a very useful ONLINE CALCULATOR for Creepage and Clearance per IEC/UL http://www.creepage.com/ It saves having to wade through the specifications and combine various tables. HINT: If you are calculating for a PCB construction, select the "IIIa/IIIb" Material Group simple. (big thanks to Dave Larusso!) onward thru the fog, Jack On Fri, Jun 20, 2014 at 11:47 AM, Karl Bates <[log in to unmask]> wrote: > This web page is helpful.http://www.smps.us/pcbtracespacing.html > Karl > > > > Date: Fri, 20 Jun 2014 16:20:52 +0000 > > From: [log in to unmask] > > Subject: Re: [DC] z-axis separation for high voltage > > To: [log in to unmask] > > > > Jack - > > > > There are two different principles at work here. The Table in 2221 is > for creepage across the surface or along the boundary between layers. The > bulk insulation given in the slash sheet is perpendicular to the copper > foil. You can search on HV creepage and find plenty of information. UL was > a great resource at one time but I no longer have access to their specs so > I don't know what they have available. > > > > Is the 1700V DC or AC? If AC make sure it is a peak-to-peak voltage, not > RMS voltage the difference can kill the design. > > > > I would recommend that your minimum core is at least 0.13mm with 2 > layers of 1080 glass. And, if it were my design I would probably want more > like 4 layers of glass and a minimum post processing thickness of 0.20mm > > > > > > Jeffrey McGlaughlin, C.I.D. > > Engineering Designer > > Avionics Systems & Tech Refersh > > Office: 614.424.7582| Fax: 614.458.7582 > > [log in to unmask] > > > > Battelle > > 505 King Avenue > > Columbus Ohio 43201-2693 > > http://www.battelle.org > > > > Connect with Battelle > > Facebook | LinkedIn > > Twitter | YouTube > > > > This message is intended only for the use of the individual or entity to > which it is addressed, and may contain information that is privileged, > confidential and/or otherwise exempt from disclosure under applicable law. > If the reader of this message is not the intended recipient or the employee > or agent responsible for delivering the message to the intended recipient, > any disclosure, dissemination, distribution, copying or other use of this > communication or its substance is prohibited. If you have received this > communication in error, please return to the sender and delete from your > computer system. > > > > > > -----Original Message----- > > From: DesignerCouncil [mailto:[log in to unmask]] On Behalf Of > Jack Olson > > Sent: Friday, June 20, 2014 11:55 AM > > To: [log in to unmask] > > Subject: Re: [DC] z-axis separation for high voltage > > > > Thanks for taking the time to respond (and to everyone else who responded > > too), > > and I understand your point about derating, > > but I am more focused on the STARTING clearance for 1700V, > > > > IPC Table 6-1 gives me something slightly over 125 mils, > > and my board is only 62 mil thickness, about half! > > I wasn't initially worried > > because if you look at the slash sheets for dielectric material, its more > > in the KV range PER MIL > > but now I'm starting to wonder... > > > > Where can I learn more about this? > > > > > > On Fri, Jun 20, 2014 at 10:45 AM, Joel S. Peiffer <[log in to unmask]> > wrote: > > > > > William provides some good advice to derate the materials insulation > > > resistance significantly as well as providing some of the reasons for > > > doing this (copper surface roughness, dielectric defects). > > > > > > I would like to go into a little more detail on derating. The boards > > > operating conditions (temp, humidity) and expected service life need > to be > > > taken into account as well. High temp/humidity operating environments > may > > > call for additional derating. The overlap area of high voltage should > > > also be taken into consideration. If the area is very small, the > > > likelihood of a material defect is very small. However, if the area is > > > very large, the likelihood of a material defect will increase in > > > proportion to the area and the material may have to be derated > > > appropriately. Finally, the derating should be dependent on the > > > dielectric thickness. Thus, thicker materials need to be derated less > > > than thinner materials. For example, a 0.5 mil defect may not have > much > > > impact on a 5 mil thick material but it will have severe consequences > on a > > > 1 mil thick material. > > > > > > If you need to utilize very thin dielectrics to ensure you meet you z > axis > > > thickness requirements, you may want to look at materials other than > FR-4 > > > to provide the required insulation resistance requirements. Some of > the > > > polyimide film materials have excellent insulation resistance and may > be a > > > better choice in this situation. > > > > > > Regards, Joel > > > > > > > > > Joel S. Peiffer > > > 3M Electronic Materials Solutions Division > > > 3M Center, Building 201-1E-17 > > > St. Paul, MN 55144 > > > Tel: (651) 575-1464 > > > Cell: (612) 327-1983 > > > [log in to unmask] > > > > > > > > > > > > From: "Brooks, William" <[log in to unmask]> > > > To: <[log in to unmask]> > > > Date: 06/20/2014 10:11 AM > > > Subject: Re: [DC] z-axis separation for high voltage > > > Sent by: DesignerCouncil <[log in to unmask]> > > > > > > > > > > > > The epoxy/glass dielectric actually is spec'd at 750V per mil > insulation > > > resistance perpendicular to the layers according to Mil-P-13949/4C for > FR4 > > > glass epoxy laminated materials. So 1.3 mils minimum of material > > > perpendicular to the layers would net you 1KV insulation resistance > top to > > > bottom or internal layer to layer. > > > > > > Always give yourself some margin... The back side of the copper foil is > > > rough and can be 'spiked' on the laminated side for foil adhesion... > those > > > spikes can cause the spacing to be less than the minimum target spacing > > > you require when laminated. Also there can be bubbles or voids in the > > > materials that could occur right between your two high voltage > > > conductors... Unless you are trying to mimic a capacitance plane pair, > > > there is little or no reason to have the high voltage lines that close. > > > You don't want a short to occur internally in the board. Give yourself > a > > > buffer of at least a couple of additional layers of 2 mil prepreg on > > > internal layers. Just saying... :) Good design practice is to de-rate > by > > > 50%. > > > > > > I don't warranty sharing my observations... or advice... but if you > feel > > > the need to compensate me... I like microbrewery beers... the Darker > > > Belgian style... I'm not a big hops lover... though I like the hoppy > beers > > > too just not as much... :) > > > > > > > > > William Brooks, CID+ > > > Senior MTS (Contract) > > > 2747 Loker Ave West > > > Carlsbad, CA 92010-6603 > > > 760-930-7212 > > > Fax: 760.918.8332 > > > Mobile: 760.216.0170 > > > E-mail: [log in to unmask] > > > > > > > > > > > > -----Original Message----- > > > From: DesignerCouncil [mailto:[log in to unmask]] On Behalf Of > Jack > > > Olson > > > Sent: Friday, June 20, 2014 7:35 AM > > > To: [log in to unmask] > > > Subject: [DC] z-axis separation for high voltage > > > > > > maybe I'm having a "not enough coffee yet" morning, but I was asked how > > > much separation I need between layers for high voltage. > > > > > > We have a design that may have 1700V in several places. > > > Since we are looking at a clearance into the board, layer-to-layer I'm > > > pretty sure I can use the "internal" column B1 of Table 6-1 in IPC-2221 > > > (using Table 6-1 for z-axis was discussed in a committee meeting and no > > > one > > > disagreed) > > > > > > but the number I get for 1700V is = > > > (.25 mm for the first 500V) plus (.0025 mm for each of the other > 1200V, 3 > > > mm) > > > equals 3.25 mm > > > > > > For one thing, it already seems like I'm off-track because .25 for 500V > > > doesn't correspond very well with 3 mm for 1200V, but if you can't > trust > > > IPC..... well, let's not go there. > > > > > > My REAL question is that, although I'm safe using 3.25 mm, my board is > not > > > that thick! > > > Is there a smaller z-axis clearance that can be used for 1700V? across > > > typical FR4 material? > > > (we are using a RoHS compatible 170Tg /126) > > > > > > What's the MINIMUM layer spacing I can use for 1700V? > > > > > > thanks, > > > Jack > > > > > > > > > ______________________________________________________________________ > > > This email has been scanned by the Symantec Email Security.cloud > service. > > > For more information please contact helpdesk at x2960 or > [log in to unmask] > > > ______________________________________________________________________ > > > > > > > > > > --------------------------------------------------------------------------------- > > > DesignerCouncil Mail List provided as a free service by IPC using > LISTSERV > > > 16.0. > > > To unsubscribe, send a message to [log in to unmask] with following > text in > > > the BODY (NOT the subject field): SIGNOFF DesignerCouncil. > > > To temporarily stop/(restart) delivery of DesignerCouncil send: SET > > > DesignerCouncil NOMAIL/(MAIL) For additional information, or contact > Keach > > > Sasamori at [log in to unmask] or 847-615-7100 ext.2815 > > > > > > > --------------------------------------------------------------------------------- > > > > > > > > > > _____________________________________________________________________________ > > > Scanned by IBM Email Security Management Services powered by > MessageLabs. > > > For more information please visit http://www.ers.ibm.com > > > > > > This email is intended only for the use of the party to which it is > > > addressed and may contain information that is privileged, > confidential, or > > > protected by law. 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