Doesn't the board represent the board? In otherwords do you need coupons since the vias are external? Pete ----- Original Message ----- From: Denise Chevalier [mailto:[log in to unmask]] Sent: Monday, October 07, 2013 04:04 PM To: [log in to unmask] <[log in to unmask]> Subject: Re: [IPC-600-6012] a/b coupon design per 2221 Covering them would represent the board so it should be OK -----Original Message----- From: IPC-600-6012 [mailto:[log in to unmask]] On Behalf Of Jose A Rios Sent: Monday, October 07, 2013 4:01 PM To: [log in to unmask] Subject: Re: [IPC-600-6012] a/b coupon design per 2221 hi denise, we dont either, but if you have a design where all vias for a via represented on a coupon are covered with soldermask, we cover it with soldermask on the coupon as well. again only if ALL vias are covered with sm..... Joey Rios PWB & Process Quality Eng'r Endicott Interconnect Technologies 1093 Clark St. Endicott, NY 13760 Office: 607-755-5896; Cell: 607-206-3642 From: Denise Chevalier <[log in to unmask]> To: <[log in to unmask]>, Date: 10/07/2013 03:57 PM Subject: Re: [IPC-600-6012] a/b coupon design per 2221 Sent by: IPC-600-6012 <[log in to unmask]> We don't usually put solder mask on our A/B coupons - G coupons used for solder mask thickness, T coupon used for DFSM tented vias (usually covered by solder mask) -----Original Message----- From: IPC-600-6012 [mailto:[log in to unmask]] On Behalf Of Jose A Rios Sent: Monday, October 07, 2013 3:29 PM To: [log in to unmask] Subject: [IPC-600-6012] a/b coupon design per 2221 hi all, what is the proper configuration of an ipc a/b coupon for layer 1, relative to soldermask, given the 2 designs below?? for both, the total number of vias in the pwb is in the 10,000 - 11,000 range. - design 1: - 'b' holes only (no 'a' size holes), - all filled and cap plated, - on layer 1, 95% of those vias are covered with soldermask, 5% have soldermask openings hence exposed thru final finish, - on the bottom layer, 100% of the vias have soldermask openings - design 2: - same as above, except only 0.1% of the vias have soldermask openings on layer 1 leave a soldermask opening on layer 1 of the a/b's, or cover them with soldermask?? include both in the coupon design, at say a 3:4 ratio (given its an a/b theres 4 holes, 3 covered with sm, 1 uncovered)?? aabus?? Joey Rios PWB & Process Quality Eng'r Endicott Interconnect Technologies 1093 Clark St. Endicott, NY 13760 Office: 607-755-5896; Cell: 607-206-3642 ______________________________________________________________________ This email has been scanned by the Symantec Email Security.cloud service. For more information please contact helpdesk at x2960 or [log in to unmask] ______________________________________________________________________ ______________________________________________________________________ This email has been scanned by the Symantec Email Security.cloud service. For more information please contact helpdesk at x2960 or [log in to unmask] ______________________________________________________________________ ______________________________________________________________________ This email has been scanned by the Symantec Email Security.cloud service. For more information please contact helpdesk at x2960 or [log in to unmask] ______________________________________________________________________ ______________________________________________________________________ This email has been scanned by the Symantec Email Security.cloud service. For more information please contact helpdesk at x2960 or [log in to unmask] ______________________________________________________________________ ______________________________________________________________________ This email has been scanned by the Symantec Email Security.cloud service. For more information please contact helpdesk at x2960 or [log in to unmask] ______________________________________________________________________