Yes indeed Core Memory. X and Y plus the sense/inhibit wire. Pulse X and Y with no inhibit and the bit is a one. X and Y plus inhibit pulse is a zero. Read is destructive so every read cycle is stored in a memory based register, the memory follows with a write cycle to restore the location. Worked on systems using it for 12 years. 16K R/W memories, repaired all but the core stacks themselves. That was sent out to Plessey or DataRam. These systems also had a 2K wire ROM called a QuadriRom. We repaired everything including the wires on the QuadriRom. The system had to come up running after power failure and these were Non-volatile memory of their day Drew Meyer