Hi Steve and Mordechai, In the first picture it looks like the trace under the dielectric is superimposed on the pad. This looks like a condition called "telegraphing" where the copper conductors or pads are pressed into the dielectric and any copper in the outer layers leaving an impression that is visible upon inspection. The second picture is of a microvia. Note that the layer two copper is very thick compared to the dielectric. So the amount of "b-stage" dielectric is squeezed out between the conductors and the layer one copper during lamination. This condition is called "glass lock" or "glass crush". Sincerely, Paul Reid Program Coordinator PWB Interconnect Solutions Inc. 235 Stafford Rd., West, Unit 103 Nepean, Ontario Canada, K2H 9C1 613 596 4244 ext. 229 Skype paul_reid_pwb [log in to unmask] -----Original Message----- From: TechNet [mailto:[log in to unmask]] On Behalf Of Steve Gregory Sent: December 5, 2012 11:49 AM To: [log in to unmask] Subject: [TN] A PCB defect that is not specified by IPC Hi Mordechai, I have not seen anything like this before. I've posted your pictures so everyone else can see: http://stevezeva.homestead.com/Pad_Wrinkle.jpg http://stevezeva.homestead.com/Via_Xsection.jpg Could you share what the overall stack-up of this board was supposed to be and what prepreg thickness was used? Steve From: Mordechai Kirshenbaum Sent: Tuesday, December 04, 2012 3:16 PM To: [log in to unmask] Subject: A PCB defect that is not specified by IPC Hi Steve On routine visual inspection of an income PCB board we found a type of the defect that is not specified in any of the IPC standards (e.g IPC-A-600 Acceptability of Printed Boards). It looks like wrinkles on pads and conductors (see fig 1 in the attached file). We suspected that it was caused by thick copper conductor on the second layer (under the outer layer). We measured the copper and the dielectric thickness between the outer and the second layers and found that the copper thickness on the 2nd layer was relatively high (70 micro-meter), and the dielectric thickness lower than specified (only 50 microns). Have you seen similar defect? What is the reliability impact? Is it acceptable for class 3? Best regards Mordechai Kirshenbaum MOD, Israel P.S. please feel free to post this question on the technet forum. ______________________________________________________________________ This email has been scanned by the Symantec Email Security.cloud service. For more information please contact helpdesk at x2960 or [log in to unmask] ______________________________________________________________________ ______________________________________________________________________ This email has been scanned by the Symantec Email Security.cloud service. For more information please contact helpdesk at x2960 or [log in to unmask] ______________________________________________________________________