Victor, There are no specific IPC standards concerning the acceptance/guidelines for solid plated micro via voiding or for that matter specifically for the acceptance/guidelines for open micro via voiding. There are standards with regards to voiding in BGA, CSP and flip chip solder joints, but there is no specific mention one way or the other regarding microvias in the board pads. And I can't recall a single paper that claims that regular, centered, <25% sized microvias voids as causing a reliability problem in thermal cycling or shock testing. And I am assuming that the via is properly plated and there are no plating ionic fluids or resultant salts still present. Bev RIM -----Original Message----- From: TechNet [mailto:[log in to unmask]] On Behalf Of Victor Hernandez Sent: Wednesday, April 11, 2012 11:14 AM To: [log in to unmask] Subject: [TN] Micro Stacked Via, solid copper plating, voiding Fellow TechNetters: I have searched for IPC documentation and/or Inductry Standards concerning the acceptance/guidelines for solid plated micro via voidibg. I did not locate any. Can someone confirm that and/or provided guidance as to which document covers that anomaly. Victor, ______________________________________________________________________ This email has been scanned by the Symantec Email Security.cloud service. For more information please contact helpdesk at x2960 or [log in to unmask] ______________________________________________________________________ ______________________________________________________________________ This email has been scanned by the Symantec Email Security.cloud service. For more information please contact helpdesk at x2960 or [log in to unmask] ______________________________________________________________________