Maybe the customer does not agreed with such explain unless we have enough objective evidence.

 

Thanks and best regards,

 

Justin

 

 

I see that the IPC concern on the function, e.g. blister, void may have problem in flakes by tape test

And if the patches are not solder flux, oil and cleaning agent, the risk of S/M peel off after assembling is very low.

 

So they should be acceptable.

 

 

Thanks Joseph. They are gone through the reflow process and passed to FPT/FCT test and no blistering and/or void was found. However, they are still violated the IPC standard clause 10.7.2 (Defect –Class 2, 3).

What’s your comment?

 

Thanks and best regards,

 

Justin

 

 

Justin,

If the stuffs under the S/M didn’t enlarge, swell or causing S/M peel-off after reflow, it should be acceptable,

From the photos, it seems that they are not blister and void.

 

In the S/M process, the copper surface is fresh and may easy be oxides or show dark pad if they hold in the line for a longer time. These patches will appear only after the S/M curing.

 

Ask your PCB supplier to provide you the reliability test result or go through the reflow process with them.

 

 

 

 

Thanks Joseph. So, is this s/b reject as per IPC-A-610E standard clause 10.7.2?

[log in to unmask]">

 

Thanks and best regards,

 

Justin

 

 

Cleanliness problem in S/M coating process.

 

 

Hi All,

 

Would you please share with me your value experience in solder mask coating? The photo as below:

[log in to unmask]" v:shapes="_x0000_s1032">[log in to unmask]" v:shapes="_x0000_s1031">[log in to unmask]">

[log in to unmask]" v:shapes="_x0000_s1028">It seems to me that it s/b rejected as per IPC-A-610E standard clause 10.7.2.

 

Thanks in advance!

 

Best regards,

 

Justin

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