Rights folks! I'm designing a new surface mount device which originally started off as 5 X 5 square. It has 25 I/Os. It's LGA is a 5 X 5 array of 0.60 diameter pads on a 1 X 1 pitch. The device has now increased in size to 7.5 X 7.5. Now, do I increase the LGA spacing to cover the increased area again or do I stay with what fitted on the 5 X 5 device? I'm inclined to stick with the original LGA as I believe that the stress analysis will tell me that the smaller grid will have lower stresses in the SJs than the bigger grid. Are there any practical reasons for maximising grid size? Regards, -- Eric Christison Consumer& Micro group Imaging Division STMicroelectronics (R&D) Ltd 33 Pinkhill Edinburgh EH12 7BF United Kingdom Tel: +44 (0)131 336 6165 Fax: + 44 (0)131 336 6001 The contents of the email are ST confidential. ______________________________________________________________________ This email has been scanned by the MessageLabs Email Security System. For more information please contact helpdesk at x2960 or [log in to unmask] ______________________________________________________________________ --------------------------------------------------- Technet Mail List provided as a service by IPC using LISTSERV 16.0 To unsubscribe, send a message to [log in to unmask] with following text in the BODY (NOT the subject field): SIGNOFF Technet To temporarily halt or (re-start) delivery of Technet send e-mail to [log in to unmask]: SET Technet NOMAIL or (MAIL) To receive ONE mailing per day of all the posts: send e-mail to [log in to unmask]: SET Technet Digest Search the archives of previous posts at: http://listserv.ipc.org/archives For additional information, or contact Keach Sasamori at [log in to unmask] or 847-615-7100 ext.2815 -----------------------------------------------------