Lars, You have received some very good comments thus far. Wasn't sure if you were asking for something more basic, so here goes. Depending upon the application and cost, it is generally the norm to perform as much testing as possible in the wafer [un-diced] format. In wafer form, we handle all dice at the same time and all are uniformly spaced. When diced/sawn, the sawn wafer is mounted on a flexible membrane which is mounted on a larger [wafer] frame. Basic die X, Y, Theta location is still very close in the sawn wafer, but some membrane stretch can occur depending on die size and how the sawn wafer has been handled. It is more difficult to test some device types after dicing. Specifically, devices having a backside contact [diode, LED, transistos] with no electrically equivalent top-side pad are generally probed prior to dicing. Not a good idea to probe up through the membrane which the sawn wafer is adhered to. Would involve probes from above and below. Would likely dislodge the device from the membrane - since these devices are typically physically small as well. The un-diced wafer is generally placed upon a moveable 'chuck' which allows the wafer to be indexed in the X, Y, and Theta axes under a probe card. One or both [chuck and/or probe card] will move in the Z axis [up/down] to allow contact between probe and device. A 'probe card' is set up for each device topography/bond pad layout being tested. Each probe card has an individual probe targeted to each individual bonding pad/probe pad - one probe, one pad. Many probe cards have hundreds of very tiny probes. Once Theta is established and initial X,Y coordinates established, the equipment generally automatically steps across the entire wafer in a serpentine pattern. The specific test 'chuck' may allow for/control specific incident light, absence of light, controlled temperature - super/sub ambient [and atmosphere to prevent condensation] and many other items. Testing high frequency devices is always a challenge getting the signals into and out of the device under test without corruption. Some devices can not be adequately tested at wafer probe. As you can visualize, due to the small physical size of the bond pads and close physical spacing, setting up the probe card is not a trivial undertaking. Assuring all the probe tips are in the same horizontal plane so as to nearly simultaneously contact the bond pads at the same time is also another important consideration [some 'wiping' of the bond pad does take place, but one always attempts to minimize the surface damage caused by movement of the probe across the surface of the bond pad]. Extensive damage to the bond pad can introduce wire bonding problems, or wire bond reliability issues. Physically probing individual, loose, devices, is a definite challenge [refer to Inge's comment] but is occasionally done for specialized devices or applications {takes $$$$} Devices can be sorted/graded at wafer probe. Besides just good and bad, there can be those devices which have parametric shifts. We call this 'binning'. In the olden days, one could use different color inks do denote which 'bin' the device fell into. For the most part, this is all done electronically now, with a wafer map being generated. The wafer map provides the X-Y coordinate of the device and the test results, thereby allowing the die attach operation to 'pick and choose' which devices to place. None of the die need to be inked if the system is working properly. Bottom line being that one normally does as much testing as possible in wafer form, but as with all generalities, there are exceptions. Hope you received the insight you were seeking. Steve Creswick http://www.linkedin.com/in/stevencreswick -----Original Message----- From: TechNet [mailto:[log in to unmask]] On Behalf Of Lars Wallin Sent: Tuesday, January 25, 2011 8:23 AM To: [log in to unmask] Subject: [TN] TEST OF BARE DIE CIRCUITS Hello Technet, Can anyone short describe which sort of test methods are used for testing bare die circuits? Are they tested on the Waffer level or after cutting. Best Regards Lars Wallin IPC European Representative Location: Stockholm, Sweden Phone: +46 8 26 10 07 Mobile: +46 70 212 74 39 Email: [log in to unmask]<mailto:[log in to unmask]> --------------------------------------------------- Technet Mail List provided as a service by IPC using LISTSERV 15.0 To unsubscribe, send a message to [log in to unmask] with following text in the BODY (NOT the subject field): SIGNOFF Technet To temporarily halt or (re-start) delivery of Technet send e-mail to [log in to unmask]: SET Technet NOMAIL or (MAIL) To receive ONE mailing per day of all the posts: send e-mail to [log in to unmask]: SET Technet Digest Search the archives of previous posts at: http://listserv.ipc.org/archives Please visit IPC web site http://www.ipc.org/ContentPage.aspx?Pageid=E-mail-Forums for additional information, or contact Keach Sasamori at [log in to unmask] or 847-615-7100 ext.2815 ----------------------------------------------------- ______________________________________________________________________ This email has been scanned by the MessageLabs Email Security System. For more information please contact helpdesk at x2960 or [log in to unmask] ______________________________________________________________________ --------------------------------------------------- Technet Mail List provided as a service by IPC using LISTSERV 15.0 To unsubscribe, send a message to [log in to unmask] with following text in the BODY (NOT the subject field): SIGNOFF Technet To temporarily halt or (re-start) delivery of Technet send e-mail to [log in to unmask]: SET Technet NOMAIL or (MAIL) To receive ONE mailing per day of all the posts: send e-mail to [log in to unmask]: SET Technet Digest Search the archives of previous posts at: http://listserv.ipc.org/archives Please visit IPC web site http://www.ipc.org/ContentPage.aspx?Pageid=E-mail-Forums for additional information, or contact Keach Sasamori at [log in to unmask] or 847-615-7100 ext.2815 -----------------------------------------------------