On Thu, Dec 16, 2010 at 9:34 AM, Silicon Valley Chapter - IPC Designers Council <[log in to unmask]> wrote:

Silicon Valley Chapter of the IPC Designers Council

There are less than 15 seats left... RSVP today!

Wednesday, January 12, 2011

11:30am to 2:30pm

Cadence Design Systems in San Jose

Designing a Multilayer PCB Stackup to Optimize Manufacturability, Reliability and Signal Integrity

Lee Ritchey

Who is considered to be one of the industry´s premier authorities on high-speed PCB and system design. He conducts on-site private training courses for high technology companies and also teaches courses for UC Berkeley´s extension program as well as industry trade shows and technical conferences. In addition, he provides consulting services to top manufacturers of Internet and server products. Ritchey holds a B.S.E.E. degree from California State University, Sacramento where he graduated as outstanding senior.

Meeting will be hosted by

Cadence Design Systems

EBC, Building 9

2655 Seely Ave

San Jose, CA 95134

Seating is limited! RSVP is required.

Reply to [log in to unmask]" rel="nofollow" target="_blank">[log in to unmask]

Bob McCreight, C.I.D.
IPC Designers Council
Silicon Valley Chapter
(President)

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