Revision A to IPC-TM-650, Method 2.5.7.2, Dielectric Withstanding Voltage (HiPot Method) - Thin Dielectric Layers for Printed Circuit Boards (PCBs) is now available. 

 

The dielectric withstanding voltage test (Hipot test) consists of the application of a voltage higher than the operating voltage for a specific time across the thickness of the test specimen’s dielectric layer. This is used to prove that a printed board can operate safely at its rated voltage and withstand momentary voltage spikes due to switching, surges, and other similar phenomena. Although this test is similar to a voltage breakdown test, it is not intended for this test to cause insulation breakdown. Rather, it serves to determine whether the test specimen’s layers have adequate withstanding voltage. This document is applicable to thin dielectric materials such as those defined by the IPC-4821 embedded capacitor material specification.

 

The test method can be downloaded for free in .pdf format at the IPC-TM-650 Test Methods Manual website, located at http://www.ipc.org/ContentPage.aspx?pageid=Test-Methods