Ken, I am only talking about a copper pour on the top side of a PCB under a BGA. I don't think a top side copper pour is a HDI concept. Where did you get this info? We both know top pours impacts fan out, that may or not be important. But my comment was WHY. When any solder mask chip or scratches would be a good source for shorts. Handling or rework can cause these chips and scratches. Those would be reasons for no top pour. My argument is that copper pour on the top offers no apparent HDI emissions improvement. I could be wrong but I have yet to hear a reason for yea or nay. The electrostatic shield reason might be possible in some cases. A fast clock fan out that passes near an set of pins for an asynchronous PLL would be a perfect example. This is near field and electrostatic shield are real important. (I design some transformers, shields are real important.) If you top copper pour is your primary GND plane and PWR is somewhere below, then you probably increased your problems with EMI. Bob Kondner -----Original Message----- From: TechNet [mailto:[log in to unmask]] On Behalf Of Kenneth Wood Sent: Wednesday, September 16, 2009 4:42 PM To: [log in to unmask] Subject: Re: [TN] Ground Pour Under BGA But that is my point...can you prove to me that HDI concepts do not help emissions? Your previous posts seem to imply that they do not. Ken -----Original Message----- From: TechNet [mailto:[log in to unmask]] On Behalf Of Robert Kondner Sent: Wednesday, September 16, 2009 4:35 PM To: [log in to unmask] Subject: Re: [TN] Ground Pour Under BGA Hi, I guy walk into a room and sprays something into the air. Someone asks what it is. The first guy says "Elephant Repeller" Second guy says there are elephants around here. First guy says "See, It Works". As Lee Ritchey says about electronic design "If you can not prove it don't say it." What you are suggesting may or may not be important but as of right now neither you nor I know for sure. This is no way to define a process. Relying on New World Assumptions is no different from Old World Assumptions, right? Bob Kondner -----Original Message----- From: TechNet [mailto:[log in to unmask]] On Behalf Of Kenneth Wood Sent: Wednesday, September 16, 2009 4:21 PM To: [log in to unmask] Subject: Re: [TN] Ground Pour Under BGA Proof? I have designed boards that have to pass -190dB EMI (MRI equipment)...there are certain things the make big differences. GND planes, edge plating and internal routing = passing emissions. Relying on old world assumptions = not passing emissions. Ken -----Original Message----- From: TechNet [mailto:[log in to unmask]] On Behalf Of Robert Kondner Sent: Wednesday, September 16, 2009 11:24 AM To: [log in to unmask] Subject: Re: [TN] Ground Pour Under BGA Ken, I don't know your total stack up but having internal layers between GND and PWR planes is waste of planes. Plane pairs are SO much more effective when they are very close. Putting routing layers in between is not good. People sometimes imaging they are putting traces inside a faraday cage when they do that but it is a false assumption. Bob Kondner -----Original Message----- From: TechNet [mailto:[log in to unmask]] On Behalf Of Kenneth Wood Sent: Wednesday, September 16, 2009 10:27 AM To: [log in to unmask] Subject: Re: [TN] Ground Pour Under BGA You're not routing below the GND plane, you are routing below the PWR plane(s)...maybe on layer 3 or 4 or 5 etc... Ken Saturn PCB Design, Inc. www.saturnpcb.com -----Original Message----- From: TechNet [mailto:[log in to unmask]] On Behalf Of Robert Kondner Sent: Wednesday, September 16, 2009 10:23 AM To: [log in to unmask] Subject: Re: [TN] Ground Pour Under BGA Hi, But that still makes your top GND plane look like Swiss Cheese. When I think of routing below that "Swiss Chese" and the return currents moving around all thoses holes it gives me the Creeps. Where did I go wrong? Bob Kondner -----Original Message----- From: TechNet [mailto:[log in to unmask]] On Behalf Of Kenneth Wood Sent: Wednesday, September 16, 2009 10:17 AM To: [log in to unmask] Subject: Re: [TN] Ground Pour Under BGA Keep in mind that on HDI designs you are not JUST adding a few micro vias and pouring GND on the top layer...you are using via-in-pad on all devices so to try and minimize top side pour cuts. Also, you are routing as many nets on internal layers as possible. The top layer GND is not usually the only GND plane too, there is usually an internal plane to back up the top layer. This does reduce EMI significantly, shorter runs and external shielding works. Ken Saturn PCB Design, Inc. www.saturnpcb.com -----Original Message----- From: TechNet [mailto:[log in to unmask]] On Behalf Of Robert Kondner Sent: Wednesday, September 16, 2009 10:07 AM To: [log in to unmask] Subject: Re: [TN] Ground Pour Under BGA Ken, With all the BGA pads and possible vias I don't see how a top side can have a better mesh of copper paths than an internal layer. I would think a poor copper mesh plane would be a generator of large GND return loops. Aka antennas. As for a GND plane being a few mils closer to the BGA and this reducing EMI, that sounds like hog wash. Consider that conductor lengths from a ball to chip is probably about 1/2 inch at times. How is adding 10 mils going to affect anything? I am open to Hog Wash ideas but they need to be well defined. Thanks, Bob Kondner -----Original Message----- From: TechNet [mailto:[log in to unmask]] On Behalf Of Kenneth Wood Sent: Wednesday, September 16, 2009 9:54 AM To: [log in to unmask] Subject: Re: [TN] Ground Pour Under BGA It is an technique used in HDI designs that utilize micro vias. Top layer is GND and layer 2 can be a power layer. It also helps with EMI. Ken Saturn PCB Design, Inc. www.saturnpcb.com -----Original Message----- From: TechNet [mailto:[log in to unmask]] On Behalf Of Robert Kondner Sent: Wednesday, September 16, 2009 8:42 AM To: [log in to unmask] Subject: Re: [TN] Ground Pour Under BGA Hi, What would be the goal of placing atop side GND plane under the BGA? Low Z Gnd return? Electrostatic shield? Having a plane under the BGA vs another layer is not going to make a difference in plane Z. Sounds like a good chance of creating shorts if the solder mask chips or is damaged during rework. Bob Kondner -----Original Message----- From: TechNet [mailto:[log in to unmask]] On Behalf Of Guy Ramsey Sent: Wednesday, September 16, 2009 7:43 AM To: [log in to unmask] Subject: Re: [TN] Ground Pour Under BGA IPC 7095, BGA Technology by Lau. -----Original Message----- From: TechNet [mailto:[log in to unmask]] On Behalf Of Toby Carrier Sent: Tuesday, September 15, 2009 8:45 PM To: [log in to unmask] Subject: [TN] Ground Pour Under BGA Hello all, Is it a good idea to create a top layer ground flood under a BGA package? I am guessing that the fanout will not allow much area for the ground pour, am I correct in thinking so? Does anyone have any good reference info on this topic? Also, if you don't have a ground pour under the BGA, how will that affect the impedance control of the traces going to the BGA ball? Thanks for the help, Toby --------------------------------------------------- Technet Mail List provided as a service by IPC using LISTSERV 15.0 To unsubscribe, send a message to [log in to unmask] with following text in the BODY (NOT the subject field): SIGNOFF Technet To temporarily halt or (re-start) delivery of Technet send e-mail to [log in to unmask]: SET Technet NOMAIL or (MAIL) To receive ONE mailing per day of all the posts: send e-mail to [log in to unmask]: SET Technet Digest Search the archives of previous posts at: http://listserv.ipc.org/archives Please visit IPC web site http://www.ipc.org/contentpage.asp?Pageid=4.3.16 for additional information, or contact Keach Sasamori at [log in to unmask] or 847-615-7100 ext.2815 ----------------------------------------------------- --------------------------------------------------- Technet Mail List provided as a service by IPC using LISTSERV 15.0 To unsubscribe, send a message to [log in to unmask] with following text in the BODY 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