Victor, Double check TM 2010, it has a little more die attach detail. I was suggesting the FC section thinking the back-side the device being like a FC - basically non-functional bulk. - That would not be a good analogy for your application. When you say "power", the fur on the back of my neck immediately goes up and I get really scared when you even hint at the word 'crack' near the attach surface. I have power cycled devices before and had the top of the chip crack entirely through - leaving the entire base of the device attached to the substrate. I can not imagine having done this with a device that may have been cracked in the first place. I vote that you play it entirely safe if there are cracks. Scallops could be a bit safer, but still would like to know where they are coming from to make me sleep better in the evenings. Steve C -----Original Message----- From: [log in to unmask] [mailto:[log in to unmask]] Sent: Wednesday, August 05, 2009 11:36 AM To: [log in to unmask]; [log in to unmask] Subject: RE: [TN] die base chip outs / fractures Steve, Thank you for sharing. The current revision is G and I have B. I reviewed the current TM 2017 and I didn't see much as far anomalies, cracks/fractures of the bulk silicon at the bonding area. The device is a power diode package, 2x, per package, To266. It is not a flip chip application. Victor, -----Original Message----- From: TechNet [mailto:[log in to unmask]] On Behalf Of Steven Creswick Sent: Wednesday, August 05, 2009 8:20 AM To: [log in to unmask] Subject: Re: [TN] die base chip outs / fractures Victor, I am not sure what the IPC equivalent to MIL-STD-883 would be, but if you refer to 883, TM 2010 - internal visual - monolithic, or TM 2017 internal visual - hybrid you may find what you are looking for. My recollection is that TM 2010 may provide the most info [para 3.1.3] although we were mostly concerned about chip-outs at the upper edge of the chip, nearer to the active region. You might consider the section on flip chips for info as well. If the chips are diced with a diamond saw, one seldom [if ever] sees chipping along the bottom edge of the die unless there has been mis-handling of the sawn wafer while still on the frame. Mainly, don't want cracks going in the direction of the active region of the chip - [personally, don't want to see cracks AT ALL - especially, if you can see them with a low-power scope, etc]. We would not want to see loose bits of Si rattling around inside a sealed hybrid. If over-molded, it is not so likely to move anywhere... Interested in further detail of the chipping you are seeing. You should be able to down-load MIL-STD-883G from http://assist.daps.dla.mil/online/start/ Once you get the user sign-on info. It is a ~6 Mb file Steve -----Original Message----- From: TechNet [mailto:[log in to unmask]] On Behalf Of Victor Hernandez Sent: Wednesday, August 05, 2009 8:16 AM To: [log in to unmask] Subject: [TN] die base chip outs / fractures Fellow TechNetters: Is there an IPC documents pertaining to acceptance of anomalies with die. I am see small cracks/chip out at the die to die attach region. How much chip out/ crack is allowed? Victor, --------------------------------------------------- Technet Mail List provided as a service by IPC using LISTSERV 15.0 To unsubscribe, send a message to [log in to unmask] with following text in the BODY (NOT the subject field): SIGNOFF Technet To temporarily halt or (re-start) delivery of Technet send e-mail to [log in to unmask]: SET Technet NOMAIL or (MAIL) To receive ONE mailing per day of all the posts: send e-mail to [log in to unmask]: SET Technet Digest Search the archives of previous posts at: http://listserv.ipc.org/archives Please visit IPC web site http://www.ipc.org/contentpage.asp?Pageid=4.3.16 for additional information, or contact Keach Sasamori at [log in to unmask] or 847-615-7100 ext.2815 ----------------------------------------------------- --------------------------------------------------- Technet Mail List provided as a service by IPC using LISTSERV 15.0 To unsubscribe, send a message to [log in to unmask] with following text in the BODY (NOT the subject field): SIGNOFF Technet To temporarily halt or (re-start) delivery of Technet send e-mail to [log in to unmask]: SET Technet NOMAIL or (MAIL) To receive ONE mailing per day of all the posts: send e-mail to [log in to unmask]: SET Technet Digest Search the archives of previous posts at: http://listserv.ipc.org/archives Please visit IPC web site http://www.ipc.org/contentpage.asp?Pageid=4.3.16 for additional information, or contact Keach Sasamori at [log in to unmask] or 847-615-7100 ext.2815 ----------------------------------------------------- --------------------------------------------------- Technet Mail List provided as a service by IPC using LISTSERV 15.0 To unsubscribe, send a message to [log in to unmask] with following text in the BODY (NOT the subject field): SIGNOFF Technet To temporarily halt or (re-start) delivery of Technet send e-mail to [log in to unmask]: SET Technet NOMAIL or (MAIL) To receive ONE mailing per day of all the posts: send e-mail to [log in to unmask]: SET Technet Digest Search the archives of previous posts at: http://listserv.ipc.org/archives Please visit IPC web site http://www.ipc.org/contentpage.asp?Pageid=4.3.16 for additional information, or contact Keach Sasamori at [log in to unmask] or 847-615-7100 ext.2815 -----------------------------------------------------