That'd be great in this application--the thicker the copper, the better. This is a DC application, not RF. Something I've wondered about is if stitching layers together helps. I mean, in this case I have to go all of 7mm, from a thro-hole (wire to PCB) to an SMT lead (the IC itself). It seems most of the current will flow on just one layer, no matter how many via's I use to stitch layers together. Or does adding many via's in the path of the current add (essentially) copper thickness, and not represent a necking down of the current path as I fear? I've been keeping via's from being too close to the SMT leads, for fear of necking causing resistance increases. Shawn Upton, KB1CKT Test Engineer Allegro MicroSystems, Inc [log in to unmask] 603.626.2429/fax: 603.641.5336 -----Original Message----- From: TechNet [mailto:[log in to unmask]] On Behalf Of Roger Stoops Sent: Thursday, July 30, 2009 3:42 PM To: [log in to unmask] Subject: Re: [TN] Via plating question And don't forget that 2 mils in vias translates to at least 2 mils on the outer layers... Is it possible to double-up on vias if impedance is an issue? --------------------------------------------------- Technet Mail List provided as a service by IPC using LISTSERV 15.0 To unsubscribe, send a message to [log in to unmask] with following text in the BODY (NOT the subject field): SIGNOFF Technet To temporarily halt or (re-start) delivery of Technet send e-mail to [log in to unmask]: SET Technet NOMAIL or (MAIL) To receive ONE mailing per day of all the posts: send e-mail to [log in to unmask]: SET Technet Digest Search the archives of previous posts at: http://listserv.ipc.org/archives Please visit IPC web site http://www.ipc.org/contentpage.asp?Pageid=4.3.16 for additional information, or contact Keach Sasamori at [log in to unmask] or 847-615-7100 ext.2815 -----------------------------------------------------