I need advise in a case where the outer layers have blind Via-in-pad (BGAs) from lay14 to 13 and 1 to 2. Those were plated and filled-up with non-conductive. What is the acceptable level for non-uniformity of the capping? I have 4 pictures to shareat following address: http://www.pcbspecialist.com/PCBpics/RJ_00157.jpg http://www.pcbspecialist.com/PCBpics/RJ_00158.jpg http://www.pcbspecialist.com/PCBpics/RJ_00159.jpg http://www.pcbspecialist.com/PCBpics/RJ_00160.jpg From the IPC-6016 (HDI) I got relevant : 3.5.3.2 Surface Mount Lands (Area for attachment such as solder, TAB, conductive adhesive) Defects such as nicks, dents, and pinholes along the edge of the land (length or width) shall not exceed that identified in the respective slash sheets. Slash sheet says "As Specified" and there is no customer requirement.. 3.6.4 Filled Vias Buried vias and/or buried microvias shall be filled and inspected in accordance with the procurement documentation. Blind vias on the external layers do not have any fill requirements. The PCBs have been manufactured as Class 2. What is your opinion? Is there more documents I could base on for acceptability? Thank you for your help Meilleures salutations Very Best Regards Roland --------------------------------------------------- Technet Mail List provided as a service by IPC using LISTSERV 15.0 To unsubscribe, send a message to [log in to unmask] with following text in the BODY (NOT the subject field): SIGNOFF Technet To temporarily halt or (re-start) delivery of Technet send e-mail to [log in to unmask]: SET Technet NOMAIL or (MAIL) To receive ONE mailing per day of all the posts: send e-mail to [log in to unmask]: SET Technet Digest Search the archives of previous posts at: http://listserv.ipc.org/archives Please visit IPC web site http://www.ipc.org/contentpage.asp?Pageid=4.3.16 for additional information, or contact Keach Sasamori at [log in to unmask] or 847-615-7100 ext.2815 -----------------------------------------------------