Jack,

  I am a "One Man Band" here. I am an EE by training and experience but I
also do PCB design and I have a couple of small products. I am a big fan of
ICT and I own a Teradyne Z1820 for which I also write the test programs.

  I add 35mil square test points in SPECCTRA with some hand finishing. For
low Z nets I setup the required points for the 4 wire tests. 

  Getting 35mil square is difficult some get turned down to 30 or 25.

  In the end all test points are defined by me before the PCB is finished. I
typically do this after the first 100 boards when I know the requirements
and design are all defined, understood and correct.

Bob Kondner



-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Jack Olson
Sent: Friday, July 10, 2009 1:20 PM
To: [log in to unmask]
Subject: [TN] ICT and SolderMask

I'm wading into deeper water these days...

(As a circuit board designer,)
We have vias that can be used as test points that are 40mil pads
with 13mil holes. Normally we would like mask to cover most of
the pad but not the hole, so we have an 18mil aperture on the
mask layer.
Whenever these vias are USED as test points, we have to open
up the mask and leave them fully exposed.

The problem is, no matter how hard we try to generate test point
data, during test fixture development they end up inserting a few
more, moving them around, etc. which means we either have to
modify the mask or leave ALL of them exposed. to minimize the
possibility of solder shorts, we are discussing now to modify the
mask instead of leaving them all open, preferably without having
to change the board revision.

Has anyone else had to deal with this situation?

I would be interested to know if you are generating test point data,
Is it really good enough?
Or,
Are they modifying it in production?
If so, do they make an effort to get the TP changes back to you?

the man with the mask,
Jack

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