Just to keep in mind whether it applies directly to the situation under discussion or not, 1. It is quite possible and probable to develop a void-free process, so the consideration of voided material acceptance should be an exception and not a norm. 2. Voids always have the potential to cause problems whether reported in the literature or not. Below are comments from a coworker here who is a reliability person: << I think it's pretty well understood that if you have significant voiding around underfilled solder joints the solder will extrude into the void under temperature cycling. The joint shape thus becomes distorted, and the degree of distortion depends on the size and shape of the void and the number of cycles imposed. Distorted solder joints are less reliable than pristine, barrel-shaped joints due to stress concentrations. I doubt that in a high-reliability application space that any customer would accept even 50% voiding around a joint, much less a void spanning two joints. Standoff heights of 100 microns or more can be underfilled without voids; this is not difficult with a little process development. BGA joints are roughly that size or larger, but flip chip are often smaller, of course. Defining a good dispense pattern for flip chip or BGA is often a black art that takes some experimentation in the lab, as you know. >> He was with Motorola for a number of years and got the following comments from there: << My amigo at Freescale tells me they generally subscribe to a JEDEC C-SAM inspection standard for flip chips. The standard states something like no more than 5-10% total die area can be void, with NO voids allowed in the last row of joints at the die edge (since they fail first in temp cycle and drop). He couldn't remember if the actual number was 5% or 10%. He is not aware of a similar standard for BGA joints, but they apply the same 5-10% rule with no voids allowed at die edge or package edge (where failures occur first). He thought the JEDEC standard might be free, if you're interested. >> My personal experience is that a void free process can be developed and that in flip chips voids cause stress at the edges and chip damage is possible at the edges of the void. Chip damage also is possible when the edge of the chip is covered partially. -----Original Message----- From: TechNet [mailto:[log in to unmask]] On Behalf Of Bev Christian Sent: Thursday, July 09, 2009 3:10 PM To: [log in to unmask] Subject: [TN] More Underfill Discussion TechNetters, Well I have been shopping to Class 2 people the draft we all built here on TechNet of a standard for underfill workmanship. Some are saying they can't live with voids that only go 50% around the perimeter of a solder ball, they want more leeway. They also say they want to allow voids connecting solder balls. Now I put in the prohibition of the latter because of the statement in the J-STD-030 "Guideline for Selection and Application of Underfill Material for Flip Chip and Other Micropackages", where it talks about unequal stresses put on the solder balls when they is not 100 underfill coverage around each and every ball. My questions to you are: 1) What is the physical evidence behind that statement in 030? 2) What was the magnitude of the deformation? 3) How long did it take? My reason for the last question is if it takes 9 years for significant, reliability impairing deformation to occur in a 20 year life product, that is real bad. But if it happens in the products with a 2 to 3 year life product, why should we care? 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