Hi Jack,
 
Our test point pads are usually specific...we don't tend to unmask the vias for this.
The data / coordinates are contained within the smd pick and place file with their own unique identifier. They basically extract this data afterwards and modify it as needed.
Together we decide on the required test points beforehand (usually they exagerate and add points that are not needed later) and luckily there have not been many modification requests afterwards. If there are they lets us know via pilot run reports etc.
 
Sorry it's not directly answering your question...
 
Paul.

________________________________

From: DesignerCouncil [mailto:[log in to unmask]] On Behalf Of Jack Olson
Sent: venerd́ 10 luglio 2009 19.18
To: [log in to unmask]
Subject: [DC] ICT and SolderMask


I'm wading into deeper water these days...
 
We have vias that can be used as test points that are 40mil pads
with 13mil holes. Normally we would like mask to cover most of
the pad but not the hole, so we have an 18mil aperture on the 
mask layer.
Whenever these vias are USED as test points, we have to open
up the mask and leave them fully exposed.
 
The problem is, no matter how hard we try to generate test point
data, during test fixture development they end up inserting a few
more, moving them around, etc. which means we either have to 
modify the mask or leave ALL of them exposed. We are discussing
now to modify the mask to minimize the possibility of solder shorts, 
preferably without having to change the board revision.
 
Has anyone else had to deal with this situation?
 
I would be interested to know if you are generating test point data,
Is it really good enough? 
Or,
Are they modifying it in production?
If so, do they make an effort to get the TP changes back to you?
 
the man with the mask,
Jack
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