Hello Chris, Thank you for the input. It is sepaparation/delamination, really. It is inside the substrate between the outer layer and the adjacent inner layer, not land cratering or land lifted, I'm sure of that. After thermal cycling test, the separation/delamintion occurred inside pcb board, so I should check on IPC 6012B for acceptance, am I right? With the acceptance spec definition on IPC 6012B section 3.3.2.3 and section 3.6.2.5, I'm not sure if that separation/delamination is acceptable or not. Thank you all for inputs. Have a nice day. Charming Chan -----邮件原件----- 发件人: Chris Mahanna [mailto:[log in to unmask]] 发送时间: 2009年6月2日 23:21 收件人: TechNet E-Mail Forum; Charming Chan 主题: RE: [TN] Separation/Delamination Acceptance Spec. Charming Chan, You've got "land cratering". Land cratering is not in 6012. Thermal cycling is not in 6012. Hence the ambiguities. Land cratering is definitely bad. You need to look at the SMT reliability documents. Chris -----Original Message----- From: TechNet [mailto:[log in to unmask]] On Behalf Of Charming Chan Sent: Tuesday, June 02, 2009 11:06 AM To: [log in to unmask] Subject: [TN] Separation/Delamination Acceptance Spec. Hello All, We performed thermal cycling test on a PCBA for reliability verification and found separation/delamination under a SMD land when checking micro section for structural integrity. The requirements about separation/delamination in IPC-6012B are as follows. I'm quite confused about the definition on section 3.3.2.3 and section 3.6.2.5, so I am asking a favor here to make sure if that separation/delamination after thermal cycling test is acceptable or not. Thank you all for inputs. ---------------------------------------------------------------------------- ---------------------------------------------------------------------- In spec IPC-6012B, section 3.3.2.3 says that "Delamination and blistering is acceptable for all classes of end product provided the area affected by imperfections does not exceed 1% of the board area on each side and does not reduce the spacing between conductive patterns below the minimum conductor spacing. There shall be no propagation of imperfections as a result of thermal testing that replicates future assembly processes. For Class 2 and 3, the blister or delamination shall not span more than 25% of the distance between adjacent conductive patterns. Refer to IPC-A-600 for more information." While, section 3.6.2.5 , in IPC-6012B, says that "Delamination or Blistering For Class 2 and 3 there shall be no evidence of delamination or blistering. For Class 1, if delamination or blistering is present, evaluate the entire board per 3.3.2.3." ---------------------------------------------------------------------------- ---------------------------------------------------------------------- By the way, the thermal cycling test attributes as follows. 10 minutes dwell time at 0C low temp, 10 minutes dwell time at 100C high temp, 10 C/minute thermal gradient, 500 cycles. Thanks & Best Regards Charming Chan --------------------------------------------------- Technet Mail List provided as a service by IPC using LISTSERV 15.0 To unsubscribe, send a message to [log in to unmask] with following text in the BODY (NOT the subject field): SIGNOFF Technet To temporarily halt or (re-start) delivery of Technet send e-mail to [log in to unmask]: SET Technet NOMAIL or (MAIL) To receive ONE mailing per day of all the posts: send e-mail to [log in to unmask]: SET Technet Digest Search the archives of previous posts at: http://listserv.ipc.org/archives Please visit IPC web site http://www.ipc.org/contentpage.asp?Pageid=4.3.16 for additional information, or contact Keach Sasamori at [log in to unmask] or 847-615-7100 ext.2815 ----------------------------------------------------- --------------------------------------------------- Technet Mail List provided as a service by IPC using LISTSERV 15.0 To unsubscribe, send a message to [log in to unmask] with following text in the BODY (NOT the subject field): SIGNOFF Technet To temporarily halt or (re-start) delivery of Technet send e-mail to [log in to unmask]: SET Technet NOMAIL or (MAIL) To receive ONE mailing per day of all the posts: send e-mail to [log in to unmask]: SET Technet Digest Search the archives of previous posts at: http://listserv.ipc.org/archives Please visit IPC web site http://www.ipc.org/contentpage.asp?Pageid=4.3.16 for additional information, or contact Keach Sasamori at [log in to unmask] or 847-615-7100 ext.2815 -----------------------------------------------------