You're correct, Standards development has absolutely nothing to do with the Designer's Council or local chapters.
.
Who is working on keeping them alive and insuring that they are correct?
Hundreds of people like me.
a lowly volunteer who makes an effort to show up at the meetings and call into the conference calls.
.
Have there been any active groups making or suggesting changes or amendments?
Yes. you can find a list of the groups here, but not how many people are participating in each group.
http://www.ipc.org/Status.aspx
.
Just for the record, I remember Mike Jouppi asking this list for help for a new document titled
"Current Carrying Capacity of Printed Boards"
Did any of you volunteer?
nope.
How do I know?
because I'm the only only one that DID volunteer.
.
I'm not typing this out to blow my own horn,
because I'm truly "the new guy" in these development meetings.
I'm saying it on behalf of SO MANY people who have been devoting time to this for YEARS
.
I realize its hard to imagine everything going on behind the scenes,
but you would be surprised how many people are involved,
sometimes over a hundred people all discussing one simple paragraph of an acceptance document.
and you know what? Hardly ANY of them are designers.
(I think I was the only designer at the last meeting of the IPC-222x DESIGN document)
You know who IS at the DESIGN document meeting?
Mostly Fabricators and Assemblers who are hoping you can learn how to design better!
.
So, next time you're at APEX or IPC MidWest, take a break from collecting trinkets
on the show floor, and walk into one of the meetings where the work is getting done.
They are open to ANYONE
.
As for the question about CID modules, Here is an invitation
(If you didn't get one, it may be that you've never expressed an interest in helping)
.
So, here's your invitation:
===============================
To: All members of the Design community
Subject: Call for Participation - Focus Module Development
Dear Colleagues,
As many of you know, we have updated the Basic and Advanced Designer Certification training materials, and it is now time to move to the next phase of professional development. Your Education Committee has authorized development of the High Speed – High Frequency Focus Module for Certification.
Professor Rainer Thueringer, University of Giessen, Germany has already prepared several chapters of the information to be studied. He also helped to define the 32 topics to be covered in the two days of training review that make up a Certification Workshop. Now we need your input in order to move forward, so that the whole training module has a cohesive structure.
Here is your chance to participate. We are planning nine working weekends in order to prepare the syllabus, followed by five weekends to develop the questions and answers to be used in the exam. Each meeting will build on the previous effort. We will then schedule beta test sessions to fine-tune the relationship between study material and exam.
This is a great opportunity for professional development: build your credentials, collaborate with other industry experts, and make a real contribution to the Design community. Volunteers will receive credit in the published materials, as co-authors of a particular section and/or as general contributors.
Designers who volunteer should have ideas about content for at least one of the 32 areas covered in the following Course Outline. Background in signal integrity and high speed issues is most helpful. Volunteers may attend the working sessions in person or via teleconference. You may also send in your existing articles and/or presentations, with authorization for use in the Focus Module. Feel free to bring in colleagues with expertise in any of the areas covered by the Course Outline.
The following dates and locations have been suggested. They are coupled to scheduled IPC events in each area, but we are open to suggestions for alternate sites. Please review the list below, and let us know how you can participate by November 15, 2008.
Study Guide Preparation: 2009 Working Sessions
January 17-18 |
Orlando, FL |
January 31-Feb 1 |
Austin, TX |
February 14-15 |
Phoenix, AZ |
February 21-22 |
Irvine, CA |
March 14-15 |
Bannockburn, IL |
April 18-19 |
Boston, MA |
May 16-17 |
San Jose, CA |
June 6-7 |
Toronto, Canada |
June 20-21 |
San Diego, CA |
2009 Test Question Preparation: Study Guide Review and Modification
July 25-26 |
Raleigh , NC |
August 7-9 |
Seattle, WA |
August 22-23 |
Bannockburn, IL |
September 12-13 |
Philadelphia, PA |
October 10-11 |
San Francisco, CA |
October 24-25 |
Irvine, CA |
2009 Beta Testing
November 9-11 [Beta #1] Seattle, WA
November 12-14 [Beta #2] Phoenix, AZ
November 19-21 [Beta #3] Fredericksburg, VA
December 3-5 [Beta #4] San Diego, CA
2009 Beta Test Results analysis and modifications
December 7-9 Beta Analysis in Bannockburn, IL
To volunteer, contact IPC Professional Development:
[log in to unmask] or +1 847 597 2827.
We look forward to hearing from you, and will keep you informed about progress in the development of this new Designer Council Certification activity.
Best regards,
Dieter Bergman
IPC Director of Technology Transfer
Course Outline: Certification Focus Module for High Speed - High Frequency
DAY 1
BASICS OF HIGH SPEED
- 1.1 High Speed Defined
- Low and High Frequency Signals
- Signal Rise Distance; Edge Rate
- Critical Line Length - Risetime Relationship
- Skin Effect; Signal Attenuation
- 1.2 Wave shape and Frequency
- Sine Wave Description
- Digital Pulses and Harmonics
- Time Domain and Fourier Spectrum; Bandwidth
- Clock Frequency vs. Switching Frequencies
- 1.3 Impedance Definition
- Line Impedance –Water model
- DC- versus Impulse Current
- Electrical Line Impedance; Lumped C,L
- Power Supply Impedance; Requirements
- 1.4 Transmission Line Definition
- Signals on TEM-Lines; Differential Signals
- Propagation Delay, Attenuation, Slewrate and Skew
- Reflections and Oscillations; Termination topic
- Coupled Lines; Crosstalk
ELECTRICAL REQUIREMENTS
- 2.1 Power System Implementation
- Distribution Path; Ground Bounce
- Bypassing/Decoupling
- 2-sided Boards
- Multilayer; Embedded Capacitor
- 2.2 Signal Transmission
- RF Signal Return Current
- Reflections and Oscillation
- Topologies and Terminations
- Crosstalk (Forward & Backward) & Control
- 2.3 Circuit Analysis
- Timing Margin; Clock Skew
- Loaded Line Characteristics & Timing
- Branching Issues; Stubs
- Layer Skipping
- 2.4 Differential Signaling
- Routing Techniques
- Terminations
- Influence of Planes
- Conductor Width & Spacing
BOARD CHARACTERISTICS
- 3.1 General PC Board Fabrication
- Standard Materials (Laminates & Prepregs)
- Material Properties (DK, CTE, ...)
- Copper Requirements; VLP Foils
- Process Tolerances & Influence Analysis
- 3.2 Board Impedance
- Impedance Classes
- Single Ended Layering (Microstrip and Stripline)
- Differential Pairs
- Power planes
- 3.3 Multilayer Constructions
- 4 Layer Structures
- 6 Layer Construction
- 8+ Layer Constructions
- Layering Approaches
- 3.4 HDI-Microvia Constructions
- Microstrip Constructions
- Stripline Constructions
- Dual-Stripline Constructions
- Impedance Variations & Tolerances
LAYOUT PRINCIPLES
- 4.1 PC Board Design Elements
- Optimum Impedance Value
- Proper Trace Width & Spaces
- Maximum Stub Lengths
- Test Structures needed
- 4.2 Component Placement & Splitting Planes
- Circuitry Analysis; Busstructures
- Split GND/VCC PLanes (® Martin O'Hara et.al.)
- Component Side Distribution
- Peripherie & Connectors
- 4.3 Vias & Via Chains
- Mechanical Properties
- Capacitance & Inductance of Vias
- Influence on the Line Impedance
- Return-Current Flow
- 4.4 Prelayout Analysis (Line Simulation) (® Freddie)
- Layer Stacking Strategy
- Timing, Clock Distribution
- Termination Strategies; Noise Budgets
- Preventive Crosstalk Analysis
DAY 2
COMPONENTS AND ASSEMBLY
- 5.1 Bypassing/Decoupling Capacitors (® Rainer + O'Hara)
- Real Capacitors; Impedance vs. Frequency
- Dielectric, ESR & Loss Tangent
- Parallel Connection of Capacitors
- Optimal on Board Contacting
- 5.2 Component/Package Selection
- Parasitic Package Inductance & Capacitance
- Electrical Values: Rise time, Slew rate, Noise Margin, Driving Force
- Fanout Wiring Requirements & Stub Length
- Embedded Passives, COB
- 5.3 Connector Systems (® Howard Johnson)
- Mutual Inductive Coupling & Parasitic Capacitance
- High Speed Connectors
- Estimating Crosstalk
- Return-Current Path
- 5.4 Ribbon Cables (® Howard Johnson)
- Signal Propagation
- Frequency Response
- Cable Rise time
- Cable Crosstalk
PERFORMANCE PARAMETERS
- 6.1 Concurrent Layout Analysis (Line & Board Simulation) (® Freddie)
- Component IBIS Models; Loads, Terminations
- Timing/Delay/Skew Optimization
- Crosstalk & Reflections Analysis
- Power Distribution System: Integrity Analysis; Decaps
- 6.2 Optimum Layer Relationship
- Signal Layer Distribution; Shielding Planes
- Spliting Planes; Cutouts, Field Fringing (® Martin O'Hara et.al.)
- Crosstalk in GND Planes (® Howard Johnson)
- Stack-up Balance, Producability
- 6.3 Material Properties & Selection
- High Speed Dielectric Material
- RC-Foil vs. Reinforced Material
- Copper Thickness vs. Line-width
- Thermal Management; Heatsinks
- 6.4 Costs, Availability, Lead-time
- Influence Layer Count & Line-width
- HDI/µVia vs. Conventional Boards
- Intermixing High Frequency Materials
- Back Drilling for Stub Removal
ANALYSIS AND VERIFICATION
- 7.1 Post Layout Analysis (Board Simulation)(® Freddie)
- Power Integrity: Decoupling & Noise Margin
- Signal Integrity: Crosstalk & Reflections
- Constraint Driven Routing Analysis
- Delay/Skew Situation
- 7.2 Signal Integrity Measurements
- Defining Test Equipment
- Performance Parameters
- On-Board Measurements
- Interpretation & Consequences
- 7.3 Impedance Control Testing
- Test Setup Methods
- Coupon Design and Placement
- Testing Differential Pairs
- On-Board Measurements
- 7.4 Assembly Analysis Verification
- Registration Capability
- Testpoints and Test Nets
- Embedded Passives
- External Shields & Coating
DOCUMENTATION
- 8.1 General Documentation Practices
- Mixture of Electronic and Hard Copy Data
- Re-procurement of "as- built" requirements
- Configuration Management Strategy
- Field Reports and Maintenance
- 8.2 Materials/Impedance Tolerance
- Dielectric Parameter Descriptions
- Maximum Allowance for Performance Variation
- Coupon Verification Strategy
- Prototype and High Volume Description Controls
- 8.3 Multilayer Construction
- Single Lamination Criteria
- Sequential, build-up Multilayer
- Embedded Passive Description and Control
- Exotic Material Influence/Definition
- 8.4 Board & Assembly Thickness Issues
- Limitation for Card Edge Conditions
- Assembly Support and Housing Influence
- Moisture Influence & Conformal Coating Descriptions
- Sequencing of Material, Fabrication, Assembly and Test
DAY 3
CERTIFICATION TESTING
To volunteer, contact IPC Professional Development:
[log in to unmask] or +1 847 597 2827.
On Wed, Dec 3, 2008 at 5:02 PM, Ted Tontis
<[log in to unmask]> wrote:
If the local chapters are not active and the designer council is not actively working on keeping them alive, who is insuring that the standards are current? Have there been any active groups making or suggesting changes or amendments to the current standards? What ever happened to the advanced CID modules you would be able to take after the advanced certification course?
Interestingly enough there are just as many designer questions on TN then there are manufacturing questions and this forum has been quite for sometime. I lost my full time design job four years ago and started work with EMS providers in a manufacturing environment. I am now an electronics automotive quality engineer and have been doing board layout on the side for the last three years. I have lost all contact with IPC DC, but still sign up to the DC forum looking for new ideas and classes to keep my design knowledge current. I am sure there are other designers out there that have done the same. Could it be that we as designers have dropped in numbers so much that we no longer have a voice or that due to down sizing our workloads have tripled giving us less time to participate in the DC or area chapters?
Ted T
-------------------------------------------------------------------------------
DesignerCouncil Mail List provided as a service by IPC using LISTSERV 1.8e
To unsubscribe, send a message to [log in to unmask] with following text in
the BODY (NOT the subject field):
SIGNOFF DesignerCouncil
To temporarily stop/(start) delivery of DesignerCouncil for vacation breaks send: SET DesignerCouncil NOMAIL/(MAIL)
Search previous postings at: http://listserv.ipc.org/archives
Please visit IPC web site http://www.ipc.org/contentpage.asp?Pageid=4.3.16 for additional information, or contact Keach Sasamori at [log in to unmask] or 847-615-7100 ext. 2815
-------------------------------------------------------------------------------