It is called extraneous plating or background plating.
a) What could be the cause of this?
Uaually caused by over-catalyst during ENIG process.
b) Any detrimental effect in reliability?
Sure, it violates the minimum spacing (if luckily without creating hard shorts)
c) Any IPC spec govern this issue?
You can find it in IPC-4552 section 3.
Best Regards, Jason Zhao Zhao PCB International US 510-468-4412 China 137-74692180 --- On Wed, 9/17/08, Yap, Stella (SMI) <[log in to unmask]> wrote: From: Yap, Stella (SMI) <[log in to unmask]> |