Good morning Techs. We are redoing our conformal coating and masking process instructions for double sided boards and was asked to revisit the tolerance for masking up to keepout surfaces/edges. For example, many of our boards have a ~ ¼" wide keepout zone around the perimeter that is defined by a gold edge. Typically, the operator will mask up to the edge with an ESD tape and than spend non-value added time touching up after de-masking if the c/c does not come right up to the edge. As far as I know, IPC is silent on this type of masking question so I was wondering what the industry consensus on a realistic masking tolerance is. A few CMs have told me that they typically hold from 0 to .060" up to 1/8" provided ALL components and SJs are coated and that there is solder resist up to the edge of the keepout surface. I would think that something less than 1/8" like .060" is achievable and cost effective without compromising the reliability of the board as long as ALL components and SJs are coated and there is solder resist up to the edge of the keep out surface. Please let me know what other users use as realistic masking tolerance without compromising the reliability of the board/coating. Thanks Best Regards, - Joe --------------------------------------------------- Technet Mail List provided as a service by IPC using LISTSERV 15.0 To unsubscribe, send a message to [log in to unmask] with following text in the BODY (NOT the subject field): SIGNOFF Technet To temporarily halt or (re-start) delivery of Technet send e-mail to [log in to unmask]: SET Technet NOMAIL or (MAIL) To receive ONE mailing per day of all the posts: send e-mail to [log in to unmask]: SET Technet Digest Search the archives of previous posts at: http://listserv.ipc.org/archives Please visit IPC web site http://www.ipc.org/contentpage.asp?Pageid=4.3.16 for additional information, or contact Keach Sasamori at [log in to unmask] or 847-615-7100 ext.2815 -----------------------------------------------------