Tech Net & Designer Net Greetings. We are running into a situation on Lead Free processed PCBs. Failure mode is finding open vias during unit testing (fully populated). Boards are Tg170, Material type EM320, 0.063" thick boards. 6 layers of 1 oz copper. ENIG 3~5u" Suspect vias go from top layer to bottom layer only. After running through reflow, we have found vias open. No visual signs of delamination, however when ohming out the via, if we press on the via we get continuity - thus we suspect the vias are opening during the process. Anyone out there having these problems, or information concerning this failure mode? Z-expansion failure? Tom Parkinson Quality System Manager - CIT WinTronics, Inc. Phone: 724-981-5770 - extension 235 --------------------------------------------------------------------------------- DesignerCouncil Mail List provided as a free service by IPC using LISTSERV 1.8d To unsubscribe, send a message to [log in to unmask] with following text in the BODY (NOT the subject field): SIGNOFF DesignerCouncil. To temporarily stop/(restart) delivery of DesignerCouncil send: SET DesignerCouncil NOMAIL/(MAIL) Search previous postings at: www.ipc.org > On-Line Resources & Databases > E-mail Archives Please visit IPC web site http://www.ipc.org/contentpage.asp?Pageid=4.3.16 for additional information, or contact Keach Sasamori at [log in to unmask] or 847-615-7100 ext.2815 ---------------------------------------------------------------------------------