TechNet Friends, I was wondering if anyone could supply me with a comment regarding board warpage and reliability... Our old test and acceptance standard was developed around a maximum of 1000 microstrains. Readings above this supposedly would result in sporadic cracking of the larger sized ceramic chip capacitors or resistors. Since part dimensions have become smaller, might I assume the 1000 microstrain limit could be safely extended (with testing for confirmation, of course)? The bow and twist specs set forth in IPC-A-610D state that after solder conditions should not exceed 0.75% for surface mount applications. Was this spec set by the committee after some sort of reliability testing? If so, does anyone know if the study has been made available for reference? Many thanks in advance, Leland Woodall Quality Coordinator Keihin Carolina System Technology, Inc. --------------------------------------------------- Technet Mail List provided as a service by IPC using LISTSERV 1.8e To unsubscribe, send a message to [log in to unmask] with following text in the BODY (NOT the subject field): SIGNOFF Technet To temporarily halt or (re-start) delivery of Technet send e-mail to [log in to unmask]: SET Technet NOMAIL or (MAIL) To receive ONE mailing per day of all the posts: send e-mail to [log in to unmask]: SET Technet Digest Search the archives of previous posts at: http://listserv.ipc.org/archives Please visit IPC web site http://www.ipc.org/contentpage.asp?Pageid=4.3.16 for additional information, or contact Keach Sasamori at [log in to unmask] or 847-615-7100 ext.2815 -----------------------------------------------------