Hi Bill- I saw that in some of the earlier replies, you had been referred to the footprint available in IPC-7351. Is there a problem with using that config that we should know about? I'd like to hear about how you decide to handle the vias in the thermal pad. Having issues with another pak type at present. In our case, the parts solder just fine but the wicking through the holes causes a flatness problem when mounting to a heatsink on the opposite side. Potential for poking through the sealpad and we need to be electrically isolated. Tenting the bottom side (LPI) was not the answer.... All the Best, -Chris "Brooks,Bill" <[log in to unmask]> To: [log in to unmask] Sent by: TechNet cc: <[log in to unmask]> Subject: Re: [TN] 56 pin LFCSP footprint 12/02/2005 11:58 AM Please respond to TechNet E-Mail Forum; Please respond to "Brooks,Bill" Thanks... I contacted AD and talked with a technical support representative... He's looking into a footprint recommendation from their development team... He also sent me an application note on the part. It seems it has a large thermal 'belly pad', for lack of a better name, that gets soldered to the board in the center of the part. They recommend .3 mm vias on 1mm centers as thermal vias under the part, but as to any hard data on choice of solder, heat profiles, or the like, I did not see any reliable data. They mentioned the idea of plugging the vias or tenting them, and the use of no-clean flux containing solders because there is no way you would be able to clean under the part... That has me a little concerned too. I have heard of troubles with plugging vias on this forum before... but if I leave them open won't they will most likely wick the solder away from the pad to the far side of the board starving the thermal pad. I have used a chip with a 'belly thermal pad' before but in small quantities... this is a medium volume product and troubles with assembly could be costly so I value the comments put forth greatly. Thanks again for your experienced insight. Best regards, Bill Brooks - KG6VVP PCB Design Engineer, C.I.D.+, C.I.I. Tel: (760)597-1500 Ext 3772 Fax: (760)597-1510 Datron World Communications, Inc. _______________________________________ San Diego Chapter of the IPC Designers Council Communications Officer, Web Manager http://dcchapters.ipc.org/SanDiego/ http://pcbwizards.com --------------------------------------------------- Technet Mail List provided as a service by IPC using LISTSERV 1.8e To unsubscribe, send a message to [log in to unmask] with following text in the BODY (NOT the subject field): SIGNOFF Technet To temporarily halt or (re-start) delivery of Technet send e-mail to [log in to unmask]: SET Technet NOMAIL or (MAIL) To receive ONE mailing per day of all the posts: send e-mail to [log in to unmask]: SET Technet Digest Search the archives of previous posts at: http://listserv.ipc.org/archives Please visit IPC web site http://www.ipc.org/contentpage.asp?Pageid=4.3.16 for additional information, or contact Keach Sasamori at [log in to unmask] or 847-615-7100 ext.2815 ----------------------------------------------------- --------------------------------------------------- Technet Mail List provided as a service by IPC using LISTSERV 1.8e To unsubscribe, send a message to [log in to unmask] with following text in the BODY (NOT the subject field): SIGNOFF Technet To temporarily halt or (re-start) delivery of Technet send e-mail to [log in to unmask]: SET Technet NOMAIL or (MAIL) To receive ONE mailing per day of all the posts: send e-mail to [log in to unmask]: SET Technet Digest Search the archives of previous posts at: http://listserv.ipc.org/archives Please visit IPC web site http://www.ipc.org/contentpage.asp?Pageid=4.3.16 for additional information, or contact Keach Sasamori at [log in to unmask] or 847-615-7100 ext.2815 -----------------------------------------------------