Hi Fred, I would suggest posting this one on Technet and getting Steve to post your picture of the 'ant holes' on his web site... That way we can see what is happening... If you have not seen Steve Gregory's web site it's very useful for posting PCB issues to get some technical help... Take a look at it here http://www.stevezeva.homestead.com/ Just ask him to post it and send it attached to an e-mail directly to him. His e-mail is [log in to unmask] Bill Brooks - KG6VVP PCB Design Engineer, C.I.D.+, C.I.I. Tel: (760)597-1500 Ext 3772 Fax: (760)597-1510 Datron World Communications, Inc. _______________________________________ San Diego Chapter of the IPC Designers Council Communications Officer, Web Manager http://dcchapters.ipc.org/SanDiego/ http://pcbwizards.com -----Original Message----- From: Fred Dark [mailto:[log in to unmask]] Sent: Monday, September 12, 2005 9:50 AM To: (Designers Council Forum); Phillip Bavaro Cc: [log in to unmask] Subject: RE: [DC] Raised vias Hello Guy's, Basically, The note below is a older not but not much different from what we note know; 4. SOLDER MASK:USE SMOBC PROCESS (SOLDER MASK OVER BARE COPPER). SOLDER MASK TO BE LPI (LIQUID PHOTO IMAGEABLE), APPLIED TO BOTH SIDES PER THE APPROPRIATE ARTWORK LAYER. PLUG VIA HOLES FROM THE COMPONENT SIDE. SOLDER MASK REGISTRATION SHALL BE +/-.002. I'm just noting to "Plug" from component side... and then apply soldermask to both sides.. etc... From the IPC web site "TYPE III - Plugged" is what I was receiving... I do think that this is vendor related more than anything, after talking to our production manager in charge of incoming boards and assembly. What type of note is a standard...? We note on the drawing also to follow IPC-600,6011 and 6012 (the latest revision's)... I would think that this is enough... Regard's, Fred Dark Jr. -----Original Message----- From: Phillip Bavaro [mailto:[log in to unmask]] Sent: Sunday, September 11, 2005 3:08 PM To: [log in to unmask] Subject: Re: [DC] Raised vias Man, I hate ants ever since I got bit by a red ant who was pissed off at me so those pictures gave me the creeps.......thanks Bill....lol!!! Seriously tho, are the "ant hills" more than just double the soldermask thickness (applied with a dot pattern first and then applied without an aperture to cover over the via) or are they actually a mound that is thicker and will interfere with the stencil from coming in contact with the metal lands? Was is a new supplier? If not, did they perhaps use a new process to apply the "plugs"? Plugs can be applied to either side and should not be the cause of the problem. I am assuming these are bare boards which have not been wavesoldered yet. I have seen soldermask "trees" rise out of wavesoldered boards which had soldermask lightly coating the inside the solder coated barrels, and I have seen solder "termite hills" after soldering extremely thick boards with cracked barrels, but never seen an ant hill made out of purely soldermask. A real picture would help quite a bit. Hope this helps, Phil "Brooks,Bill" <[log in to unmask]> wrote: Hi Fred, I think if this is related to the soldermask note you posted awhile back that the use of the word 'plugged' may have been unfortunate... Correct me if I am wrong in my assumption that you wanted to put soldermask over the hole in a plated through via but not fill it? By 'plugged', did you expect them to stuff soldermask into the holes? I suppose that is a possible interpretation of the note you posted... I have not seen any pictures of the issue but what you describe as an ant hole seems someone non-standard. Here is what you posted.. 4. SOLDER MASK: USE SMOBC PROCESS (SOLDER MASK OVER BARE COPPER). SOLDER MASK TO BE LPI (LIQUID PHOTO IMAGEABLE), WITH VIA HOLES PLUGGED, APPLIED TO BOTH SIDES PER THE APPROPRIATE ARTWORK LAYER. SOLDER MASK REGISTRATION SHALL BE +/- .005 I found some images of ant holes for you to sort of give me an idea of what you mean... (I have to admit, the thought did bring some strange mental images to mind... :) ) Now don't take my kidding around seriously, after all it's Friday, and you have to cut me a little slack at this point... ok? Let's see, Is it like this? http://www.northern.wvnet.edu/~tdanford/west04/w410c.jpg or like this? http://www.nyanjasafaris.co.uk/images/ant_hill.jpg or maybe like this? http://gimli.physics.utoronto.ca/Sumner_2003/img/img_0576.jpg or even like this? http://www.ees.nmt.edu/~ljwilcox/travel/australia/images/aust_ant.jpg Hmmm... its hard to imagine, but seriously, if you send me a picture maybe I'll have a better idea of the problem is and can guess what happened... Of course contacting your vendor would be the most prudent thing on the list of problem solvers that I would use... they probably can get right to the heart of the matter... ;) Best regards, Bill Brooks - KG6VVP PCB Design Engineer, C.I.D.+, C.I.I. Tel: (760)597-1500 Ext 3772 Fax: (760)597-1510 Datron World Communications, Inc. _______________________________________ San Diego Chapter of the IPC Designers Council Communications Officer, Web Manager http://dcchapters.ipc.org/SanDiego/ http://pcbwizards.com -----Original Message----- From: Fred Dark [mailto:[log in to unmask]] Sent: Friday, September 09, 2005 2:36 PM To: [log in to unmask] Subject: [DC] Raised vias Hello All, I received some board's in from a vendor and on the component side the vias are raised... I rejected the board's, but what causes this... We note on our drawing to plugged vias from component side and we always have... This is the first time it's a problem... Is it wrong to plug via's from the component side... It look's like a ant hole, if you know what I mean... looks like added solder mask... Regard's, Fred Dark Jr. ---------------------------------------------------------------------------- ----- DesignerCouncil Mail List provided as a free service by IPC using LISTSERV 1.8d To unsubscribe, send a message to [log in to unmask] with following text in the BODY (NOT the subject field): SIGNOFF DesignerCouncil. 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