Hello folks, The key SMT assembly issue is often the higher molten solder meniscus on the thermal pad on the PCB. This can cause package tilt and lead to opens on the peripheral leads. With the very small, low mass packages, like QFNs, this can be significant. Most companies handle this by printing solder paste in a grid pattern on the PCB thermal pad, this print may cover approximately 50% of the thermal pad. Melting of this paste grid and lateral spreading on the PCB thermal pad and the package's exposed die attach pad (DAP) helps to lower the meniscus and pull the QFN down to the PCB and allow good bonding of the peripheral pads. Since the QFN pads are typically much closer to the package's exposed DAP than with exposed pad QFPs, etc., care must be taken to prevent solder bridging between the exposed DAP and the contact pads. Since the thermal pad on the PCB, which is directly opposed to the DAP, often is connected to internal PCB planes with vias to allow a stiff voltage connection and/or good thermal spreading in the internal plane, the issue of how to prevent solder thieving into the vias must be handled. This is often done with solder mask tenting or filling/partial filling. The SM rings around these vias reduces the wetted surface area of the thermal pad, so this needs to be comprehended in the design of the solder paste stencil apertures for the thermal pad to prevent excessive meniscus height and to allow adequate area of solder bonding between the package DAP and the thermal pad. It is generally recognized, and represented in some published documents and application notes that the solder bond area between the DAP and the thermal pad can tolerate voids across up to approximately 50% of the interfacial area without any significant degradation in either thermal or electrical resistance across the solder joint. Some other thermal pad issues are related to the common desire to rout signals across the PCB thermal pad area. To address this issue, ASAT, Inc. has developed a gridded DAP in the QFN package, formed by half-etching of the DAP thickness so as to produce a checkered pattern of exposed DAP elements on the exterior of the package, while maintaining a solid leadframe DAP to which the die is bonded inside the package. This allows the design of a gridded thermal pad on the PCB to permit routing of signals across the thermal pad area. This gridded DAP pattern also promises to ease some of the difficulty in reworking QFN assemblies on PCBs. Best regards, Leo Leo M. Higgins III, Ph.D. Director of Applications Engineering ASAT, Inc. 3755 Capital of Texas Hwy, Suite 100 Austin, Texas 78704 ph 512-383-4593 fx 512-383-1590 -----Original Message----- From: Daan Terstegge [mailto:[log in to unmask]] Sent: Thursday, October 28, 2004 6:53 AM To: [log in to unmask] Subject: [TN] IC's with solderable area underneath Hi Technet, I'm seeing more and more QFP's and other IC's with a solderable area underneath the package body (heatsink function). Strangely enough not much thought is being given to expectations of designers or to the problems that these components may give in assembly. Does anyone know of standard requirements (i.e. IPC) for the soldered area? When a designer doesn't mention it on the assembly drawing, would you assume that is still mandatory to have solder in that area? If so, how can this requirement be met when using a soldering iron (i.e. Metcal's minihoof tip) to install a QFP for rework or repair? Any other comments with regards to such components? Best regards, Daan Terstegge PCB Assembly Department Thales Land & Joint Systems Tel +31(0)35 524 8297 Fax +31(0)35 524 8181 [log in to unmask] Unclassified Email --------------------------------------------------- Technet Mail List provided as a service by IPC using LISTSERV 1.8e To unsubscribe, send a message to [log in to unmask] with following text in the BODY (NOT the subject field): SIGNOFF Technet To temporarily halt or (re-start) delivery of Technet send e-mail to [log in to unmask]: SET Technet NOMAIL or (MAIL) To receive ONE mailing per day of all the posts: send e-mail to [log in to unmask]: SET Technet Digest Search the archives of previous posts at: http://listserv.ipc.org/archives Please visit IPC web site http://www.ipc.org/contentpage.asp?Pageid=4.3.16 for additional information, or contact Keach Sasamori at [log in to unmask] or 847-615-7100 ext.2815 ----------------------------------------------------- --------------------------------------------------- Technet Mail List provided as a service by IPC using LISTSERV 1.8e To unsubscribe, send a message to [log in to unmask] with following text in the BODY (NOT the subject field): SIGNOFF Technet To temporarily halt or (re-start) delivery of Technet send e-mail to [log in to unmask]: SET Technet NOMAIL or (MAIL) To receive ONE mailing per day of all the posts: send e-mail to [log in to unmask]: SET Technet Digest Search the archives of previous posts at: http://listserv.ipc.org/archives Please visit IPC web site http://www.ipc.org/contentpage.asp?Pageid=4.3.16 for additional information, or contact Keach Sasamori at [log in to unmask] or 847-615-7100 ext.2815 -----------------------------------------------------