Technetters, At this point I want to present my position, because I have one. But first - the trigger to my question came from a failure analysis I made to a batch of 12 boards. We manufactured nearly 200 units of this relatively new product without significant problems. Yes, we have had some, but we assumed they were related to the complexity of the board (18 layers, 15 BGAs, 5000 components total, 4 mils traces and spaces, 2.7 mm thick, controlled impedances on all the layers, and a bunch of other goodies). But this specific batch failed completely. Since the assembly was done in two runs, while the PCB batches in each assembly run were mixed (2 to 3 PCB batches per assembly run) and the problem was only on the bare boards from the specific batch we concluded that the problem is in this batch. The problem in the assemblies was that on every board there were few (1 to 5) disconnected traces. In one of the cases we drilled down to the identification of the via that while pressing on the failure disappeared. We made a cross section through this via and found a very nice plating, with uniform coating (nice task, considering the 1:9 aspect ratio of this thick board) - and a clear horizontal crack right in the middle of the Z-axis. Also, it was clear from the analysis that all the non-functional pads were removed. The Gerber data contains the pads in all the layers. We allow removal of non-functional only with our consent because of two reasons: 1. Via strength and withstanding of thermal cycles. 2. Sometimes the pad is being used as a trib for signal integrity, if so needed by the high speed signal analysis simulations (3.125 GHz, after all). I think that in this case the first reason proved itself to be valid. Since the PCB manufacturer disagreed with me (hello there, I know you read it!) I decided to ask for the honored forum opinion. Regards Ofer Cohen Manager Quality Assurance, Reliability and Production Technologies Seabridge Ltd. - A Siemens Company -----Original Message----- From: TechNet [mailto:[log in to unmask]]On Behalf Of Mcmaster, Michael Sent: Tuesday, July 27, 2004 19:26 To: [log in to unmask] Subject: Re: [TN] Removal of non functional pads I went back and checked my personal Technet archive. We last discussed this issue in March 2003. This is my posting from then. (Feel free to check the on-line archives to see the other posting on this issue - the old subject was "non functional pad removal") Begin 2003 post: So far this argument has been pretty one-sided for leaving non-functional pads in the design. And I agree with all the arguments presented in favor of doing so. But there are potential negative impacts to leaving non-functional pads. Leaving the pads in increases drill wear and heat generation. As a result drilled hole quality degrades much more rapidly and defects like pad tearout, hole wall notching, drill bit plugging, etc. occur much faster. If these aren't being caught, they can be more of a problem than the reliability gains achieved by leaving pads in. To address this you need to reduce maximum drill hit counts which ends up increasing the cost of building the board. It's important to remember that drilling a circuit board is a very difficult operation. You are trying to make a very small hole in a (relatively) thick composite made of dissimilar materials: copper and a glass-reinforced polymer. And you can't leave any of the latter over the former. The resulting drill process is a compromise. A good board fabricator will have done their homework and understand the interactions involved here. The optimum configuration for NFPs may be a compromise somewhere between "all" and "none" depending on board thickness, hole size, material, copper weight, etc. :End 2003 post The only thing I'd like to add is my recommendation that you leave the pads in your design and allow it up to your fabricator whether to leave them in or remove them. But you do this ONLY AFTER you grill them about their rules and why they do what they do. The fabricator should be able to support their position with reliability data. -----Original Message----- From: TechNet [mailto:[log in to unmask]] On Behalf Of Frank Kimmey Sent: Tuesday, July 27, 2004 6:35 AM To: [log in to unmask] Subject: Re: [TN] Removal of non functional pads Ofer, As you have already seen from Brain, Jeff and others, there are varying thoughts on this subject. That said, here are mine. Unused pads on inner layer can play an important part in the construction and reliability of your PCBs. I recommend removal of unused pads on low layer count, low Z axis CTE materials to improve manufacturability at fab. There will be longer drill life, less inner layer misregistration possibilities, etc. I adamantly refuse to allow removal of unused pads on high layer counts and/or high Z axis CTE or mismatched CTE materials. The reasons for this is pretty simple, first if the laminate material stretches the copper barrel enough then the PTH barrel can actually end up longer than the PCB is thick (very strange looking phenomena), also stretching of the plated barrel can cause reliability issues due to cracking and subsequent opens (read this as field failures). Leaving at least a minimal annular ring on inner layer pads will aid in supporting the PTH and reduce the likelihood of damage cause by PCB Z axis expansion. I think you will find most fabricators would prefer to see unused pads removed as that will commonly improve manufacturability, where most reliability types would prefer to see all pads remaining to improve barrel anchoring/strength and integrity. Talk to your fabricator and your quality guys to help reach the best decision for your specific construction. Remember communicate your issues and most of them will have an acceptable solution. Hope it helps, FNK Frank N Kimmey CID+ Principle PCB Designer Powerwave Technologies EDH 916-941-3159 FAX 916-941-3195 CEL 916-804-2491 -----Original Message----- From: Ofer Cohen [mailto:[log in to unmask]] Sent: Tuesday, July 27, 2004 3:48 AM To: [log in to unmask] Subject: [TN] Removal of non functional pads Technetters, Are there any guidelines regarding removal of non functional pads in thick (>2.5 mm) PCBs? Are the guidelines documented somewhere? Regards Ofer Cohen Manager Quality Assurance, Reliability and Production Technologies --------------------------------------------------- Technet Mail List provided as a service by IPC using LISTSERV 1.8e To unsubscribe, send a message to [log in to unmask] with following text in the BODY (NOT the subject field): SIGNOFF Technet To temporarily halt or (re-start) delivery of Technet send e-mail to [log in to unmask]: SET Technet NOMAIL or (MAIL) To receive ONE mailing per day of all the posts: send e-mail to [log in to unmask]: SET Technet Digest Search the archives of previous posts at: http://listserv.ipc.org/archives Please visit IPC web site http://www.ipc.org/contentpage.asp?Pageid=4.3.16 for additional information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700 ext.5315 ----------------------------------------------------- --------------------------------------------------- Technet Mail List provided as a service by IPC using LISTSERV 1.8e To unsubscribe, send a message to [log in to unmask] with following text in the BODY (NOT the subject field): SIGNOFF Technet To temporarily halt or (re-start) delivery of Technet send e-mail to [log in to unmask]: SET Technet NOMAIL or (MAIL) To receive ONE mailing per day of all the posts: send e-mail to [log in to unmask]: SET Technet Digest Search the archives of previous posts at: http://listserv.ipc.org/archives Please visit IPC web site http://www.ipc.org/contentpage.asp?Pageid=4.3.16 for additional information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700 ext.5315 ----------------------------------------------------- --------------------------------------------------- Technet Mail List provided as a service by IPC using LISTSERV 1.8e To unsubscribe, send a message to [log in to unmask] with following text in the BODY (NOT the subject field): SIGNOFF Technet To temporarily halt or (re-start) delivery of Technet send e-mail to [log in to unmask]: SET Technet NOMAIL or (MAIL) To receive ONE mailing per day of all the posts: send e-mail to [log in to unmask]: SET Technet Digest Search the archives of previous posts at: http://listserv.ipc.org/archives Please visit IPC web site http://www.ipc.org/contentpage.asp?Pageid=4.3.16 for additional information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700 ext.5315 ----------------------------------------------------- --------------------------------------------------- Technet Mail List provided as a service by IPC using LISTSERV 1.8e To unsubscribe, send a message to [log in to unmask] with following text in the BODY (NOT the subject field): SIGNOFF Technet To temporarily halt or (re-start) delivery of Technet send e-mail to [log in to unmask]: SET Technet NOMAIL or (MAIL) To receive ONE mailing per day of all the posts: send e-mail to [log in to unmask]: SET Technet Digest Search the archives of previous posts at: http://listserv.ipc.org/archives Please visit IPC web site http://www.ipc.org/contentpage.asp?Pageid=4.3.16 for additional information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700 ext.5315 -----------------------------------------------------