We are currently looking for a way to measure PCB / chip component stress during our assembly process, especially depanelization. We would like to get an idea of what amount of stress (flex) the boards are undergoing. We would also like to use this to compare a few different processes--for example router depaneling compared to cutter depaneling as well as manual depaneling. But we are now facing several problem: 1. How much "stress" (or flex) is too much, for both PCB and chip components near the PCB edge? 2. What equipment could be used to make an accurate measurement? 3. Any simular test is done before? Thanks, Ernie Fung --------------------------------------------------- Technet Mail List provided as a service by IPC using LISTSERV 1.8e To unsubscribe, send a message to [log in to unmask] with following text in the BODY (NOT the subject field): SIGNOFF Technet To temporarily halt or (re-start) delivery of Technet send e-mail to [log in to unmask]: SET Technet NOMAIL or (MAIL) To receive ONE mailing per day of all the posts: send e-mail to [log in to unmask]: SET Technet Digest Search the archives of previous posts at: http://listserv.ipc.org/archives Please visit IPC web site http://www.ipc.org/contentpage.asp?Pageid=4.3.16 for additional information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700 ext.5315 -----------------------------------------------------