Folks, Please help by letting me know what you are using for clearance of ceramic capacitors to a board edge. We currently use a .160" minimum clearance on the edges secured by pick and place conveyor tabs and .100 (sometimes slightly less) to other board edges. These numbers were established for mechanical interference issues driven by test fixtures and pick and place. Recently, we had a problem with a couple of ceramic cap's (with a X7R temperature rating) that cracked near the leads after depanelizing with a 'pizza cutter' along the score line. It's not entirely clear to me whether the depaneling operation and the caps proximity to the board edge of .085" were the sole contributors. It seems that X7R rated caps are more prone to cracking and at least one manufacturers data sheet calls for .200" clearance for depanelling. Modelling indicated significant stress on the component which decreased as the component was moved further away from the edge. Our solution was to route slots adjacent to the components instead of scoring the entire edge. As a result of this issue our Manufacturing Engineering group is asking for .200" board edge clearance in our design guidelines for ALL ceramic capacitors. To me this seems to be overkill but, before I tell them to kiss-off I thought it best to find out what the rest of my fellow designers are doing. Thanks Much! Rick Richard G. Smith CAD Services Manager C-COR "The Only Solution for Network Integrity" Broadband Communications Products 999 Research Parkway Meriden, Ct. 06450 PH: 203-639-7670 FX: 203-317-4421 [log in to unmask] www.c-cor.net --------------------------------------------------- Technet Mail List provided as a service by IPC using LISTSERV 1.8e To unsubscribe, send a message to [log in to unmask] with following text in the BODY (NOT the subject field): SIGNOFF Technet To temporarily halt or (re-start) delivery of Technet send e-mail to [log in to unmask]: SET Technet NOMAIL or (MAIL) To receive ONE mailing per day of all the posts: send e-mail to [log in to unmask]: SET Technet Digest Search the archives of previous posts at: http://listserv.ipc.org/archives Please visit IPC web site http://www.ipc.org/contentpage.asp?Pageid=4.3.16 for additional information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700 ext.5315 -----------------------------------------------------