Chris, I hear what you are saying, and yes, I used the word "ground" out of habit. My confusion though lies in the fact that there will be no reference plane below the signal trace (hence coplanar) and that the designer seems to think that they (end user) only want the reference line on one side of the signal line. When I try and use the Polar calculator with the parameters given below, and I deselect the "plane" radio buttons it tells me that I need a reference line width of at least 10x the dielectric thickness, which is 62mil) or 10x the coplanar separation. Again, to clarify, my confusion is in the fact that I do not have reference "plane" surrounding the signal trace. I need to understand how the proposed design will work, and how to reconcile the calculations before manufacturing. Thanks John -----Original Message----- From: Chris Robertson [mailto:[log in to unmask]] Sent: November 19, 2003 11:48 AM To: TechNet E-Mail Forum.; John Parsons Subject: Re: [TN] Co-planar Impedance Calculations It doesn't have to be ground. That is why they are always called reference planes. I personally use + and - voltages with no problems. I also have used split planes above and below, but I also recommend not to use split plane reference planes in the areas where controlled impedance traces are or on very high frequencies. This is just my personal findings. I like the polar calculator and actually compared my calculator on their findings. Go to www.pcbdr.com and get the spread sheet calculator. or directly to http://home.hiwaay.net/~robdne/files/Beta%20ResourceV4.xls to use the calculator online. (click on the "stack" tab at the bottom) The updated version is much better. These calculate the entire board and adds the thickness on the fly. Chris Robertson Author “PCB Designer’s Reference” [log in to unmask] ISBN: 0130674818 Search for it at www.Amazon.com ----- Original Message ----- From: John Parsons To: [log in to unmask] Sent: Wednesday, November 19, 2003 1:14 PM Subject: [TN] Co-planar Impedance Calculations Greetings all, I have a customer who is doing an impedance design for Intel and he has no previous impedance experience. This is the information I have. - double sided board - target impedance 50ohm - signal line 5mil wide, spaced 5mil from "ground" trace and this pair of traces should be spaced a minimum of 20mil from adjacent traces. This is what he was given from Intel. I am using an older Polar model (CITS25 calculator) which does have models for co-planar designs but from what I can tell they assume that the signal trace is sandwiched between ground (return lines) on both sides. Is this a correct interpretation? Is it possible to model the design as described above? While we have some experience with controlled impedance I have no experience with the aforementioned design and could use some assistance. Best Regards John Parsons --------------------------------------------------- Technet Mail List provided as a service by IPC using LISTSERV 1.8e To unsubscribe, send a message to [log in to unmask] with following text in the BODY (NOT the subject field): SIGNOFF Technet To temporarily halt or (re-start) delivery of Technet send e-mail to [log in to unmask]: SET Technet NOMAIL or (MAIL) To receive ONE mailing per day of all the posts: send e-mail to [log in to unmask]: SET Technet Digest Search the archives of previous posts at: http://listserv.ipc.org/archives Please visit IPC web site http://www.ipc.org/contentpage.asp?Pageid=4.3.16 for additional information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700 ext.5315 -----------------------------------------------------