We started building product using these parts- QFN 32 (8 mm sq) and QFN Motorola, National Semiconductor and Intersil all have useful information on QFN. At a previous life, we found that extended the toe to extend outside the periphery of the QFN package greatly assisted in verifying solder deposition and reflow and also assisted in reworking insufficient (we have vias in pad- another design flaw). We would run an mini-wave tip around the periphery of the component. The major problem we had was in printing thermal pads without overprinting into thermal vias and getting insufficient solder. According to National, you can have 80 % voiding in thermal pads without sacrificing thermal dissipation. would be interested in other's experiences Tom Gervascio Senior Process Engineer Sparton Electronics (352) 540-4040 [log in to unmask] --------------------------------------------------- Technet Mail List provided as a free service by IPC using LISTSERV 1.8e To unsubscribe, send a message to [log in to unmask] with following text in the BODY (NOT the subject field): SIGNOFF Technet To temporarily halt or (re-start) delivery of Technet send e-mail to [log in to unmask]: SET Technet NOMAIL or (MAIL) To receive ONE mailing per day of all the posts: send e-mail to [log in to unmask]: SET Technet Digest Search the archives of previous posts at: http://listserv.ipc.org/archives Please visit IPC web site http://www.ipc.org/contentpage.asp?Pageid=4.3.16 for additional information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700 ext.5315 -----------------------------------------------------