Here's my understanding of the problem for what it's worth.. If you think of the impedance matched signals as a differential pair, the signal trace and its return path in the plane need to stay together, equidistant, as much as possible much like common differential pairs are run horizontally matched, only these 'micro strip' traces are matched vertically through the dielectric instead of parallel in the same layer. Consistent impedance matching keeps the energy being sent down the line from reflecting or radiating into space and it all arrives at the destination load and is used and the returned currents follow along the return path directly under the signal trace, in the plane... Nothing should break that pair's equidistant relationship, otherwise you have a change in the relative impedance resulting in a release of RF energy and reflections and EMI that occur due to that change. An RF signal track that is run across a broken plane acts like a huge relative impedance change between the track and the return path, increasing the energy radiated from the trace that essentially gets radiated as EMI. The return currents must find a different path that is not directly under the signal trace and move around the obstruction or slot in the plane creating a mismatch.. In essence, you have created an antenna. Lee Hill explains all of this much better than I can, his website is http://www.silent-solutions.com/ Bill Brooks, CID -----Original Message----- From: Brooks,Bill [mailto:[log in to unmask]] Sent: Monday, July 14, 2003 1:48 PM To: [log in to unmask] Subject: Re: [DC] Reference Planes for Impedance Controlled Signals Can you say 'Slot Antenna'... <grin> I think Lee Hill's presentation at PCB West on EMI/EMC demonstrated so well the danger of split planes and crossing the split with high speed signals or RF and the resulting harmonic EMI levels that spilled out all over the radio frequency spectrum.. Seriously, placement is the key.... and never cross the split or better yet have no split at all. Bill Brooks -----Original Message----- From: Jack C. Olson [mailto:[log in to unmask]] Sent: Monday, July 14, 2003 1:26 PM To: [log in to unmask] Subject: Re: [DC] Reference Planes for Impedance Controlled Signals 8MHz Here's more info. We have a PowerPC processor BGA that has many +5V and +2.6V pins. Instead of trying to do a split plane, and having the impedance controlled stuff possibly traveling over a split, I thought it was better to have both a solid +5v plane and solid +2.6v planes on different layers. But as soon as you do that, you have some signals closer to one plane that the other, and the question is will there be signal integrity issues by using the +5v plane as a reference. On the other hand, how do you guys create complicated split planes and keep signals from crossing the split? (Veribest/Mentor Expedition/Mentor BoardStationRE router) thanks, Jack Karl Bates <[log in to unmask] > Sent by: DesignerCouncil To: [log in to unmask] <DesignerCouncil@listse cc: rv.ipc.org> 07/14/2003 02:10 PM Subject: Re: [DC] Reference Planes for Impedance Controlled Signals Please respond to "(Designers Council Forum)"; Please respond to Karl Bates Caterpillar: Confidential Green Retain Until: 08/13/2003 Retention Category: G90 - General Matters/Administration And...What frequency is the circuit operating at ? Khz or Mhz or Ghz ? ---------------------------------------------------------------------------- ----- DesignerCouncil Mail List provided as a free service by IPC using LISTSERV 1.8d To unsubscribe, send a message to [log in to unmask] with following text in the BODY (NOT the subject field): SIGNOFF DesignerCouncil. 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