I would like to attend. Peggy A. Meadows Intel Corporation APD 408 765 5303 Thank you. -----Original Message----- From: Bob McCreight [mailto:[log in to unmask]] Sent: Wednesday, April 23, 2003 10:03 AM To: [log in to unmask] Subject: [DC] Meeting Announcement: Silicon Valley Chapter (May 13) The Silicon Valley Chapter of the IPC Designers Council is excited to announce that their next meeting will be May 13 (Tuesday) at Cadence Design Systems in San Jose. 11:30AM to 1:30PM; $1 for members, $5 for visitors. Lunch is provided by our sponsor: Cadence Design Systems RSVP is required as space is limited ... REPLY NOW! The Topic: Calculating Impedance and designing cross sections Presenter: Lee Ritchey LEE RITCHEY, BSEE, is owner of Speeding Edge, a consulting firm specializing in high-speed design consulting and training. Lee Ritchey is currently working with major suppliers of gigabit and beyond internet products as well as a variety of wireless products. He has 30+ years experience in the packaging of high performance equipment from microwave satellites to supercomputers. Until recently, Lee was Director of Packaging Engineering at 3Com Corporation, a major network equipment supplier. Lee is currently working full time as a consultant to several major manufacturers of Gigabit and higher Ethernet products. [In December 1998, EE Times profiled Lee Ritchey in its People 98 section, characterizing him as "high-speed design's ratchet man," and stating that "anyone who wants to learn the ins and outs of high-speed board design can't do much better than to turn to Lee Ritchey..." Lee was one of 19 technical gurus recognized by EE Times as major drivers and innovators in their fields, specifically CAD/CAE tools for simulation and design of PCBs.]* He is on the editorial review board for Printed Circuit Design Magazine and is a regular contributor of design articles to a variety of publications. He has taught his High Speed Design course to more than 3000 engineers and designers in several countries. He is a regular lecturer at the Printed Circuit Design Conference, the IPC conferences and at UC Berkeley Engineering Extension. - - - - - - - - - - Location: Cadence Design Systems 2655 Seely Ave., Bldg 5 (Duluth Room) San Jose, CA May 13 Tuesday Time: 11:30AM to 1:30PM RSVP Required (space is limited to 40 people) Duluth room is in building 5 in the back of the cafeteria. __________________________________________________ Do you Yahoo!? The New Yahoo! Search - Faster. Easier. Bingo http://search.yahoo.com --------------------------------------------------------------------------------- DesignerCouncil Mail List provided as a free service by IPC using LISTSERV 1.8d To unsubscribe, send a message to [log in to unmask] with following text in the BODY (NOT the subject field): SIGNOFF DesignerCouncil. To set a vacation stop for delivery of DesignerCouncil send: SET DesignerCouncil NOMAIL Search previous postings at: www.ipc.org > On-Line Resources & Databases > E-mail Archives Please visit IPC web site http://www.ipc.org/html/forum.htm for additional information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700 ext.5315 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- DesignerCouncil Mail List provided as a free service by IPC using LISTSERV 1.8d To unsubscribe, send a message to [log in to unmask] with following text in the BODY (NOT the subject field): SIGNOFF DesignerCouncil. To set a vacation stop for delivery of DesignerCouncil send: SET DesignerCouncil NOMAIL Search previous postings at: www.ipc.org > On-Line Resources & Databases > E-mail Archives Please visit IPC web site http://www.ipc.org/html/forum.htm for additional information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700 ext.5315 ---------------------------------------------------------------------------------