Hello technet. This is our first design using silver filled via. We have used two different PCB fab. A total of 7 lots have been done and the yield seen at our pcb fab house has not improved (15%). The major problem we have is generalized delamination after reflow (not localized) that seems to happen around layers 4-5. Our pcb. Fab is currently investigating on the causes. Until now , no satisfactory explanations has been given to us. * Have some of you been faced against the same problem (delamination On silver filled via). * Any possible Causes/solutions * Any theories on the most probable cause (design/process/material compatibility ...) At this time, product release has been delayed. Your help in this matter would be appreciated. Board specification Dimension : 6.5X9 inch board. 0.070" thickness Sub sequential buildup Layer 5 to 12 with a total of 16 layers. Silver epoxy filled via using dupont CB100 . Qty of 7000 silver filled Via of 0.008" Qty of 1000 silver filled Via of 0.010" The populated boards has a very high thermal mass: 8 BGA . current of 96 Amps. Impedance controlled and Burried capacitance Line/Spacing : 0.003" / 0.005" Best regards Michel Arbour Kontron Tel. : 450-437-4661 ext. 2287 --------------------------------------------------- Technet Mail List provided as a free service by IPC using LISTSERV 1.8e To unsubscribe, send a message to [log in to unmask] with following text in the BODY (NOT the subject field): SIGNOFF Technet To temporarily halt or (re-start) delivery of Technet send e-mail to [log in to unmask]: SET Technet NOMAIL or (MAIL) To receive ONE mailing per day of all the posts: send e-mail to [log in to unmask]: SET Technet Digest Search the archives of previous posts at: http://listserv.ipc.org/archives Please visit IPC web site http://www.ipc.org/html/forum.htm for additional information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700 ext.5315 -----------------------------------------------------