Dear TECHNETers, It is my first post to this list, please forgive me if I ask an already posted question, but I could not find any answer to my problem. We have received, populated and soldered a set of 50 boards which have voids in the gold plating layer into holes (either PTH and via holes). We have discovered the problem because of a poor vertical fill of the holes at wave soldering. Is there any standard for this parameter ? Neither IPC nor PERFAG mention anything about this, they just state on copper plating. Is there any risk of corrosion in the future for these boards ? (they will be installed in factories, means in "standard" environnement in terms of humidity and temperature ) If yes, how would you prevent it ? ( we cannot post solder the holes, because of the large quantity of these and also because many of them are hidden under SMD part; I would personnaly would use conformal coating) Many thanks for your help and kind regards Marie Magnin QA Manager FIRSTEC SA Rue du Grand Pré 70 CH 1211 Genève 2 Tél : +41(0)22 918 36 85 Fax : +41(0)22 918 36 93 mailto:[log in to unmask] http://www.firstec.ch --------------------------------------------------- Technet Mail List provided as a free service by IPC using LISTSERV 1.8e To unsubscribe, send a message to [log in to unmask] with following text in the BODY (NOT the subject field): SIGNOFF Technet To temporarily halt or (re-start) delivery of Technet send e-mail to [log in to unmask]: SET Technet NOMAIL or (MAIL) To receive ONE mailing per day of all the posts: send e-mail to [log in to unmask]: SET Technet Digest Search the archives of previous posts at: http://listserv.ipc.org/archives Please visit IPC web site http://www.ipc.org/html/forum.htm for additional information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700 ext.5315 -----------------------------------------------------