Graham, Doug and other wise persons on this topic, **Wise person? Never. Wise guy.... maybe...... In the absence of an absolute cleanliness figure for boards, for all the goods reasons given, is there then a reliable procedure / formula / guideline or even recommendation that could tell me how to determine what the cleanliness level for our boards should be? i.e. instead of giving us the fish (or not), can you teach us how to fish so that we can catch our own? **Well, when going after walleye, the king of good-eatin' fish, I prefer a white Mr. Twister on my flyline and..... oh, wait, you were speaking metaphorically.....never mind. **In order to understand what value your boards SHOULD be, you need to understand two things: (1) the residues present and (2) the effects of those residues on circuit board reliability in your end use environment. **In order to understand (1), you need to understand the residue detection methods, their pros and cons, and the proper time and place to use them. These are merely tools and you have to understand when you can and can't use them. Can't turn a phillips head screw with a 15 mm box end wrench, that sort of thing. To understand (1) you need to think about the soils that are present on a circuit board and how you measure them. Do you measure them in-situ, as with surface reflectance FT-IR, or do you extract them for analysis? Each has its merits and drawbacks. **And, after you understand (1), you must determine what those residues mean and if the residue levels found constitute a hazard to reliability. So you find you have polypropylene glycol on your boards. So you find 15 micrograms of bromide per square inch on your assemblies. What does it mean? Residues will generally negatively impact reliability in an electrochemical failure mechanism. You need an ionic contaminant, a power source, and moisture to fuel such a failure mechanism. Hence, you would need to do some accelerated testing in a humid environment to determine if the residues constitute a problem. What is a proper accelerating test? Good question, wish I knew the answer. Do you have an environmental stress test that you normally do to catch infant mortality kinds of failures? Here at Rockwell Collins (maker of the worlds finest avaiation electronics, thank you very much), we use thermal cycling on product before it goes out the door. An accelerated test would be to do this kind of cycling under power until failure occurs. Alternative, you could subject your hardware to Bellcore conditions (35C, 85% RH) under power until failure. Look for signs of dendritic growth, corrosion, or electrical leakage or false function. Do a correlation study between the residue detection method and the electrical accelerating test so that you can get an idea of what is a good residue and what is a bad residue and where the breakpoints lie. What is an acceptable amount of time in an accelerated test? Another question I wish I had the answer to. Go as long as you can afford. 1000 hours has a nice ring to it. As my good friend John Sohn once said "Every company has to go and do the HARD work". **To go back to your metaphor, I can't teach you how to fish because it depends on freshwater or salt water, pan fish or trophy fish, spring summer or late fall, US, Carribean, etc.....I could talk about how I fish, but others have acceptable ways of fishing too. You know, now I gonna be thinking about walleye fishing all day....... If we can at least calculate what the cleanliness figure SHOULD be for, say, our multilayer class 3 I/O board, made of FR4, finished with HASL, ENIG, ImAg, Immersion Tin, etc, with an LPI solder mask, assembled with water soluble fluxes, coated with an acrylic, used in a tropical climate of high humidity and high ground temperature, or over the North Pole for up to 15 years, with a known vibration profile for the 'plane it's being used in, etc., etc., - if we can calculate a cleanliness figure for that, then we know what we have to test for. **If you are looking for a starting point, look in J-HDBK-001, section 8. The values for ion chromatography come from CSL and represent a fair amount of experience in determining what cleanliness levels should be for various flux technologies. We found that for epoxy-glass boards, solder masked, with tin-lead metalization (HASL or fused), chloride levels should be less than 2.0 micrograms per square inch, bromide less than 12 micrograms per square inch and sulfate less than 3 micrograms per square inch. For boards with alternative plating (cold plated processes) like silver or palladium or gold, chloride should be less than 1.0 micrograms per square inch, bromide less than 10 ug/in2 and sulfate less than 2 ug/in2. These are for ion chromatography per IPC-TM-650, method 2.3.28. You can look at the CSL website (www.residues.com) if you want to go into more depth. I should stress that these values are a good starting point if you have no clue. You still have to do the correlation studies to determine what the residues mean to your product. The only questions then are "what are the best cleaning machines and methods to achieve that figure?", and "what are the best equipment and procedures for measuring that the figure has been achieved?". **You would find as many answers to this question as you would people to ask. Personally, I like the chemistries from Kyzen Corporation (we use Aquanox SSA and Ionox FCR) and Envirosense (Envirogold 816), with in-line aqueous cleaning. I like batch cleaning less and hand cleaning least of all. It all boils down to the soils to be removed (i.e. what fluxes are you using) and the susceptibilities (e.g. water intolerance) of the hardware being cleaned. Is the SEC test all-embracing - i.e. is it actually a fair measure of how clean a board is of all 'hazzardous' contaminants, or are there other contaminant types that the SEC test won't recognise but still cause problems with boards in the field? Should we be conducting a series of cleanliness tests in order to cover all bases? In other words, should different cleanliness tests be used depending on the chemistries that went into the boards' manufacture. **Is it all embracing? Heavens no. Is it very common, yes. There are a host of problems with SEC testers and you can go back through the Technet archives and find where either I or Brian Ellis has expounded on the topic. IPC also has some technical papers on the topic. I have seen many cases where an ionic cleanliness tester found substrates clean as a whistle, only to corrode and fail in the field. SEC testers are for process control, not product acceptance, although they are frequently used for the latter. Should different tests be used? Yes, more data points are better than one data point or no data points, but the testing must be well founded. As Susan Mansilla indicated recently, she views the IPA/water extraction as bringing too much bromine to the surface and skewing the test. Maybe, maybe not. Is bare board cleanliness different from assembly cleanliness, should it be and, if so, why? **I would say yes. In my experience, residues that are on bare boards tend to get locked in once the boards go through the first reflo cycle. They are very difficult to remove after that, so even if you have cleaning in assembly, you may not be able to remove the fabrication residues. Determining bare board cleanliness is easier than assembly cleanliness because there is usually no complicating factors like residues from components or flux residues. Determining how clean bare boards need to be is harder, since it depends a great deal on your materials sets, your assembly process, and you end use environment. How much cleanliness margin do you need for your process? How robust are your assemblies to residues? There is no easy way to do this. This is the HARD work. Doug Pauls Rockwell Collins --------------------------------------------------------------------------------- Technet Mail List provided as a free service by IPC using LISTSERV 1.8e To unsubscribe, send a message to [log in to unmask] with following text in the BODY (NOT the subject field): SIGNOFF Technet To temporarily halt or (re-start) delivery of Technet send e-mail to [log in to unmask]: SET Technet NOMAIL or (MAIL) To receive ONE mailing per day of all the posts: send e-mail to [log in to unmask]: SET Technet Digest Search the archives of previous posts at: http://listserv.ipc.org/archives Please visit IPC web site http://www.ipc.org/html/forum.htm for additional information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700 ext.5315 ---------------------------------------------------------------------------------