"PCB Man" ....( Do you have a real name instead of an anonymous handle? )
 
To the best of my knowledge, "Daisy chain" routing is used to reduce signal reflections on the clock lines caused by 'stubs' or un-terminated trace ends in high speed logic. This effect is more troublesome as you work with higher speed logic with fast transition times.  A PROPERLY TERMINATED 'Daisy chain' clock line will act in a predictable manner, will be simulatable, and if you have many receivers on the clock line you want to avoid having timing issues with the chips receiving the clock pulses inaccurately and triggering off of false echoes that are reflected back down the line out of time with the clock pulses. I would guess the EE would be the most concerned about the structure of the clock lines on your board and I would suggest you go over his/her concerns and try to implement them as they advise. Perhaps there are other designers on this list server that would like to add to my comments. :)
Regards,

Bill Brooks

-----Original Message-----
From: Pcb Man [mailto:[log in to unmask]]
Sent: Tuesday, August 27, 2002 5:10 AM
To: [log in to unmask]
Subject: [DC] Clock Signal routing

Hi Everyone,

I would like to know whether DAISY chain type routing is ok for routing CLOCK signals. Will this be of any help with respect to the signal integrity point of view?

As far as I know about DAISY chaining, it unnecessarily increases the length of any signal to which this technique is applied for routing.

Which is the best possible way of shielding the clock signals ( the closk signal on my board comes out from a BGA)

Any suggestions/answers ?


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