Gary, The biggest difference that stands out from the stackup that was functional and the the stackup that had problems is the prepreg thickness between the two 2 oz. copper planes. The stackup that failed had only .004 of preg. which is very marginal considering that 2 oz. copper is .0027 thick and you have back to back planes of this thickness. Do you know how many sheets of preg was used to achieve the .004?, as in 1 sheet of 2113 or 3 sheets of 106? This resin content can become critical when putting only .004 preg between two 2 ounce planes. Tony Steinke AIT-Atlanta Inc. ----- Original Message ----- From: "gacrowell" <[log in to unmask]> To: <[log in to unmask]> Sent: Wednesday, July 10, 2002 11:29 AM Subject: [TN] Stackup specification, tolerance, power plane resonance? > I'm looking for some guidance regarding stackup specifications. Its a long > story, I hope you'll bear with me. > > We had a fairly complex board fabbed and working. Over a couple of earlier > versions, we had built about 60 of the boards. The stackup for these > versions of the board is listed below. You can see that it has 4 internal > impedance controlled routing layers, plus some heavy copper internal power > planes. The board consumes some pretty high current, and distributes quite > a few different voltages. > > Note the 3 mil spacing between planes, which is placed between power and > ground, just because it was thought to be a good idea for the (patented, > unmentionable) interplane "C" word. > > On a similar, but different board, where the stackup had also listed 3 mils > between planes, the stackup was implemented by the fabricator with a single > prepreg sheet, and this apparently resulted in resin starvation in some > areas and we got some very exciting interplane shorts. (Other fab houses > had implemented the same stackup with two thinner prepregs.) We haven't > desired to specify lamination material in the past, preferring to leave the > implementation to the board house. > > So now it comes time to do a new 'production' version (our production > quantities are very low, never numbering more than a hundred boards or so). > A couple of last wires are incorporated in the layout, and just to be safe, > the stackup is changed to eliminate the 3 mil interplane spacings, changing > them to 4 mil. This stackup is also listed below. Other interplane > spacings have been reduced to maintain the thickness. > > This new board was ordered from a contract assembler, and that assembler > chose the board house and placed the order, using our specifications. We > have no issue with the board house chosen, its a perfectly reputable house > that I knew of, and I worked with them resolving minor issues in the board > fab on this and other boards. > > Now comes the problem. On the new board, one aspect, completely unrelated > to the minor wire changes, does not work. Same components (even swapped > components from a working, older version), same component placements and > routing. Impedance on signal layers seems to be within spec (more checking > to be done). Some of the boards can be gotten to work (sometimes > intermittently), by adding caps around the particular chip that is giving > the problem, some gotten to work by adding bulk capacitance on the board, > and some aren't working yet regardless of changes. > > The board is liberally populated with 0603 .01uF, and 0508 .1uF caps, and > 33uF tants. > > The boards that work with the addition of bulk caps seems to suggest that we > may be shy in that area. But change in operation with other caps seems to > suggest that we have a power plane resonance problem. More testing is being > done. > > The engineer on this board is understandably frustrated, and complains that > the stackup should not have been changed from the earlier version, and that > the stackup should be specified as to the exact interplane thickness. The > new boards are .005" thicker than the old, but within the .093 +/-.008 > tolerance. > > I have tried to explain that (to my knowledge) it is common to not specify > exact laminate material, and that recipes for stackups to achieve certain > thicknesses can change from fabricator to fabricator, Er changes from > supplier to supplier, and a dozen other factors can change with the wind and > phase of the moon. The final target as I understand it is that impedance, > overall thickness, and copper weights are requirements that must be met > within tolerance, but that the fabricator will adjust as required within his > process to hit those specs. > > So the questions: > > Is it time to specify laminate material in detail? Where do I start? Do I > get the laminate selection from each particular fabricator, or require that > they buy what I specify? Will this affect cost? > > Should I get the exact stackup recipe from the fabricator and require this > be maintained for new versions or other board houses? > > Should I be placing a tolerance on interplane thicknesses? Would this > affect cost? > > What should have been done to avoid this particular situation? > > > Your comments and suggestions would be appreciated. > > Gary Crowell > Micron Technology > > > (fixed pitch font is probably required to get these to line up correctly) > EARLY VERSION STACKUP: > Filename Layer Cu plating prepreg est trace trace > oz oz in. width in. D-Code > ============= ========= ==== ======= ======= ========= ====== > > 20060r1.TSP top paste > > 20060r1.TSK top silk > 20060r1.TSM top mask > > 20060r1.BRD board outline > > 20060r1.L01 top .5 1.0 .0065 > prepreg .004 > 20060r1.L02 plane .5 > core .004 > 20060r1.L03 signal .5 .005 > prepreg .005 > 20060r1.L04 signal .5 > core .004 > 20060r1.L05 plane 1.0 .005 > prepreg .003 > 20060r1.L06 plane 1.0 > core .006 > 20060r1.L07 plane 1.0 > prepreg .003 > 20060r1.L08 plane 1.0 > core .003 > 20060r1.L09 plane 2.0 > prepreg .006 > 20060r1.L10 plane 2.0 > core .003 > 20060r1.L11 plane 1.0 > prepreg .003 > 20060r1.L12 plane 1.0 > core .006 > 20060r1.L13 plane 1.0 > prepreg .003 > 20060r1.L14 plane 1.0 > core .004 > 20060r1.L15 signal .5 .005 > prepreg .005 > 20060r1.L16 signal .5 .005 > core .004 > 20060r1.L17 plane .5 > prepreg .004 > 20060r1.L18 bottom .5 1.0 .0065 > > 20060r1.BSM bottom mask > 20060r1.BSK bottom silk > > 20060r1.BSP bottom paste > > finished thickness: 0.093" +.008"/-0.008" > > > > LATEST VERSION STACKUP: > Filename Layer Cu plating prepreg est trace trace > oz oz in. width in. D-Code > ============= ========= ==== ======= ======= ========= ====== > > 20060R3.FAB fab > > 20060R3.TSP top paste > > 20060R3.TSK top silk > 20060R3.TSM top mask > > 20060R3.L01 top .5 1.0 .0065 > prepreg .004 > 20060R3.L02 plane .5 > core .004 > 20060R3.L03 signal .5 .005 > prepreg .005 > 20060R3.L04 signal .5 > core .004 > 20060R3.L05 plane 1.0 .005 > prepreg .004 > 20060R3.L06 plane 1.0 > core .004 > 20060R3.L07 plane 1.0 > prepreg .004 > 20060R3.L08 plane 1.0 > core .004 > 20060R3.L09 plane 2.0 > prepreg .004 > 20060R3.L10 plane 2.0 > core .004 > 20060R3.L11 plane 1.0 > prepreg .004 > 20060R3.L12 plane 1.0 > core .004 > 20060R3.L13 plane 1.0 > prepreg .004 > 20060R3.L14 plane 1.0 > core .004 > 20060R3.L15 signal .5 .005 > prepreg .005 > 20060R3.L16 signal .5 .005 > core .004 > 20060R3.L17 plane .5 > prepreg .004 > 20060R3.L18 bottom .5 1.0 .0065 > > 20060R3.BSM bottom mask > 20060R3.BSK bottom silk > > 20060R3.BSP bottom paste > > finished thickness: 0.093" +.008"/-0.008" > > -------------------------------------------------------------------------- ------- > Technet Mail List provided as a free service by IPC using LISTSERV 1.8d > To unsubscribe, send a message to [log in to unmask] with following text in > the BODY (NOT the subject field): SIGNOFF Technet > To temporarily halt or (re-start) delivery of Technet send e-mail to [log in to unmask]: SET Technet NOMAIL or (MAIL) > To receive ONE mailing per day of all the posts: send e-mail to [log in to unmask]: SET Technet Digest > Search the archives of previous posts at: http://listserv.ipc.org/archives > Please visit IPC web site http://www.ipc.org/html/forum.htm for additional > information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700 ext.5315 > -------------------------------------------------------------------------- ------- --------------------------------------------------------------------------------- Technet Mail List provided as a free service by IPC using LISTSERV 1.8d To unsubscribe, send a message to [log in to unmask] with following text in the BODY (NOT the subject field): SIGNOFF Technet To temporarily halt or (re-start) delivery of Technet send e-mail to [log in to unmask]: SET Technet NOMAIL or (MAIL) To receive ONE mailing per day of all the posts: send e-mail to [log in to unmask]: SET Technet Digest Search the archives of previous posts at: http://listserv.ipc.org/archives Please visit IPC web site http://www.ipc.org/html/forum.htm for additional information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700 ext.5315 ---------------------------------------------------------------------------------