Thanks for replying Rick, :) I personally find it difficult to express things without pictures... you do a very good job of it and I know it takes some careful thought to create mental pictures with words. My attempt at teaching is really forcing me to develop those 'muscles'. I did also receive some responses on the DC list and they were very interesting. Roy Beckman from Harris in Alberta Canada called me on the phone to talk about the board. (We competed in TOPGUN at PCB WEST in 2000). He was suspecting the impedance matching approach to the board, along with some of the other e-mail respondents. We discussed many potential possibilities regarding the makeup of the board and its parameters. Phil Dutton had some very valid observations as did Dave Ricketts over at Pertek and Jami Smith as well. Scott McCurdy was also pointing out the potential for 'potato chip' effects to happen with an asymmetrical construction. In fact, one respondent suggested that the board might be designed to be matched for 110 ohms which they say is the natural impedance of a 0.050" pitch ribbon cable with signal/gnd/signal/gnd pinning arrangements. I have seen some crazy stuff in my career and would not want discount that possibility either, in fact it's a fairly clever solution to that potential design problem. (The balanced ground plane construction arrangement would have yielded an impedance of approximately 92 ohms...) One suggestion was to add Ground plane fill into layer 3 along with the traces to attempt to balance the plane copper usage for the internal layers... but I would need to also change the dielectric thickness to a symmetrical arrangement to really balance it. The only chip on the board of any significance is the Phillips SA625 High Performance Low power Mixer FM IF system with a High-speed RSSI (Receive Signal Strength Indicator). This is not high speed like logic... the rise time is in the 1.2 micro second range for a 10KHz pulse. The input and output impedance is in the 1K ohm range. The outputs are Audio and data at a slow baud rate... 9600 baud I believe. I'm sure there is much more complexity to the part... but the layout is almost precisely like their manufacturer's recommendations and there is no requirement on the data sheet driving the asymmetrical layer construction. In fact the responsible Engineer for the project says that I give the old engineers too much credit... they most likely started out with a 2 layer board and found they needed 2 more layers of signals and just added them to it keeping the original relationship to the old board's ground plane.... Who can know... But... Since the board works, and the product has already been through DVT (Design Verification Testing) and the risk of changing the geometry of the assembly would require complete re-testing to make sure it did not have some adverse affect and cause the radio to not be functional in some otherwise currently working channels, the plan is, we will live with the asymmetrical construction until some time that we can afford to repeat all the DVT tests on a new version of the radio. (i.e., "If its not broke ... don't fix it...") Of course, I spent time talking with 3 EE's, the Manufacturing Engineer, and the RF Technician that did most of the R&D test and assembly of the radio to determine if there were any known problems to be concerned about, and I asked about potential yield issues with warp or flatness problems... they had none. I also requisitioned an assembly from the stock room to determine that the board was actually constructed with the plane in that fashion, and it was. It is a fairly small board (2" X 4") that has been panelized into a panel of 10 boards, parts on both sides, with routed cut away tabs for de-panelizing. So, it looks as though I will not attempt to change it at this time. Seems working on older designs is a lot like detective work... (where is Inspector Cluesau when you need him?) So, shall I say..."The case is 'sol-ved'"....<with a French accent> :) Bill Brooks PCB Design Engineer , C.I.D., C.I.I. Tel: (760)597-1500 Ext 3772 Fax: (760)597-1510 mailto:[log in to unmask] <http://www.dtwc.com/> http://dc.ipc.org/ <http://home.fda.net/bbrooks/pca/pca.htm P.S. Kathy, I took the message to the Designers Council List server ([log in to unmask]). If you want more of this sort of discussion I find that there is typically a lot of technical PCB design discussion on that list server and you will find a warm reception to your questions and fine council among its members.. - BB -----Original Message----- From: Hartley, Rick [mailto:[log in to unmask]] Sent: Tuesday, June 25, 2002 6:05 AM To: 'PCB College Forum'; 'Brooks,Bill' Subject: RE: [PCBCOLLEGE] Board Layer Stack up Guidelines Bill, I realize you asked this question through the wrong forum, but since I'm not on whatever forum you were targeting I'll answer you through this one. First, the board IS at risk of warp and twist. ANY board that's not a balanced construction is in danger of warp and twist. Balance means two things, balanced copper distribution on each layer, as well as from layer to layer, and balanced dielectric thickness looking from the center of the board stack in both directions through the stack. Obviously this board has imbalanced dielectrics. Having said that, most fabricators who do RF type boards can maintain a flat board even when the dielectrics are this imbalanced. Make no mistake about it, there will be a cost penalty. If you send this board to 'Bob's Corner Shop' or any low cost vendor who deals only in FR4 they'll piss and moan about the imbalance and tell you that "you'll get what you get". If you want a board of this type to be fabed with few ramifications you need to send it to a vendor who deals with RF/Microwave boards on a regular basis. Again it will be much more expensive. So why would someone intentionally design a board that has potential cost and/or fab issues? In the RF world wide traces and fairly thick dielectrics are the 'norm'. Reflections due to impedance discontinuities are deadly in an Analog circuit. Even very small reflections that digital circuits wouldn't see at all can destroy the performance of an RF circuit. Tight control of impedance is essential, hence the thick dielectric between the top layer and the ground plane. If you have wide traces and thick dielectrics the manufacturing tolerance on each has much less effect than would be the case with thin traces and thin dielectrics, so it's then possible to maintain very tight control of the 50 ohm lines in the RF section (or 75 ohms, as the case may be). Add to this the fact that the designers were probably faced with either a very dense digital section, where they needed fairly narrow traces and thin dielectrics, or they were faced with an overall board thickness requirement (or both) and you can easily explain why the board is stacked this way. I spent a number of years in the RF world and saw this kind of thing very frequently. Before you change the design make certain you try to understand all the parameters the original designers were faced with. It's been my experience that circuit design engineers often DO NOT think about DFM and things like this board can result from their skewed thinking. It's up to designers who understand these issues to keep them straight. That may have been the case here and maybe a different stack up can be used with no problem, but it's possible the original engineer and designer did this knowing exactly what they were doing and knowing there would be a cost penalty, but also knowing they had no choice. Regards, Rick Rick Hartley, CID Chairman, IPC Designers Council Senior Staff Engineer Applied Innovation Inc. 5800 Innovation Drive Dublin, Ohio - 43016 [log in to unmask] (614) 798-2000 (x2026) (614) 923-1167 (direct) (614) 798-1770 (fax) -----Original Message----- From: Brooks,Bill [mailto:[log in to unmask]] Sent: Monday, June 24, 2002 6:01 PM To: [log in to unmask] Subject: [PCBCOLLEGE] Board Layer Stack up Guidelines Hi folks, I have a board that was defined with an asymmetrical stack up and I am concerned about the cost issues with leaving it alone... Since we are changing the board, I thought to check for any issues with the design package and found this anomaly... It looks like this: .063 overall thick FR4 material 0.070 max ________________________ Top Layer Signal .032 separation--->________________________ GND Plane ________________________ Internal Signal 0.00 ________________________ Bottom layer Signal The odd part being, the forced separation between the ground plane and the top signal layer where the RF components reside, primarily. Have you had any experience with this sort of thing? Is there a good reference I can refer to that deals with Board stack up issues? Do you think the board is at risk for flatness problems? - Bill Brooks ---------------------------------------------------------------------------- ----- PCBCollege Mail List provided as a free service by IPC using LISTSERV 1.8d To unsubscribe, send a message to [log in to unmask] with following text in the BODY (NOT the subject field): SIGNOFF PCBCollege Search previous postings at: www.ipc.org > On-Line Resources & Databases > E-mail Archives Unlisted Archives > Type in "PCBCollege". Please visit IPC web site (http://www.ipc.org/html/forum.htm) for additional information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700 ext.5315 ---------------------------------------------------------------------------- ----- --------------------------------------------------------------------------------- DesignerCouncil Mail List provided as a free service by IPC using LISTSERV 1.8d To unsubscribe, send a message to [log in to unmask] with following text in the BODY (NOT the subject field): SIGNOFF DesignerCouncil. To set a vacation stop for delivery of DesignerCouncil send: SET DesignerCouncil NOMAIL Search previous postings at: www.ipc.org > On-Line Resources & Databases > E-mail Archives Please visit IPC web site http://www.ipc.org/html/forum.htm for additional information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700 ext.5315 ---------------------------------------------------------------------------------