Werner,

Always a pleasure to read your mailings.  I applaud and wholeheartedly agree with your "depends" statement.  It is my perspective that evaluation criteria is not always available; temp cycling conditions, reflow parameters, device quality, substrate configuration and quantity of sample size.  Albeit skeptical on my part, I suspect agenda driven evaluations render predictable results. 
I see the microelectronic packaging scheme of things as a systems approach wherein the propensity to be reliable may not seem to be significant but compared to the propensity to be unreliable it is large.  Indeed the PBGA substrate design that warps will go many fewer cycles than a similar "flat" package regardless of pad definition.   
The cycles I have seen have been
elevated shock from -55 to 125C
nice ramps and dwell times of
-30 to 100C
-55 to 125C
and burn in 80-90F

The -30 to 100C specifically addressed SMD verses NSMD.  Although large voids were present not much correlation to root cause was discussed.

Brad Saunders
Coretec   Boston office
781 858 0783