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Date: Wed, 10 Apr 2002 11:13:08 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Mickey Weiner <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Mickey Weiner <[log in to unmask]>
Subject: Re: 0402 tombstone problem
Mime-Version: 1.0
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Ioan,
We ran a test board long ago which yielded very good results with
round pads.
Very simple: 20-20-20. round 20 mils pads and 20 mil gap. Pay
attention though that
severe copper undercut may change pad size ,and add to this componnets
on the low end
of tolerance and there goes your process. I had also good results
with:
Square pads: x=24mils. gap (x axis) = 20 ;and y=22 . make the corners
round.
Mickey
Mickey Weiner
Sanmina-Sci
Tel: 972-3-9208705
Mobile: 972- 67-467809
>>> [log in to unmask] 10-Apr-02 5:16:31 PM >>>
Hi Dan,
can you give the exact dimensions of the round land pattern?
Thanks,
Ioan
> -----Original Message-----
> From: Dan R. Johnson [SMTP:[log in to unmask]]
> Sent: Wednesday, April 10, 2002 10:22 AM
> To: [log in to unmask]
> Subject: Re: [TN] 0402 tombstone problem
>
> Steve,
> I use round pads to decrease pad size (increase circuit density). A
side
> benefit seems to be less chance of skew, I don't have numbers on
> tombstoning/drawbridging, but product hasn't yelled. I have also
been
> tinkering with the idea of other geometries just haven't come across
the
> right application yet.
> Dan
>
> ----- Original Message -----
> From: [log in to unmask] <mailto:[log in to unmask]>
> To: [log in to unmask] <mailto:[log in to unmask]>
> Sent: Tuesday, April 09, 2002 8:12 PM
> Subject: Re: [TN] 0402 tombstone problem
>
> I just heard something not too long ago, that round pads for
0402's
> are the way to go.
>
> Never heard of that before, but just recently received a board
for
> quote that uses round pads for the 0402 components...anybody else
ever
> heard of this?
>
> Guess I'll find out how it works inna little while, while
pondering
> why a round pad would work better than a square pad....
>
> -Steve Gregory-
>
>
>
>
> Edward,
>
> When we do everything correct on 0402 and 0201 and
still
> have components
> standing-up, we often look to the component
terminations and
> find poor
> plating.
>
> Good luck
> Dave Fish
>
> ----- Original Message -----
> From: "Edward S. Wheeler" <[log in to unmask]>
> To: <[log in to unmask]>
> Sent: Tuesday, April 09, 2002 10:59 AM
> Subject: [TN] 0402 tombstone problem
>
>
> > Hi folks, we are running a new board with 0402 parts
on
> it. It seems that
> > we are having a tombstone problem as well as a
problem
> with parts not
> > staying centered on the pads. We are currently using
20
> mil square pads on
> > the board, with 20 mils of spacing between them. Our
> stencil is 6 mils
> > thick, laser cut and electro polished. The
trapezoidal
> walled apertures
> are
> > slightly reduced, 17 mils square, and centered on
the
> pads. It appears the
> > chip shooter is placing the parts perfectly. We are
using
> eutectic solder
> > paste with an OA flux, and reflowing the parts using
the
> recommended
> profile.
> >
> > Are there any suggestions any of you might have
concerning
> this size of a
> > part? Is there a better stencil design, reflow
profile, or
> pad design that
> > could help us out? I would appreciate any
suggestions.
> >
> > Thanks.
> >
> > Ed
>
>
>
>
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Date: Wed, 10 Apr 2002 11:30:07 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Kathy Kuhlow <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Kathy Kuhlow <[log in to unmask]>
Subject: Re: 0402 tombstone problem
Mime-Version: 1.0
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I heard of the round pad. The logic was that the round pad centers the =
tension on the pad since the mass of the pad is at the component terminatio=
n. =20
Kathy=20
--=_015C8489.00610CD5
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Content-Disposition: attachment; filename="TEXT.htm"
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<META content="MSHTML 6.00.2713.1100" name=GENERATOR></HEAD>
<BODY style="MARGIN-TOP: 2px; FONT: 10pt MS Sans Serif; MARGIN-LEFT: 2px">
<DIV>I heard of the round pad. The logic was that the round pad centers
the tension on the pad since the mass of the pad is at the component
termination. </DIV>
<DIV> </DIV>
<DIV>Kathy </DIV></BODY></HTML>
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Date: Wed, 10 Apr 2002 09:42:06 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
David Douthit <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: David Douthit <[log in to unmask]>
Subject: Re: test method to detect solder joint weakness
X-To: Graham Naisbitt <[log in to unmask]>
MIME-Version: 1.0
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Graham,
That's just what was needed, another acronym! :-)
David A. Douthit
Manager
LoCan LLC
Graham Naisbitt wrote:
> Mary
>
> Noting your question, you might like to contact Montford Instruments here in
> the UK. They specialise in HALT and HASS testing systems but now offer a new
> method called HARASS.
>
> Email: [log in to unmask]
>
> Web: www.montford.co.uk
>
> Hope this might help
>
> Regards Graham Naisbitt
>
> [log in to unmask] <mailto:[log in to unmask]>
>
> Concoat ANNOUNCE their acquisition of the former Multicore SPCID business.
>
> MUST II Solderability Testing Systems -
> CM Cleanliness Testing Systems -
> Auto-SIR Reliability Testing Systems -
> SoldaPro & NEW SoldaPro Wizard Thermal Profilers
>
> For more information please visit our new web site: www.concoatsystems.com
> <http://www.concoatsystems.com>
>
> Concoat Limited
> Alasan House, Albany Park
> Camberley GU16 7PH - UK
>
> www.concoat.co.uk <http://www.concoat.co.uk>
>
> Phone: +44 1276 691100
> Fax: +44 1276 691227
> Mobile: +44 79 6858 2121
>
> > -----Original Message-----
> > From: TechNet [mailto:[log in to unmask]]On Behalf Of Mary Lin
> > Sent: 09 April 2002 17:53
> > To: [log in to unmask]
> > Subject: [TN] test method to detect solder joint weakness
> >
> >
> > Hello-
> >
> > As we know both thermal cycling test and RS vibration test in HALT (Highly
> > Accerlated Life Test) are effective in detecting solder joint related
> > failures.
> > Right now we are in the process of developing HASS profile, can
> > someone help
> > me on fllowing questions?
> >
> > (1)Which test is more efficient, thermal cycling or RS Vibration?
> > (2) how to correlate number of cycles of test (either thermal cycling or
> > vibration) with service time in the field application?
> >
> > Thanks for your time.
> >
> > Mary
> > _________________________________________________________________________
> >
> > Live, laugh, and chat with friends about BMWs, Porsches, Jaguars
> > and the new MINI
> > at The World's Largest Auto Enthusiast Site
> > http://www.roadfly.org/
> >
> > ------------------------------------------------------------------
> > ---------------
> > Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
> > To unsubscribe, send a message to [log in to unmask] with following text in
> > the BODY (NOT the subject field): SIGNOFF Technet
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> > Please visit IPC web site http://www.ipc.org/html/forum.htm for additional
> > information, or contact Keach Sasamori at [log in to unmask] or
> > 847-509-9700 ext.5315
> > ------------------------------------------------------------------
> > ---------------
> >
>
> ---------------------------------------------------------------------------------
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=========================================================================
Date: Wed, 10 Apr 2002 09:42:20 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Jac Kroeker <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Jac Kroeker <[log in to unmask]>
Subject: Re: 0402 tombstone problem
X-To: "Tempea, Ioan" <[log in to unmask]>
In-Reply-To: <[log in to unmask]
.qc.ca>
Mime-Version: 1.0
Content-Type: text/plain; charset="us-ascii"; format=flowed
Hi TN assemblers;
Having followed this thread, I haven't seen any body point a finger at the
board finish as a cause of tombstoneing. I always thought that HASL or
poorly HASSLED boards contributed to tombstoneing. We went to immersion
White Tin years ago in order to make our boards more manufacturable. Is
there a comment from the assembly community about tombstoning and the
topography of the bare board?
Jac Kroeker
Omni Graphics Ltd.
www.omnigraph.com
At 11:16 AM 04/10/2002 -0400, you wrote:
>Hi Dan,
>
>can you give the exact dimensions of the round land pattern?
>
>Thanks,
>Ioan
>
> > -----Original Message-----
> > From: Dan R. Johnson [SMTP:[log in to unmask]]
> > Sent: Wednesday, April 10, 2002 10:22 AM
> > To: [log in to unmask]
> > Subject: Re: [TN] 0402 tombstone problem
> >
> > Steve,
> > I use round pads to decrease pad size (increase circuit density). A side
> > benefit seems to be less chance of skew, I don't have numbers on
> > tombstoning/drawbridging, but product hasn't yelled. I have also been
> > tinkering with the idea of other geometries just haven't come across the
> > right application yet.
> > Dan
> >
> > ----- Original Message -----
> > From: [log in to unmask] <mailto:[log in to unmask]>
> > To: [log in to unmask] <mailto:[log in to unmask]>
> > Sent: Tuesday, April 09, 2002 8:12 PM
> > Subject: Re: [TN] 0402 tombstone problem
> >
> > I just heard something not too long ago, that round pads for 0402's
> > are the way to go.
> >
> > Never heard of that before, but just recently received a board for
> > quote that uses round pads for the 0402 components...anybody else ever
> > heard of this?
> >
> > Guess I'll find out how it works inna little while, while pondering
> > why a round pad would work better than a square pad....
> >
> > -Steve Gregory-
> >
> >
> >
> >
> > Edward,
> >
> > When we do everything correct on 0402 and 0201 and still
> > have components
> > standing-up, we often look to the component terminations and
> > find poor
> > plating.
> >
> > Good luck
> > Dave Fish
> >
> > ----- Original Message -----
> > From: "Edward S. Wheeler" <[log in to unmask]>
> > To: <[log in to unmask]>
> > Sent: Tuesday, April 09, 2002 10:59 AM
> > Subject: [TN] 0402 tombstone problem
> >
> >
> > > Hi folks, we are running a new board with 0402 parts on
> > it. It seems that
> > > we are having a tombstone problem as well as a problem
> > with parts not
> > > staying centered on the pads. We are currently using 20
> > mil square pads on
> > > the board, with 20 mils of spacing between them. Our
> > stencil is 6 mils
> > > thick, laser cut and electro polished. The trapezoidal
> > walled apertures
> > are
> > > slightly reduced, 17 mils square, and centered on the
> > pads. It appears the
> > > chip shooter is placing the parts perfectly. We are using
> > eutectic solder
> > > paste with an OA flux, and reflowing the parts using the
> > recommended
> > profile.
> > >
> > > Are there any suggestions any of you might have concerning
> > this size of a
> > > part? Is there a better stencil design, reflow profile, or
> > pad design that
> > > could help us out? I would appreciate any suggestions.
> > >
> > > Thanks.
> > >
> > > Ed
> >
> >
========================================================
Omni Graphics Ltd. 2 - 12760 Bathgate Way, Richmond BC, Canada V6V 1Z4
Tel 604-276-9717 Fax 604-276-2514
[log in to unmask] www.omnigraph.com
========================================================
---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
=========================================================================
Date: Wed, 10 Apr 2002 19:30:59 +0200
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"D.Terstegge" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "D.Terstegge" <[log in to unmask]>
Subject: Re: 0402 tombstone problem
X-To: "Edward S. Wheeler" <[log in to unmask]>
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="----=_NextPart_000_0015_01C1E0C6.3DF81720"
This is a multi-part message in MIME format.
------=_NextPart_000_0015_01C1E0C6.3DF81720
Content-Type: text/plain;
charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
Hi Ed,=20
A good article called "TOMBSTONING OF 0402 AND 0201 COMPONENTS: A STUDY =
EXAMINING THE EFFECTS OF VARIOUS PROCESS AND DESIGN PARAMETERS ON =
ULTRA-SMALL PASSIVE DEVICES" used to be on the Plexus website.=20
Seems it disappeared when Plexus changed their website, but I uploaded =
the document to my own webspace, where you can still download it at =
http://www.smtinfo.net/docs/tombstoning.pdf.
What do you think, am I violating copyrights this way ? (comments =
welcome, off-Technet would be best I guess)=20
Anyway, hope it gives you some clues...
Daan Terstegge
http://www.smtinfo.net
----- Original Message -----=20
From: Edward S. Wheeler=20
To: [log in to unmask]
Sent: Tuesday, April 09, 2002 7:59 PM
Subject: [TN] 0402 tombstone problem
Hi folks, we are running a new board with 0402 parts on it. It seems =
that
we are having a tombstone problem as well as a problem with parts not
staying centered on the pads. We are currently using 20 mil square =
pads on
the board, with 20 mils of spacing between them. Our stencil is 6 mils
thick, laser cut and electro polished. The trapezoidal walled =
apertures are
slightly reduced, 17 mils square, and centered on the pads. It appears =
the
chip shooter is placing the parts perfectly. We are using eutectic =
solder
paste with an OA flux, and reflowing the parts using the recommended =
profile.
Are there any suggestions any of you might have concerning this size =
of a
part? Is there a better stencil design, reflow profile, or pad design =
that
could help us out? I would appreciate any suggestions.
Thanks.
Ed
=
-------------------------------------------------------------------------=
--------
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To unsubscribe, send a message to [log in to unmask] with following text =
in
the BODY (NOT the subject field): SIGNOFF Technet
To temporarily halt delivery of Technet send e-mail to =
[log in to unmask]: SET Technet NOMAIL
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[log in to unmask]: SET Technet Digest
Search the archives of previous posts at: =
http://listserv.ipc.org/scripts/wa.exe?S1=3Dtechnet
Please visit IPC web site http://www.ipc.org/html/forum.htm for =
additional
information, or contact Keach Sasamori at [log in to unmask] or =
847-509-9700 ext.5315
=
-------------------------------------------------------------------------=
--------
------=_NextPart_000_0015_01C1E0C6.3DF81720
Content-Type: text/html;
charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META http-equiv=3DContent-Type content=3D"text/html; =
charset=3Diso-8859-1">
<META content=3D"MSHTML 5.50.4134.600" name=3DGENERATOR>
<STYLE></STYLE>
</HEAD>
<BODY bgColor=3D#ffffff>
<DIV>Hi Ed, </DIV>
<DIV> </DIV>
<DIV>A good article called "TOMBSTONING OF 0402 AND 0201 COMPONENTS: A =
STUDY=20
EXAMINING THE EFFECTS OF VARIOUS PROCESS AND DESIGN PARAMETERS ON =
ULTRA-SMALL=20
PASSIVE DEVICES" used to be on the Plexus website. </DIV>
<DIV>Seems it disappeared when Plexus changed their =
website, but=20
I uploaded the document to my own webspace, where you can still download =
it at=20
<A=20
href=3D"http://www.smtinfo.net/docs/tombstoning.pdf">http://www.smtinfo.n=
et/docs/tombstoning.pdf</A>.</DIV>
<DIV>What do you think, am I violating copyrights this way=20
? (comments welcome, off-Technet would be best I =
guess) </DIV>
<DIV>Anyway, hope it gives you some clues...</DIV>
<DIV> </DIV>
<DIV>Daan Terstegge</DIV>
<DIV><A href=3D"http://www.smtinfo.net">http://www.smtinfo.net</A></DIV>
<DIV> </DIV>
<DIV> </DIV>
<DIV>----- Original Message ----- </DIV>
<BLOCKQUOTE=20
style=3D"PADDING-RIGHT: 0px; PADDING-LEFT: 5px; MARGIN-LEFT: 5px; =
BORDER-LEFT: #000000 2px solid; MARGIN-RIGHT: 0px">
<DIV=20
style=3D"BACKGROUND: #e4e4e4; FONT: 10pt arial; font-color: =
black"><B>From:</B>=20
<A [log in to unmask]
href=3D"mailto:[log in to unmask]">Edward S. Wheeler</A> </DIV>
<DIV style=3D"FONT: 10pt arial"><B>To:</B> <A [log in to unmask]
href=3D"mailto:[log in to unmask]">[log in to unmask]</A> </DIV>
<DIV style=3D"FONT: 10pt arial"><B>Sent:</B> Tuesday, April 09, 2002 =
7:59=20
PM</DIV>
<DIV style=3D"FONT: 10pt arial"><B>Subject:</B> [TN] 0402 tombstone=20
problem</DIV>
<DIV><BR></DIV>Hi folks, we are running a new board with 0402 parts on =
it. It=20
seems that<BR>we are having a tombstone problem as well as a problem =
with=20
parts not<BR>staying centered on the pads. We are currently using 20 =
mil=20
square pads on<BR>the board, with 20 mils of spacing between them. Our =
stencil=20
is 6 mils<BR>thick, laser cut and electro polished. The trapezoidal =
walled=20
apertures are<BR>slightly reduced, 17 mils square, and centered on the =
pads.=20
It appears the<BR>chip shooter is placing the parts perfectly. We are =
using=20
eutectic solder<BR>paste with an OA flux, and reflowing the parts =
using the=20
recommended profile.<BR><BR>Are there any suggestions any of you might =
have=20
concerning this size of a<BR>part? Is there a better stencil design, =
reflow=20
profile, or pad design that<BR>could help us out? I would appreciate =
any=20
=
suggestions.<BR><BR>Thanks.<BR><BR>Ed<BR><BR>----------------------------=
-----------------------------------------------------<BR>Technet=20
Mail List provided as a free service by IPC using LISTSERV 1.8d<BR>To=20
unsubscribe, send a message to <A=20
href=3D"mailto:[log in to unmask]">[log in to unmask]</A> with following =
text=20
in<BR>the BODY (NOT the subject field): SIGNOFF Technet<BR>To =
temporarily halt=20
delivery of Technet send e-mail to <A=20
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NOMAIL<BR>To=20
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href=3D"mailto:[log in to unmask]">[log in to unmask]</A>: SET Technet=20
Digest<BR>Search the archives of previous posts at: <A=20
=
href=3D"http://listserv.ipc.org/scripts/wa.exe?S1=3Dtechnet">http://lists=
erv.ipc.org/scripts/wa.exe?S1=3Dtechnet</A><BR>Please=20
visit IPC web site <A=20
=
href=3D"http://www.ipc.org/html/forum.htm">http://www.ipc.org/html/forum.=
htm</A>=20
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Date: Wed, 10 Apr 2002 13:36:02 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Randy Bock Sr." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Randy Bock Sr." <[log in to unmask]>
Subject: Re: 0402 tombstone problem
X-To: Jac Kroeker <[log in to unmask]>
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Interesting thought
----- Original Message -----
From: Jac Kroeker <[log in to unmask]>
To: <[log in to unmask]>
Sent: Wednesday, April 10, 2002 12:42 PM
Subject: Re: [TN] 0402 tombstone problem
> Hi TN assemblers;
> Having followed this thread, I haven't seen any body point a finger at the
> board finish as a cause of tombstoneing. I always thought that HASL or
> poorly HASSLED boards contributed to tombstoneing. We went to immersion
> White Tin years ago in order to make our boards more manufacturable. Is
> there a comment from the assembly community about tombstoning and the
> topography of the bare board?
> Jac Kroeker
> Omni Graphics Ltd.
> www.omnigraph.com
>
> At 11:16 AM 04/10/2002 -0400, you wrote:
> >Hi Dan,
> >
> >can you give the exact dimensions of the round land pattern?
> >
> >Thanks,
> >Ioan
> >
> > > -----Original Message-----
> > > From: Dan R. Johnson [SMTP:[log in to unmask]]
> > > Sent: Wednesday, April 10, 2002 10:22 AM
> > > To: [log in to unmask]
> > > Subject: Re: [TN] 0402 tombstone problem
> > >
> > > Steve,
> > > I use round pads to decrease pad size (increase circuit density). A
side
> > > benefit seems to be less chance of skew, I don't have numbers on
> > > tombstoning/drawbridging, but product hasn't yelled. I have also been
> > > tinkering with the idea of other geometries just haven't come across
the
> > > right application yet.
> > > Dan
> > >
> > > ----- Original Message -----
> > > From: [log in to unmask] <mailto:[log in to unmask]>
> > > To: [log in to unmask] <mailto:[log in to unmask]>
> > > Sent: Tuesday, April 09, 2002 8:12 PM
> > > Subject: Re: [TN] 0402 tombstone problem
> > >
> > > I just heard something not too long ago, that round pads for
0402's
> > > are the way to go.
> > >
> > > Never heard of that before, but just recently received a board
for
> > > quote that uses round pads for the 0402 components...anybody else ever
> > > heard of this?
> > >
> > > Guess I'll find out how it works inna little while, while
pondering
> > > why a round pad would work better than a square pad....
> > >
> > > -Steve Gregory-
> > >
> > >
> > >
> > >
> > > Edward,
> > >
> > > When we do everything correct on 0402 and 0201 and still
> > > have components
> > > standing-up, we often look to the component terminations
and
> > > find poor
> > > plating.
> > >
> > > Good luck
> > > Dave Fish
> > >
> > > ----- Original Message -----
> > > From: "Edward S. Wheeler" <[log in to unmask]>
> > > To: <[log in to unmask]>
> > > Sent: Tuesday, April 09, 2002 10:59 AM
> > > Subject: [TN] 0402 tombstone problem
> > >
> > >
> > > > Hi folks, we are running a new board with 0402 parts
on
> > > it. It seems that
> > > > we are having a tombstone problem as well as a problem
> > > with parts not
> > > > staying centered on the pads. We are currently using
20
> > > mil square pads on
> > > > the board, with 20 mils of spacing between them. Our
> > > stencil is 6 mils
> > > > thick, laser cut and electro polished. The trapezoidal
> > > walled apertures
> > > are
> > > > slightly reduced, 17 mils square, and centered on the
> > > pads. It appears the
> > > > chip shooter is placing the parts perfectly. We are
using
> > > eutectic solder
> > > > paste with an OA flux, and reflowing the parts using
the
> > > recommended
> > > profile.
> > > >
> > > > Are there any suggestions any of you might have
concerning
> > > this size of a
> > > > part? Is there a better stencil design, reflow
profile, or
> > > pad design that
> > > > could help us out? I would appreciate any suggestions.
> > > >
> > > > Thanks.
> > > >
> > > > Ed
> > >
> > >
>
> ========================================================
> Omni Graphics Ltd. 2 - 12760 Bathgate Way, Richmond BC, Canada V6V 1Z4
> Tel 604-276-9717 Fax 604-276-2514
> [log in to unmask] www.omnigraph.com
> ========================================================
>
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Date: Wed, 10 Apr 2002 12:37:33 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Kathy Kuhlow <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Kathy Kuhlow <[log in to unmask]>
Subject: Re: Single-sided/Double-sided PCB Reliability
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One point I have used is using an unsupported barrel causes the leads to =
be clinched per 5.2.7.2 which costs more with the added labor. The main =
reason I have found that customers choose unsupported barrels is to save a =
few bucks on the PCB. The added labor reasoning normally gets most =
customers to see the cost savings is really in using a supported barrel =
plus the added bonus of the mechanical strength the barrel does give. =20
Kathy=20
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<DIV>One point I have used is using an unsupported barrel causes the leads to be
clinched per 5.2.7.2 which costs more with the added labor. The main
reason I have found that customers choose unsupported barrels is to save a few
bucks on the PCB. The added labor reasoning normally gets most
customers to see the cost savings is really in using a supported barrel plus the
added bonus of the mechanical strength the barrel does give. </DIV>
<DIV> </DIV>
<DIV>Kathy </DIV></BODY></HTML>
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Date: Wed, 10 Apr 2002 12:40:27 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: 0402 tombstone problem
X-To: Daan Terstegge <[log in to unmask]>
I'm no expert on this or anything else for that matter, but I've changed all
my 0603 pads to rather convential 0402 pads based on an "old" HP study. I
like everything everyone has said. I even like round pads for chips so they
"self" align and, for sure, BGA's for paste release characteristice but
SMQ92J solved that problem - for me. I just don't want poor solder joints.
Whatever happened to home plate pads? I use them for 0402's still.
I don't use HASL on anything anymore so that problem is removed. Also, I try
very hard to eliminate component solderability issues before they occur.
Solderability testing, you know?. That one is difficult at times and don't
even know if it's getting better.
I do still xray from time to time even on chips and leaded devices. It
provides some evidence about how well flux is doing its job relative to
removing oxidation. If it doesn't work well, or if oxidation is excessive,
it can't do its job so voiding is apparent. Having said that, an old can of
workms is opened but this stuff should be vanquished.
MoonMan
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Date: Wed, 10 Apr 2002 14:00:56 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Marsico, James" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Marsico, James" <[log in to unmask]>
Subject: LARGE PWB
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Hello Technet,
We're looking at a concept for a multilayer board (maybe polyimide) that
would be 30" x 8". Don't know how many layers or how thick yet. Is this
conceivable? Bo board houses have this capability? Any foreseen problems?
What would be the largest board size that a typical board shop could
produce, that's 8" wide?
Thanks,
Jim Marsico
Senior Engineer
Production Engineering
EDO Electronics Systems Group
[log in to unmask] <mailto:[log in to unmask]>
631-595-5879
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Date: Wed, 10 Apr 2002 13:02:23 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Keach Sasamori <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Keach Sasamori <[log in to unmask]>
Subject: Listserv etiquette
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It was pointed out to us at IPC that it would be helpful to periodically =
post some guidelines for participating on Technet.
Technet is a technical forum geared discussion of technical, =
manufacturing, process and quality issues of electronic manufacturing. =
Although any type of posts regarding to the above are encouraged, if the =
particular situation is of narrow interest, please consider responding =
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Please check the archives at =
http://listserv.ipc.org/archives/technet.html or =
http://listserv.ipc.org/scripts/wa.exe?S1=3Dtechnet first before =
submitting a post to see if your question has been brought up and =
answered before.=20
When responding to lengthy and/or posts which have been responded to, as =
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footer which is attached to every post and response.
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Send all list commands such as NOMAIL, SIGNOFF, to [log in to unmask], not =
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The Technet community is a constantly evolving and changing community, =
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Each individual's netiquette on the list goes a long way in making this =
a valuable resource for all.
Thank you
-----------------------
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IS Administrator
2215 Sanders Rd.
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Date: Wed, 10 Apr 2002 14:06:46 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
tony steinke <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: tony steinke <[log in to unmask]>
Subject: core fill
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Hello Techies,
Can anyone tell me what type of reliable core fill materials are on the =
market.
I have been looking at the Howefilm and Fiberite, but both have some =
limitations. We have a .050 solid copper core to fill. And the Tg or =
operating temperature must be 170C or greater.=20
Thanks in advance
Tony Steinke
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<DIV><FONT face=3DArial size=3D2>Hello Techies,</FONT></DIV>
<DIV><FONT face=3DArial size=3D2>Can anyone tell me what type of=20
reliable core fill materials are on the market.</FONT></DIV>
<DIV><FONT face=3DArial size=3D2>I have been looking at the Howefilm and =
Fiberite,=20
but both have some limitations. We have a .050 solid =
copper core=20
to fill. A</FONT><FONT face=3DArial size=3D2>nd the Tg or operating =
temperature must=20
be 170C or greater.</FONT> </DIV>
<DIV><FONT face=3DArial size=3D2>Thanks in advance</FONT></DIV>
<DIV><FONT face=3DArial size=3D2>Tony Steinke</FONT></DIV></BODY></HTML>
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Date: Wed, 10 Apr 2002 14:15:31 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
tony steinke <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: tony steinke <[log in to unmask]>
Subject: Re: LARGE PWB
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James,
That is quite large in length, but definitely manufacturable. At 30" active
area
your panel size would probably be 32 to 35" in length. All depends on ones
tooling/fixturing/platen size of the press, and of course experience.
Tony
----- Original Message -----
From: Marsico, James <[log in to unmask]>
To: <[log in to unmask]>
Sent: Wednesday, April 10, 2002 11:00 AM
Subject: [TN] LARGE PWB
> Hello Technet,
> We're looking at a concept for a multilayer board (maybe polyimide) that
> would be 30" x 8". Don't know how many layers or how thick yet. Is this
> conceivable? Bo board houses have this capability? Any foreseen
problems?
> What would be the largest board size that a typical board shop could
> produce, that's 8" wide?
> Thanks,
> Jim Marsico
> Senior Engineer
> Production Engineering
> EDO Electronics Systems Group
> [log in to unmask] <mailto:[log in to unmask]>
> 631-595-5879
>
> --------------------------------------------------------------------------
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> --------------------------------------------------------------------------
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Date: Wed, 10 Apr 2002 14:36:31 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"McMullen, Kerry" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "McMullen, Kerry" <[log in to unmask]>
Subject: Component Lead Touch-up
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Hi,
We have a board with about 12,000 leads. The board is inspected to Class II
standards. We noticed about 300 leads were touched up.
I have not seen anything in IPC for % of leads that can be touched up on a
printed circuit board before the board is considered unacceptable. I don't
know if this data is in IPC 7711 or 7721. I have ordered the manuals
though.
Is there a standard I should be looking for, or is there a % that people
use?
Thanks,
Kerry
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<BODY bgColor=#fff8e0>
<DIV><FONT face=Arial size=2><SPAN
class=085503818-10042002>Hi,</SPAN></FONT></DIV><SPAN class=085503818-10042002>
<DIV><FONT face=Arial size=2><SPAN class=085503818-10042002>We have a board with
about 12,000 leads. The board is inspected to Class II standards. We
noticed about 300 leads were touched up.</SPAN></FONT></DIV>
<DIV><FONT face=Arial size=2><SPAN
class=085503818-10042002></SPAN></FONT> </DIV>
<DIV><FONT face=Arial size=2>I have not seen anything in IPC for % of leads that
can be touched up on a printed circuit board before the board is considered
unacceptable. I don't know if this data is in IPC 7711 or 7721. I
have ordered the manuals though.</FONT></DIV>
<DIV><FONT face=Arial size=2></FONT> </DIV>
<DIV></SPAN><SPAN class=085503818-10042002><FONT face=Arial color=#0000ff
size=2>Is there a standard I should be looking for, or is there a % that people
use?</FONT></SPAN></DIV>
<DIV><SPAN class=085503818-10042002><FONT face=Arial color=#0000ff
size=2></FONT></SPAN> </DIV>
<DIV><SPAN class=085503818-10042002><FONT face=Arial color=#0000ff
size=2>Thanks,</FONT></SPAN></DIV>
<DIV><SPAN class=085503818-10042002><FONT face=Arial color=#0000ff
size=2>Kerry</FONT></SPAN></DIV>
<DIV><FONT face=Arial size=2><SPAN
class=085503818-10042002></SPAN></FONT> </DIV>
<DIV><FONT face=Arial color=#0000ff size=2></FONT> </DIV></BODY></HTML>
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Date: Wed, 10 Apr 2002 14:49:26 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Bev Christian <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Bev Christian <[log in to unmask]>
Subject: Re: 0402 tombstone problem
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Steve,
I understand what you are saying, but Peter spoke specifically about a
possible alloy effect and I was trying to get some more info about that.
Bev
-----Original Message-----
From: Creswick, Steven [mailto:[log in to unmask]]
Sent: April 10, 2002 12:21 PM
To: [log in to unmask]
Subject: Re: [TN] 0402 tombstone problem
Could it be that rather than Sn/Pb composition, it might be related to the
wettability (prior storage conditions) of the components in question -
thereby tying it into the required activity level of the flux?
Considered rectangular pads with rounded corners, or 'rectangular' pads with
semi-circular ends? It has worked on LTCC based product.
Steven Creswick - Gentex.Corp
-----Original Message-----
From: Bev Christian [mailto:[log in to unmask]]
Sent: Wednesday, April 10, 2002 8:46 AM
To: [log in to unmask]
Subject: Re: [TN] 0402 tombstone problem
Peter,
So which is worse - high tin (e.g. Sn/Pb95/5) or relatively "high" lead
(Sn/Pb63/37)?
Bev Christian
Research in Motion
-----Original Message-----
From: Peter Lee [mailto:[log in to unmask]]
Sent: April 10, 2002 12:07 AM
To: [log in to unmask]
Subject: Re: [TN] 0402 tombstone problem
Our experience with eliminating 0402 tombstoning was to try different
no-clean solder paste. We've also found that the parts' end termination
tin/lead % has some negative impact on the yield.
Rgds,
Peter
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of [log in to unmask]
Sent: April 9, 2002 8:13 PM
To: [log in to unmask]
Subject: Re: [TN] 0402 tombstone problem
I just heard something not too long ago, that round pads for 0402's are the
way to go.
Never heard of that before, but just recently received a board for quote
that uses round pads for the 0402 components...anybody else ever heard of
this?
Guess I'll find out how it works inna little while, while pondering why a
round pad would work better than a square pad....
-Steve Gregory-
Edward,
When we do everything correct on 0402 and 0201 and still have components
standing-up, we often look to the component terminations and find poor
plating.
Good luck
Dave Fish
----- Original Message -----
From: "Edward S. Wheeler" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Tuesday, April 09, 2002 10:59 AM
Subject: [TN] 0402 tombstone problem
> Hi folks, we are running a new board with 0402 parts on it. It seems that
> we are having a tombstone problem as well as a problem with parts not
> staying centered on the pads. We are currently using 20 mil square pads on
> the board, with 20 mils of spacing between them. Our stencil is 6 mils
> thick, laser cut and electro polished. The trapezoidal walled apertures
are
> slightly reduced, 17 mils square, and centered on the pads. It appears the
> chip shooter is placing the parts perfectly. We are using eutectic solder
> paste with an OA flux, and reflowing the parts using the recommended
profile.
>
> Are there any suggestions any of you might have concerning this size of a
> part? Is there a better stencil design, reflow profile, or pad design that
> could help us out? I would appreciate any suggestions.
>
> Thanks.
>
> Ed
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<DIV><SPAN class=3D492354818-10042002><FONT face=3DArial =
color=3D#0000ff=20
size=3D2>Steve,</FONT></SPAN></DIV>
<DIV><SPAN class=3D492354818-10042002><FONT face=3DArial =
color=3D#0000ff size=3D2>I=20
understand what you are saying, but Peter spoke specifically about a =
possible=20
alloy effect and I was trying to get some more info about=20
that.</FONT></SPAN></DIV>
<DIV><SPAN class=3D492354818-10042002><FONT face=3DArial =
color=3D#0000ff=20
size=3D2>Bev</FONT></SPAN></DIV>
<BLOCKQUOTE dir=3Dltr style=3D"MARGIN-RIGHT: 0px">
<DIV class=3DOutlookMessageHeader dir=3Dltr align=3Dleft><FONT =
face=3DTahoma=20
size=3D2>-----Original Message-----<BR><B>From:</B> Creswick, Steven=20
[mailto:[log in to unmask]]<BR><B>Sent:</B> April 10, 2002 12:21=20
PM<BR><B>To:</B> [log in to unmask]<BR><B>Subject:</B> Re: [TN] 0402 =
tombstone=20
problem<BR><BR></FONT></DIV>
<DIV><FONT face=3DArial color=3D#0000ff size=3D2><SPAN=20
class=3D964001516-10042002>Could it be that rather than Sn/Pb =
composition, it=20
might be related to the wettability (prior storage conditions) of=20
the components in question - thereby tying it into the required =
activity=20
level of the flux?</SPAN></FONT></DIV>
<DIV><FONT face=3DArial color=3D#0000ff size=3D2><SPAN=20
class=3D964001516-10042002></SPAN></FONT> </DIV>
<DIV><FONT face=3DArial color=3D#0000ff size=3D2><SPAN=20
class=3D964001516-10042002>Considered rectangular pads with rounded =
corners, or=20
'rectangular' pads with semi-circular ends? It has worked on =
LTCC based=20
product.</SPAN></FONT></DIV>
<DIV><FONT face=3DArial color=3D#0000ff size=3D2><SPAN=20
class=3D964001516-10042002><BR>Steven Creswick - =
Gentex.Corp</SPAN></FONT></DIV>
<BLOCKQUOTE dir=3Dltr style=3D"MARGIN-RIGHT: 0px">
<DIV class=3DOutlookMessageHeader dir=3Dltr align=3Dleft><FONT =
face=3DTahoma=20
size=3D2>-----Original Message-----<BR><B>From:</B> Bev Christian=20
[mailto:[log in to unmask]]<BR><B>Sent:</B> Wednesday, April 10, =
2002 8:46=20
AM<BR><B>To:</B> [log in to unmask]<BR><B>Subject:</B> Re: [TN] 0402 =
tombstone=20
problem<BR><BR></DIV></FONT>
<DIV><SPAN class=3D907554412-10042002><FONT face=3DArial =
color=3D#0000ff=20
size=3D2>Peter,</FONT></SPAN></DIV>
<DIV><SPAN class=3D907554412-10042002><FONT face=3DArial =
color=3D#0000ff size=3D2>So=20
which is worse - high tin (e.g. Sn/Pb95/5) or relatively "high" =
lead=20
(Sn/Pb63/37)?</FONT></SPAN></DIV>
<DIV><SPAN class=3D907554412-10042002><FONT face=3DArial =
color=3D#0000ff=20
size=3D2>Bev Christian</FONT></SPAN></DIV>
<DIV><SPAN class=3D907554412-10042002><FONT face=3DArial =
color=3D#0000ff=20
size=3D2>Research in Motion</FONT></SPAN></DIV>
<BLOCKQUOTE dir=3Dltr style=3D"MARGIN-RIGHT: 0px">
<DIV class=3DOutlookMessageHeader dir=3Dltr align=3Dleft><FONT =
face=3DTahoma=20
size=3D2>-----Original Message-----<BR><B>From:</B> Peter Lee=20
[mailto:[log in to unmask]]<BR><B>Sent:</B> April 10, 2002 12:07=20
AM<BR><B>To:</B> [log in to unmask]<BR><B>Subject:</B> Re: [TN] 0402 =
tombstone problem<BR><BR></FONT></DIV>
<DIV class=3DSection1>
<P class=3DMsoNormal><FONT face=3DArial color=3Dnavy =
size=3D2><SPAN=20
style=3D"FONT-SIZE: 10pt; COLOR: navy; FONT-FAMILY: Arial">Our =
experience=20
with eliminating 0402 <SPAN class=3DSpellE>tombstoning</SPAN> was =
to try=20
different no-clean solder paste. We’ve also found that the =
parts’ end=20
termination tin/lead % has some negative impact on the=20
yield.<o:p></o:p></SPAN></FONT></P>
<P class=3DMsoNormal><FONT face=3DArial color=3Dnavy =
size=3D2><SPAN=20
style=3D"FONT-SIZE: 10pt; COLOR: navy; FONT-FAMILY: =
Arial"><o:p> </o:p></SPAN></FONT></P>
<P class=3DMsoNormal><SPAN class=3DSpellE><FONT face=3DArial =
color=3Dnavy=20
size=3D2><SPAN=20
style=3D"FONT-SIZE: 10pt; COLOR: navy; FONT-FAMILY: =
Arial">Rgds</SPAN></FONT></SPAN><FONT=20
face=3DArial color=3Dnavy size=3D2><SPAN=20
style=3D"FONT-SIZE: 10pt; COLOR: navy; FONT-FAMILY: =
Arial">,<o:p></o:p></SPAN></FONT></P>
<P class=3DMsoNormal><FONT face=3DArial color=3Dnavy =
size=3D2><SPAN=20
style=3D"FONT-SIZE: 10pt; COLOR: navy; FONT-FAMILY: Arial">Peter=20
<o:p></o:p></SPAN></FONT></P>
<P class=3DMsoNormal><FONT face=3DArial color=3Dnavy =
size=3D2><SPAN=20
style=3D"FONT-SIZE: 10pt; COLOR: navy; FONT-FAMILY: =
Arial"><o:p> </o:p></SPAN></FONT></P>
<P class=3DMsoNormal><FONT face=3DArial color=3Dnavy =
size=3D2><SPAN=20
style=3D"FONT-SIZE: 10pt; COLOR: navy; FONT-FAMILY: Arial"><SPAN=20
style=3D"mso-spacerun: yes"> </SPAN><SPAN=20
style=3D"mso-spacerun: =
yes"> </SPAN><o:p></o:p></SPAN></FONT></P>
<P class=3DMsoNormal><FONT face=3DArial color=3Dnavy =
size=3D2><SPAN=20
style=3D"FONT-SIZE: 10pt; COLOR: navy; FONT-FAMILY: =
Arial"><o:p> </o:p></SPAN></FONT></P>
<P class=3DMsoNormal style=3D"MARGIN-LEFT: 0.5in"><FONT =
face=3DTahoma=20
size=3D2><SPAN style=3D"FONT-SIZE: 10pt; FONT-FAMILY: =
Tahoma">-----Original=20
Message-----<BR><B><SPAN style=3D"FONT-WEIGHT: bold">From:</SPAN><=
/B>=20
TechNet [mailto:[log in to unmask]] <B><SPAN style=3D"FONT-WEIGHT: =
bold">On=20
Behalf Of </SPAN></B>[log in to unmask]<BR><B><SPAN=20
style=3D"FONT-WEIGHT: bold">Sent:</SPAN></B> April 9, 2002 8:13=20
PM<BR><B><SPAN style=3D"FONT-WEIGHT: bold">To:</SPAN></B>=20
[log in to unmask]<BR><B><SPAN style=3D"FONT-WEIGHT: =
bold">Subject:</SPAN></B>=20
Re: [TN] 0402 tombstone problem</SPAN></FONT></P>
<P class=3DMsoNormal style=3D"MARGIN-LEFT: 0.5in"><FONT =
face=3D"Times New Roman"=20
size=3D3><SPAN style=3D"FONT-SIZE: =
12pt"><o:p> </o:p></SPAN></FONT></P>
<P class=3DMsoNormal style=3D"MARGIN-LEFT: 0.5in"><FONT =
face=3DArial=20
size=3D2><SPAN style=3D"FONT-SIZE: 10pt; FONT-FAMILY: Arial">I =
just heard=20
something not too long ago, that round pads for 0402's are the =
way to=20
go.<BR><BR>Never heard of that before, but just recently received =
a board=20
for quote that uses round pads for the 0402 components...anybody =
else ever=20
heard of this?<BR><BR>Guess I'll find out how it works inna =
little while,=20
while pondering why a round pad would work better than a square=20
pad....<BR><BR>-Steve Gregory- <BR><BR><BR=20
style=3D"mso-special-character: line-break"><![if =
!supportLineBreakNewLine]><BR=20
style=3D"mso-special-character: =
line-break"><![endif]><o:p></o:p></SPAN></FONT></P>
<P class=3DMsoNormal style=3D"MARGIN-LEFT: 0.5in"><FONT =
face=3DArial=20
size=3D2><SPAN=20
style=3D"FONT-SIZE: 10pt; FONT-FAMILY: Arial">Edward,<BR><BR>When =
we do=20
everything correct on 0402 and 0201 and still have=20
components<BR>standing-up, we often look to the component =
terminations and=20
find poor<BR>plating.<BR><BR>Good luck<BR>Dave Fish<BR><BR>----- =
Original=20
Message -----<BR>From: "Edward S. Wheeler"=20
<[log in to unmask]><BR>To: =
<[log in to unmask]><BR>Sent:=20
Tuesday, April 09, 2002 10:59 AM<BR>Subject: [TN] 0402 tombstone=20
problem<BR><BR><BR>> Hi folks, we are running a new board with =
0402=20
parts on it. It seems that<BR>> we are having a tombstone =
problem as=20
well as a problem with parts not<BR>> staying centered on the =
pads. We=20
are currently using 20 mil square pads on<BR>> the board, with =
20 mils=20
of spacing between them. Our stencil is 6 mils<BR>> thick, =
laser cut=20
and electro polished. The trapezoidal walled =
apertures<BR>are<BR>>=20
slightly reduced, 17 mils square, and centered on the pads. It =
appears=20
the<BR>> chip shooter is placing the parts perfectly. We are =
using=20
eutectic solder<BR>> paste with an OA flux, and reflowing the =
parts=20
using the recommended<BR>profile.<BR>><BR>> Are there any=20
suggestions any of you might have concerning this size of =
a<BR>> part?=20
Is there a better stencil design, reflow profile, or pad design=20
that<BR>> could help us out? I would appreciate any=20
suggestions.<BR>><BR>> Thanks.<BR>><BR>>=20
Ed<o:p></o:p></SPAN></FONT></P>
<P class=3DMsoNormal=20
style=3D"MARGIN-BOTTOM: 12pt; MARGIN-LEFT: 0.5in; MARGIN-RIGHT: =
0in; mso-margin-top-alt: 0in"><FONT=20
face=3D"Times New Roman" size=3D3><SPAN=20
style=3D"FONT-SIZE: =
12pt"><o:p> </o:p></SPAN></FONT></P></DIV></BLOCKQUOTE></BLOCKQUOTE=
></BLOCKQUOTE></BODY></HTML>
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=========================================================================
Date: Wed, 10 Apr 2002 11:51:09 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Dan R. Johnson" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Dan R. Johnson" <[log in to unmask]>
Subject: Re: 0402 tombstone problem
X-To: "Tempea, Ioan" <[log in to unmask]>
MIME-version: 1.0
Content-type: text/plain; charset=iso-8859-1
Content-transfer-encoding: 7BIT
Ioan
Because we have some tight real estate constraints I have used .020 dia. for
0402's .050 dia. for 0805's etc.
Dan
----- Original Message -----
From: "Tempea, Ioan" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Wednesday, April 10, 2002 8:16 AM
Subject: Re: [TN] 0402 tombstone problem
> Hi Dan,
>
> can you give the exact dimensions of the round land pattern?
>
> Thanks,
> Ioan
>
> > -----Original Message-----
> > From: Dan R. Johnson [SMTP:[log in to unmask]]
> > Sent: Wednesday, April 10, 2002 10:22 AM
> > To: [log in to unmask]
> > Subject: Re: [TN] 0402 tombstone problem
> >
> > Steve,
> > I use round pads to decrease pad size (increase circuit density). A side
> > benefit seems to be less chance of skew, I don't have numbers on
> > tombstoning/drawbridging, but product hasn't yelled. I have also been
> > tinkering with the idea of other geometries just haven't come across the
> > right application yet.
> > Dan
> >
> > ----- Original Message -----
> > From: [log in to unmask] <mailto:[log in to unmask]>
> > To: [log in to unmask] <mailto:[log in to unmask]>
> > Sent: Tuesday, April 09, 2002 8:12 PM
> > Subject: Re: [TN] 0402 tombstone problem
> >
> > I just heard something not too long ago, that round pads for
0402's
> > are the way to go.
> >
> > Never heard of that before, but just recently received a board for
> > quote that uses round pads for the 0402 components...anybody else ever
> > heard of this?
> >
> > Guess I'll find out how it works inna little while, while
pondering
> > why a round pad would work better than a square pad....
> >
> > -Steve Gregory-
> >
> >
> >
> >
> > Edward,
> >
> > When we do everything correct on 0402 and 0201 and still
> > have components
> > standing-up, we often look to the component terminations
and
> > find poor
> > plating.
> >
> > Good luck
> > Dave Fish
> >
> > ----- Original Message -----
> > From: "Edward S. Wheeler" <[log in to unmask]>
> > To: <[log in to unmask]>
> > Sent: Tuesday, April 09, 2002 10:59 AM
> > Subject: [TN] 0402 tombstone problem
> >
> >
> > > Hi folks, we are running a new board with 0402 parts on
> > it. It seems that
> > > we are having a tombstone problem as well as a problem
> > with parts not
> > > staying centered on the pads. We are currently using 20
> > mil square pads on
> > > the board, with 20 mils of spacing between them. Our
> > stencil is 6 mils
> > > thick, laser cut and electro polished. The trapezoidal
> > walled apertures
> > are
> > > slightly reduced, 17 mils square, and centered on the
> > pads. It appears the
> > > chip shooter is placing the parts perfectly. We are
using
> > eutectic solder
> > > paste with an OA flux, and reflowing the parts using the
> > recommended
> > profile.
> > >
> > > Are there any suggestions any of you might have
concerning
> > this size of a
> > > part? Is there a better stencil design, reflow profile,
or
> > pad design that
> > > could help us out? I would appreciate any suggestions.
> > >
> > > Thanks.
> > >
> > > Ed
> >
> >
> >
> >
>
> --------------------------------------------------------------------------
-------
> Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
> To unsubscribe, send a message to [log in to unmask] with following text in
> the BODY (NOT the subject field): SIGNOFF Technet
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> Please visit IPC web site http://www.ipc.org/html/forum.htm for additional
> information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700
ext.5315
> --------------------------------------------------------------------------
-------
---------------------------------------------------------------------------------
Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
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---------------------------------------------------------------------------------
=========================================================================
Date: Wed, 10 Apr 2002 19:59:15 +0100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Hinners Hans M Civ WRALC/LUGE <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Hinners Hans M Civ WRALC/LUGE <[log in to unmask]>
Subject: Re: ESS Beginner looking for recommendations
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Hi TechNetters,
Thanks to both Davids, Paul, Barrie and Peter for the info.
Apologies for the delay - I was out getting married this weekend.
And if folks need a diversion I can ask Steve to post a couple of wedding
pics.
Hans
I'm a married spud!
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Hans M. Hinners
Electronics Engineer
Warner Robins - Air Logistics Center (WR-ALC/LUGE)
226 Cochran Street
Robins AFB GA 31098-1622
mailto:[log in to unmask]
Com: (478) 926 - 5224
Fax: (478) 926 - 4911
DSN Prefix: 468
-----Original Message-----
From: [log in to unmask] [mailto:[log in to unmask]]
Sent: Monday, April 08, 2002 1:00 AM
To: [log in to unmask]
Subject: Re: [TN] ESS Beginner looking for recommendations
MIL-STD-810 will give you a lot of test methods and requirements
Peter
Hinners Hans M Civ
WRALC/LUGE To: [log in to unmask]
<Hans.Hinners@ROBI cc: (bcc: DUNCAN
Peter/Asst Prin Engr/ST
NS.AF.MIL> Aero/ST Group)
Sent by: TechNet Subject: [TN] ESS Beginner
looking for
<[log in to unmask]> recommendations
04/04/02 04:32 AM
Please respond to
"TechNet E-Mail
Forum."; Please
respond to Hinners
Hans M Civ
WRALC/LUGE
Hi All,
I'm looking for recommendations on books/articles/websites (knowledge) on
ESS and Reliability testing for high reliability (military) electronics.
I've yanked up MIL-STD-883 as a start. I'm more interested in temp.,
humidity & vibration than salt fog. I need to come up with something quick
but valid - I'll refine it when I have time.
Hans
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Hans M. Hinners
Electronics Engineer
Warner Robins - Air Logistics Center (WR-ALC/LUGE)
226 Cochran Street
Robins AFB GA 31098-1622
mailto:[log in to unmask]
Com: (478) 926 - 5224
Fax: (478) 926 - 4911
DSN Prefix: 468
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Date: Wed, 10 Apr 2002 15:11:13 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: core fill
Content-Type: text/plain; charset=iso-8859-1
Content-Transfer-Encoding: 8bit
Tony,
I don't know if Howfill is even available any more. WE have used Fiberite to fill 0.060 thick copper core w/o any problems. 0.040 thick copper core regularly.
Arlon has a prepreg that replaces Howfill, but I am not sure it will work for 0.060 thick core.
Rush
Accurate Engg Inc
www.accueng.com
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Date: Wed, 10 Apr 2002 15:36:10 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Randy Bock Sr." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Randy Bock Sr." <[log in to unmask]>
Subject: Re: ESS Beginner looking for recommendations
X-To: Hinners Hans M Civ WRALC/LUGE <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
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Congrats... Spud
----- Original Message -----
From: Hinners Hans M Civ WRALC/LUGE <[log in to unmask]>
To: <[log in to unmask]>
Sent: Wednesday, April 10, 2002 2:59 PM
Subject: Re: [TN] ESS Beginner looking for recommendations
> Hi TechNetters,
>
> Thanks to both Davids, Paul, Barrie and Peter for the info.
>
> Apologies for the delay - I was out getting married this weekend.
> And if folks need a diversion I can ask Steve to post a couple of wedding
> pics.
>
> Hans
>
> I'm a married spud!
> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> Hans M. Hinners
> Electronics Engineer
> Warner Robins - Air Logistics Center (WR-ALC/LUGE)
>
> 226 Cochran Street
> Robins AFB GA 31098-1622
>
> mailto:[log in to unmask]
>
> Com: (478) 926 - 5224
> Fax: (478) 926 - 4911
> DSN Prefix: 468
>
>
> -----Original Message-----
> From: [log in to unmask] [mailto:[log in to unmask]]
> Sent: Monday, April 08, 2002 1:00 AM
> To: [log in to unmask]
> Subject: Re: [TN] ESS Beginner looking for recommendations
>
>
> MIL-STD-810 will give you a lot of test methods and requirements
>
> Peter
>
>
>
> Hinners Hans M Civ
> WRALC/LUGE To: [log in to unmask]
> <Hans.Hinners@ROBI cc: (bcc: DUNCAN
> Peter/Asst Prin Engr/ST
> NS.AF.MIL> Aero/ST Group)
> Sent by: TechNet Subject: [TN] ESS
Beginner
> looking for
> <[log in to unmask]> recommendations
>
>
> 04/04/02 04:32 AM
> Please respond to
> "TechNet E-Mail
> Forum."; Please
> respond to Hinners
> Hans M Civ
> WRALC/LUGE
>
>
>
>
>
>
> Hi All,
>
> I'm looking for recommendations on books/articles/websites (knowledge) on
> ESS and Reliability testing for high reliability (military) electronics.
> I've yanked up MIL-STD-883 as a start. I'm more interested in temp.,
> humidity & vibration than salt fog. I need to come up with something
quick
> but valid - I'll refine it when I have time.
>
> Hans
>
> ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> Hans M. Hinners
> Electronics Engineer
> Warner Robins - Air Logistics Center (WR-ALC/LUGE)
> 226 Cochran Street
> Robins AFB GA 31098-1622
>
> mailto:[log in to unmask]
>
> Com: (478) 926 - 5224
> Fax: (478) 926 - 4911
> DSN Prefix: 468
>
> --------------------------------------------------------------------------
--
> -----
>
> Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
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> the BODY (NOT the subject field): SIGNOFF Technet
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the
> intended recipient, please delete it and notify us immediately; you should
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Date: Wed, 10 Apr 2002 15:37:20 EDT
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Werner Engelmaier <[log in to unmask]>
Subject: Re: test method to detect solder joint weakness
MIME-Version: 1.0
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
Hi David,
I am with you--these are NOT new test methods, just new names. What is the
difference between good ald ESS and HASS?
Werner Engelmaier
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Date: Wed, 10 Apr 2002 15:52:16 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
James TerVeen <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: James TerVeen <[log in to unmask]>
Subject: Re: ESS Beginner looking for recommendations
X-To: Hinners Hans M Civ WRALC/LUGE <[log in to unmask]>
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
Congratulations!!!!!!!
But you should have asked us first??? I am certain this would have stired
up a great deal of responses.
I hope you have many little potato's ( How do you spell that anyway)
Hinners Hans M Civ
WRALC/LUGE To: [log in to unmask]
<Hans.Hinners@ROBI cc:
NS.AF.MIL> Subject: Re: [TN] ESS Beginner looking for
Sent by: TechNet recommendations
<[log in to unmask]>
04/10/02 02:59 PM
Please respond to
"TechNet E-Mail
Forum."; Please
respond to Hinners
Hans M Civ
WRALC/LUGE
Hi TechNetters,
Thanks to both Davids, Paul, Barrie and Peter for the info.
Apologies for the delay - I was out getting married this weekend.
And if folks need a diversion I can ask Steve to post a couple of wedding
pics.
Hans
I'm a married spud!
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Hans M. Hinners
Electronics Engineer
Warner Robins - Air Logistics Center (WR-ALC/LUGE)
226 Cochran Street
Robins AFB GA 31098-1622
mailto:[log in to unmask]
Com: (478) 926 - 5224
Fax: (478) 926 - 4911
DSN Prefix: 468
-----Original Message-----
From: [log in to unmask] [mailto:[log in to unmask]]
Sent: Monday, April 08, 2002 1:00 AM
To: [log in to unmask]
Subject: Re: [TN] ESS Beginner looking for recommendations
MIL-STD-810 will give you a lot of test methods and requirements
Peter
Hinners Hans M Civ
WRALC/LUGE To: [log in to unmask]
<Hans.Hinners@ROBI cc: (bcc: DUNCAN
Peter/Asst Prin Engr/ST
NS.AF.MIL> Aero/ST Group)
Sent by: TechNet Subject: [TN] ESS
Beginner
looking for
<[log in to unmask]> recommendations
04/04/02 04:32 AM
Please respond to
"TechNet E-Mail
Forum."; Please
respond to Hinners
Hans M Civ
WRALC/LUGE
Hi All,
I'm looking for recommendations on books/articles/websites (knowledge) on
ESS and Reliability testing for high reliability (military) electronics.
I've yanked up MIL-STD-883 as a start. I'm more interested in temp.,
humidity & vibration than salt fog. I need to come up with something quick
but valid - I'll refine it when I have time.
Hans
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Hans M. Hinners
Electronics Engineer
Warner Robins - Air Logistics Center (WR-ALC/LUGE)
226 Cochran Street
Robins AFB GA 31098-1622
mailto:[log in to unmask]
Com: (478) 926 - 5224
Fax: (478) 926 - 4911
DSN Prefix: 468
----------------------------------------------------------------------------
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Date: Wed, 10 Apr 2002 15:52:18 EDT
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Werner Engelmaier <[log in to unmask]>
Subject: Re: test method to detect solder joint weakness
MIME-Version: 1.0
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
Hi David,
I am with you--these are NOT new test methods, just new names. What is the
difference between good old ESS and HASS?
Werner Engelmaier
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Date: Wed, 10 Apr 2002 14:52:31 -0500
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: "Robert B. Denbo" <[log in to unmask]>
Subject: Re: core fill
X-To: tony steinke <[log in to unmask]>
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="----=_NextPart_000_0022_01C1E09F.68F67A10"
This is a multi-part message in MIME format.
------=_NextPart_000_0022_01C1E09F.68F67A10
Content-Type: text/plain;
charset="iso-8859-1"
Content-Transfer-Encoding: 7bit
Tony:
We have used Fiberite, without issue, on Copper and Aluminum cores up to
0.180" thick.
Robert B. Denbo
Engineering Manager
Midwest Printed Circuit Services, Inc.
http://www.midwestpcb.com
mailto:[log in to unmask]
847.740.4120
847.740.4187 Fax
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of tony steinke
Sent: Wednesday, April 10, 2002 4:07 PM
To: [log in to unmask]
Subject: [TN] core fill
Hello Techies,
Can anyone tell me what type of reliable core fill materials are on the
market.
I have been looking at the Howefilm and Fiberite, but both have some
limitations. We have a .050 solid copper core to fill. And the Tg or
operating temperature must be 170C or greater.
Thanks in advance
Tony Steinke
------=_NextPart_000_0022_01C1E09F.68F67A10
Content-Type: text/html;
charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META HTTP-EQUIV=3D"Content-Type" CONTENT=3D"text/html; =
charset=3Diso-8859-1">
<META content=3D"MSHTML 6.00.2715.400" name=3DGENERATOR>
<STYLE></STYLE>
</HEAD>
<BODY bgColor=3D#fff8e0>
<DIV><SPAN class=3D418284819-10042002><FONT =
face=3DArial>Tony:</FONT></SPAN></DIV>
<DIV><SPAN class=3D418284819-10042002><FONT =
face=3DArial></FONT></SPAN> </DIV>
<DIV><SPAN class=3D418284819-10042002><FONT face=3DArial>We have used =
Fiberite,=20
without issue, on Copper and Aluminum cores up to 0.180"=20
thick.</FONT></SPAN></DIV>
<DIV><SPAN class=3D418284819-10042002><FONT face=3DArial=20
color=3D#ff0000></FONT><BR><FONT size=3D2>Robert B. Denbo<BR>Engineering =
Manager<BR>Midwest Printed Circuit Services, Inc.<BR><A=20
href=3D"http://www.midwestpcb.com/"=20
target=3D_blank>http://www.midwestpcb.com</A><BR><A=20
href=3D"mailto:[log in to unmask]">mailto:[log in to unmask]</A><BR=
>847.740.4120<BR>847.740.4187=20
Fax </FONT></DIV></SPAN>
<BLOCKQUOTE dir=3Dltr style=3D"MARGIN-RIGHT: 0px">
<DIV class=3DOutlookMessageHeader dir=3Dltr align=3Dleft><FONT =
face=3DTahoma=20
size=3D2>-----Original Message-----<BR><B>From:</B> TechNet=20
[mailto:[log in to unmask]]<B>On Behalf Of </B>tony =
steinke<BR><B>Sent:</B>=20
Wednesday, April 10, 2002 4:07 PM<BR><B>To:</B>=20
[log in to unmask]<BR><B>Subject:</B> [TN] core fill<BR><BR></FONT></DIV>
<DIV><FONT face=3DArial size=3D2>Hello Techies,</FONT></DIV>
<DIV><FONT face=3DArial size=3D2>Can anyone tell me what type of=20
reliable core fill materials are on the market.</FONT></DIV>
<DIV><FONT face=3DArial size=3D2>I have been looking at the Howefilm =
and Fiberite,=20
but both have some limitations. We have a .050 solid=20
copper core to fill. A</FONT><FONT face=3DArial size=3D2>nd the =
Tg or=20
operating temperature must be 170C or greater.</FONT> </DIV>
<DIV><FONT face=3DArial size=3D2>Thanks in advance</FONT></DIV>
<DIV><FONT face=3DArial size=3D2>Tony=20
Steinke</FONT></DIV></BLOCKQUOTE></BODY></HTML>
------=_NextPart_000_0022_01C1E09F.68F67A10--
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=========================================================================
Date: Wed, 10 Apr 2002 16:02:58 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Randy Bock Sr." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Randy Bock Sr." <[log in to unmask]>
Subject: Re: Component Lead Touch-up
X-To: "McMullen, Kerry" <[log in to unmask]>
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That is about 2.5%, not really a large qty given the number of total =
leads. Your on track by ordering
IPC 7711 Rework Std. IPC 7712 is Rework and Modification of PWB and =
Electronic Assemblies.
=20
----- Original Message -----=20
From: McMullen, Kerry=20
To: [log in to unmask]
Sent: Wednesday, April 10, 2002 2:36 PM
Subject: [TN] Component Lead Touch-up
Hi,
We have a board with about 12,000 leads. The board is inspected to =
Class II standards. We noticed about 300 leads were touched up.
=20
I have not seen anything in IPC for % of leads that can be touched up =
on a printed circuit board before the board is considered unacceptable. =
I don't know if this data is in IPC 7711 or 7721. I have ordered the =
manuals though.
=20
Is there a standard I should be looking for, or is there a % that =
people use?
=20
Thanks,
Kerry
=20
=20
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charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META content=3D"text/html; charset=3Diso-8859-1" =
http-equiv=3DContent-Type>
<META content=3D"MSHTML 5.00.2614.3500" name=3DGENERATOR>
<STYLE></STYLE>
</HEAD>
<BODY bgColor=3D#fff8e0>
<DIV><FONT size=3D2>That is about 2.5%, not really a large qty given the =
number of=20
total leads. Your on track by ordering</FONT></DIV>
<DIV><FONT size=3D2>IPC 7711 Rework Std. IPC 7712 is Rework and =
Modification=20
of PWB and Electronic Assemblies.</FONT></DIV>
<DIV> </DIV>
<DIV><FONT size=3D2> </FONT></DIV>
<DIV> </DIV>
<DIV> </DIV>
<BLOCKQUOTE=20
style=3D"BORDER-LEFT: #000000 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: =
0px; PADDING-LEFT: 5px; PADDING-RIGHT: 0px">
<DIV style=3D"FONT: 10pt arial">----- Original Message ----- </DIV>
<DIV=20
style=3D"BACKGROUND: #e4e4e4; FONT: 10pt arial; font-color: =
black"><B>From:</B>=20
<A href=3D"mailto:[log in to unmask]"=20
[log in to unmask]>McMullen, Kerry</A> </DIV>
<DIV style=3D"FONT: 10pt arial"><B>To:</B> <A =
href=3D"mailto:[log in to unmask]"=20
[log in to unmask]>[log in to unmask]</A> </DIV>
<DIV style=3D"FONT: 10pt arial"><B>Sent:</B> Wednesday, April 10, 2002 =
2:36=20
PM</DIV>
<DIV style=3D"FONT: 10pt arial"><B>Subject:</B> [TN] Component Lead=20
Touch-up</DIV>
<DIV><BR></DIV>
<DIV><FONT face=3DArial size=3D2><SPAN=20
class=3D085503818-10042002>Hi,</SPAN></FONT></DIV><SPAN=20
class=3D085503818-10042002>
<DIV><FONT face=3DArial size=3D2><SPAN class=3D085503818-10042002>We =
have a board=20
with about 12,000 leads. The board is inspected to Class II =
standards. =20
We noticed about 300 leads were touched up.</SPAN></FONT></DIV>
<DIV><FONT face=3DArial size=3D2><SPAN=20
class=3D085503818-10042002></SPAN></FONT> </DIV>
<DIV><FONT face=3DArial size=3D2>I have not seen anything in IPC for % =
of leads=20
that can be touched up on a printed circuit board before the board is=20
considered unacceptable. I don't know if this data is in IPC =
7711 or=20
7721. I have ordered the manuals though.</FONT></DIV>
<DIV><FONT face=3DArial size=3D2></FONT> </DIV>
<DIV></SPAN><SPAN class=3D085503818-10042002><FONT color=3D#0000ff =
face=3DArial=20
size=3D2>Is there a standard I should be looking for, or is there a % =
that=20
people use?</FONT></SPAN></DIV>
<DIV><SPAN class=3D085503818-10042002><FONT color=3D#0000ff =
face=3DArial=20
size=3D2></FONT></SPAN> </DIV>
<DIV><SPAN class=3D085503818-10042002><FONT color=3D#0000ff =
face=3DArial=20
size=3D2>Thanks,</FONT></SPAN></DIV>
<DIV><SPAN class=3D085503818-10042002><FONT color=3D#0000ff =
face=3DArial=20
size=3D2>Kerry</FONT></SPAN></DIV>
<DIV><FONT face=3DArial size=3D2><SPAN=20
class=3D085503818-10042002></SPAN></FONT> </DIV>
<DIV><FONT color=3D#0000ff face=3DArial=20
size=3D2></FONT> </DIV></BLOCKQUOTE></BODY></HTML>
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Date: Wed, 10 Apr 2002 14:53:42 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Jeffrey Ciesla <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Jeffrey Ciesla <[log in to unmask]>
Subject: Re: MIL Standard
You can find some of the specifications online at
http://www.dscc.dla.mil/Programs/MilSpec/DocSearch.asp
Jeff
On Wed, 3 Apr 2002 09:33:41 -0600, Bill Christoffel
<[log in to unmask]> wrote:
>Try this, It's the best I found.
>http://astimage.daps.dla.mil/quicksearch/
>
>Bill C.
>Advanced Manufacturing Eng.
>NorLux Corp.
>
>-----Original Message-----
>From: Wright, Michael D. [mailto:[log in to unmask]]
>Sent: Wednesday, April 03, 2002 8:49 AM
>To: [log in to unmask]
>Subject: Re: [TN] MIL Standard
>
>
>Is there a web link where the Mil Specs can be downloaded?
>
>Michael Wright
>Sr. Engineer
>ITT Cannon
>952-974-5813
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Date: Wed, 10 Apr 2002 16:12:27 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Phil Nutting <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Phil Nutting <[log in to unmask]>
Subject: connecting aluminum to copper
MIME-Version: 1.0
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Good afternoon TechNet,
Would anyone like to share their knowledge about using an aluminum =
standoff as a conductor when connecting two circuit boards together. I =
suspect that if it were aluminum to copper there would be an issue, but =
what about aluminum to HASL surface of circuit boards?
Thanks in advance for your wisdom,
Phil Nutting
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Date: Wed, 10 Apr 2002 15:55:52 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Kevin Stokes <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Kevin Stokes <[log in to unmask]>
Subject: Benchmarking Quality in Electronics Contract Manufacturing
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Does anyone have an idea where I can find some benchmark information on
quality support within electronics contract manufacturing facilities?
Something like:
# of quality personnel/total sales
cost of quality/total sales
Please help,
Kevin
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<TITLE>Benchmarking Quality in Electronics Contract =
Manufacturing</TITLE>
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<BODY>
<P><FONT SIZE=3D2>Does anyone have an idea where I can find some =
benchmark information on quality support within electronics contract =
manufacturing facilities?</FONT></P>
<P><FONT SIZE=3D2>Something like:</FONT>
<BR> <FONT SIZE=3D2># of =
quality personnel/total sales</FONT>
<BR> <FONT SIZE=3D2>cost of =
quality/total sales</FONT>
</P>
<P><FONT SIZE=3D2>Please help,</FONT>
</P>
<P><FONT SIZE=3D2>Kevin</FONT>
</P>
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Date: Wed, 10 Apr 2002 17:08:52 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
[log in to unmask]
Sender: TechNet <[log in to unmask]>
From: "Mark E. Schumacher" <[log in to unmask]>
Subject: Re: connecting aluminum to copper
X-To: Phil Nutting <[log in to unmask]>
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
Phil,
Alluminum to tin lead surface does not work well with aging effects. We
Nickel Plate (electrically deposited) all terminals which are in contact
with to tin-lead surface. In addition, we add a contact lubricant , Nyogel
760G to the contact surfaces to seal out oxygen. We have a good track
record with this combination.
Interfaces to stay away from, these were huge failures.
Alluminum to Tin Lead
Alluminum to Nickel
Mark
Phil Nutting
<PNutting@KAISERSY To: [log in to unmask]
STEMS.COM> cc:
Sent by: TechNet Subject: [TN] connecting aluminum to copper
<[log in to unmask]>
04/10/02 04:12 PM
Please respond to
"TechNet E-Mail
Forum."; Please
respond to Phil
Nutting
Good afternoon TechNet,
Would anyone like to share their knowledge about using an aluminum standoff
as a conductor when connecting two circuit boards together. I suspect that
if it were aluminum to copper there would be an issue, but what about
aluminum to HASL surface of circuit boards?
Thanks in advance for your wisdom,
Phil Nutting
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Date: Wed, 10 Apr 2002 15:53:34 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Howard Watson <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Howard Watson <[log in to unmask]>
Subject: Through hole components in Reflow
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I have an SMT board that has 1 through hole 16 pin DIP (TI #L293DNE), and
I have had great success using the Pin in Hole Reflow method to solder the
part alongside with the SMD's. Everything is fine, but I can't prove to
my customer that the part is not suffering damage inside the case. The
Datasheet lists a lead temperature range of 260 Deg.C for 10 seconds, which is fine for wave
solder, but it doesn't apply to a reflow temperature profile. I contacted
technical support at TI and they stated:
"Although we don't have any data regarding pin-in-paste reflow processing,
we are aware that some customers are using our through-hole packages in a
backside wave soldering process without any issues. Unfortunately, we do
not have a standard specification or requirements document for the reflow
processing of our through-hole packages."
The consensus here is that there should not be a problem, however, my
customer does not like words like "should" or "not likely". He needs data
for any process change request, rightly so. My question to the experts
out there on plastic encapsulated dies: is there any difference between
the Surface Mount and Through hole package for thermal related damage?
Will I be OK as long as I am following our reflow guidelines for peak
temp, time above liquidus, and max rising slope? Thanks for all of your
great help and suggestions.
Howard Watson
Manufacturing Engineer
AMETEK/Dixson
--=_alternative 007801AB87256B97_=
Content-Type: text/html; charset="us-ascii"
<br><font size=2 face="sans-serif">I have an SMT board that has 1 through hole 16 pin DIP (TI #L293DNE), and I have had great success using the Pin in Hole Reflow method to solder the part alongside with the SMD's. Everything is fine, but I can't prove to my customer that the part is not suffering damage inside the case. The Datasheet lists a <u>lead</u> temperature range of 260 Deg.C for 10 seconds, which is fine for wave solder, but it doesn't apply to a reflow temperature profile. I contacted technical support at TI and they stated:</font>
<br><font size=2 face="Courier New">"Although we don't have any data regarding pin-in-paste reflow processing, we are aware that some customers are using our through-hole packages in a backside wave soldering process without any issues. Unfortunately, we do not have a standard specification or requirements document for the reflow processing of our through-hole packages."</font>
<br>
<br><font size=2 face="sans-serif">The consensus here is that there should not be a problem, however, my customer does not like words like "should" or "not likely". He needs data for any process change request, rightly so. My question to the experts out there on plastic encapsulated dies: is there any difference between the Surface Mount and Through hole package for thermal related damage? Will I be OK as long as I am following our reflow guidelines for peak temp, time above liquidus, and max rising slope? Thanks for all of your great help and suggestions.</font>
<br>
<br><font size=2 face="sans-serif">Howard Watson<br>
Manufacturing Engineer<br>
AMETEK/Dixson</font>
--=_alternative 007801AB87256B97_=--
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Date: Wed, 10 Apr 2002 17:06:35 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
David Douthit <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: David Douthit <[log in to unmask]>
Subject: Re: test method to detect solder joint weakness
X-To: [log in to unmask]
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Werner,
What I have been told is that ESS is used on 100% of the products while HASS is a form of "sample"
testing.
As far as I can tell the amount of product tested is the only difference.
David A. Douthit
Manager
LoCan LLC
Werner Engelmaier wrote:
> Hi David,
> I am with you--these are NOT new test methods, just new names. What is the
> difference between good old ESS and HASS?
>
> Werner Engelmaier
>
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Date: Wed, 10 Apr 2002 18:14:31 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Jindra, Larry" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Jindra, Larry" <[log in to unmask]>
Subject: Re: Solder Ball Wrinkles
X-To: [log in to unmask]
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Dave-
Thanks for your interest. My "wrinkles" are irregular. The "wrinkles" do not appear to be mechanically made. However, the balls were probed by the BGA supplier (different company than the BGA packager) during test at temperature (95C). These probe (prong) marks are evident on the sides of the balls, at the 4 quadrants. I don't believe they are causing any trouble.
I am sending samples of the wrinkled balls to Mr. Ramsey, to see what he thinks of the metallurgy.
Larry Jindra
Mfg Engr Group Lead
TRW Radio Systems
[log in to unmask]
w) 858-592-3424
f) 858-592-3940
-----Original Message-----
From: [log in to unmask] [mailto:[log in to unmask]]
Sent: Monday, April 01, 2002 9:07 AM
To: [log in to unmask]; Jindra, Larry
Subject: Re: [TN] Solder Ball Wrinkles
Hi Larry. Is it possible that the "wrinkles" are not a reflection of
solderball metallurgical microstructure but witness marks from test probing
of the BGA by the component fabricator?
Dave Hillman
Rockwell Collins
[log in to unmask]
"Jindra, Larry" <[log in to unmask]>@ipc.org> on 03/29/2002 04:19:24 PM
Please respond to "TechNet E-Mail Forum." <[log in to unmask]>; Please respond
to "Jindra, Larry" <[log in to unmask]>
Sent by: TechNet <[log in to unmask]>
To: [log in to unmask]
cc:
Subject: Re: [TN] Solder Ball Wrinkles
True, I was talking about appearance of the BGAs prior to mounting.
We just did a blind installation test with the same packages from an
earlier lot that did not exhibit "wrinkles." The result show a
significantly greater voiding joints from the "wrinkled" BGAs, given the
same paste, place and reflow processing parameters. Given that the same
things that cause voiding can cause shorting, we have a process problem
that appears to be caused by a supplier process.
The packaging vendor claims the bad balls saw a normal process. I need to
tell them we suspect they are .....
Larry Jindra
Mfg Engr Group Lead
TRW Radio Systems
[log in to unmask]
w) 858-592-3424
f) 858-592-3940
-----Original Message-----
From: Guy Ramsey [mailto:[log in to unmask]]
Sent: Friday, March 29, 2002 1:13 PM
To: TechNet E-Mail Forum.; Jindra, Larry
Subject: RE: [TN] Solder Ball Wrinkles
As I read your message, we are not talking about BGAs that were mounted on
boards. These are the packages before they were installed? It this true?
Yes, I would be worried. Sound like something was wrong in the solder ball
attach process. I am not very familiar with commercial methods. Reballing
processes that produce wrinkled balls can be caused by excessive heat and
excessive convection.
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Jindra, Larry
> Sent: Friday, March 29, 2002 12:59 PM
> To: [log in to unmask]
> Subject: [TN] Solder Ball Wrinkles
>
>
> We have a lot of BGA packages from a custom package house with a
> "wrinkled" appearance to the ball surface, most pronounced on top
> of the ball, where they will interface with the PCB. These
> packages are prone to shorting.
>
> Does anyone out there have an idea of what might cause that
> "wrinkled" appearance, and why it might make the package
> succeptible to shorting?
>
>
> Larry Jindra
> Mfg Engr Group Lead
> TRW Radio Systems
> [log in to unmask]
> w) 858-592-3424
> f) 858-592-3940
>
> ------------------------------------------------------------------
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Date: Wed, 10 Apr 2002 21:24:35 EDT
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Rudy Sedlak <[log in to unmask]>
Subject: Nickel Test
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I recall seeing a spot test for Nickel that involved using a solution of
Dimethylglyoxime in dilute Ammonia, + ???? as a spot test for gold porosity
to show presence of Nickel.
Does anyone have the exact details of this test? Does anyone know if it
works on Electroless Nickel? (Suspect it may not because EN is so much more
passive.)
Rudy Sedlak
RD Chemical Company
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Date: Thu, 11 Apr 2002 10:42:42 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
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From: [log in to unmask]
Subject: Re: Pot washers!
X-To: [log in to unmask]
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Iain,
I tried asking about these a little while ago and came up with nothing. I
would really appreciate it if you could tell me if you find a source.
The reason why I came up with nothing is that the dishwasher style cleaners
fell into serious disrepute for various reasons, one of them being that if
used with DI water, the seals (usually containing silicon) disintegrated,
making a mess of the floor, but also putting more contamination onto the
board than it took off. Standard seals had to be replaced with neoprene or
something that wasn't attacked by the DI water. Also, they weren't able to
properly clean boards like a modern batch cleaner or in-line system.
For my purposes, I would still like to get hold of a dishwasher type
cleaner, though. Small batch cleaners are still very expensive, and me
cleaning requirements are very light - removal of any handling
contamination, atmospheric contamination, residues from stripping acrylic
coating from boards, and flux residues after local repairs. All this to
re-clean boards prior to conformal coating.
Good luck with your search - I hope you have more success than I did.
Peter
iain.braddock@
MBDA.CO.UK To: [log in to unmask]
Sent by: cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
TechNet Aero/ST Group)
<[log in to unmask] Subject: [TN] Pot washers!
RG>
04/10/02 02:36
PM
Please respond
to "TechNet
E-Mail
Forum.";
Please respond
to
iain.braddock
Hey dudes,
Anybody out there provide a name / contact details for UK based firms
that supply semi-aqeous dishwasher style cleaners similar to household
ones but have the resistivity meter on that samples the rinse cycle
water at the drain. Could really do with locating a
manufacturer/supplier pretty sharpish.
CIA,
Iain.
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Date: Thu, 11 Apr 2002 09:20:16 +0300
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Brian Ellis <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Brian Ellis <[log in to unmask]>
Subject: Re: connecting aluminum to copper
X-To: Phil Nutting <[log in to unmask]>
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Phil
I don't recommend any Al (or alloys) to Cu or Sn/Pb junction, where they
are in electrical contact. The electrochemical potential is sufficiently
great that corrosion is inevitable if they got damp, with all sorts of
nasties potentially migrating over the board surface. Al would be OK if
there were no electrical contact.
Brian
Phil Nutting wrote:
>
> Good afternoon TechNet,
>
> Would anyone like to share their knowledge about using an aluminum standoff as a conductor when connecting two circuit boards together. I suspect that if it were aluminum to copper there would be an issue, but what about aluminum to HASL surface of circuit boards?
>
> Thanks in advance for your wisdom,
>
> Phil Nutting
>
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Date: Thu, 11 Apr 2002 15:59:34 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Voids on BGA
X-To: Antonio Souza <[log in to unmask]>
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Hi, Antonio,
As the other two respondants have indicated, voids in BGA joints are
principally caused by volatile compounds in the flux out-gassing into the
joint. Voids in these cases tend to be small and of no significance as long
as they don't blow out through the side of the ball, which is rare. Larger,
more irregularly-shaped voids can occur when you have via holes in the
pads, unfilled holes especially, although these holes are normally plugged
nowadays.
Voids in BGA joints are common and are not considered to be a problem
unless they are very large and/or found at the top of the ball next to the
compnoent substrate. These weaken the balls' adherence to the component.
Careful selection of flux and tight soldering process control can eliminate
voiding, but the cost of this will be high with no real advantage gained
unless your voids are a problem.
Best wishes
Peter
Antonio Souza
<[log in to unmask] To: [log in to unmask]
INPE.BR> cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
Sent by: Aero/ST Group)
TechNet Subject: [TN] Voids on BGA
<[log in to unmask]
ORG>
04/10/02
08:25 PM
Please
respond to
"TechNet
E-Mail
Forum.";
Please
respond to
Antonio Souza
Does anybody know the main causes for Voids on BGA solder joints?
Thanks
Antonio
Brazil
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Date: Thu, 11 Apr 2002 16:08:14 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: 0402 tombstone problem
X-To: "D.Terstegge" <[log in to unmask]>
MIME-Version: 1.0
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Thanks, Daan. I just downloaded the file before you get sued and forced to
removed it again from your site.
Peter
"D.Terstegge"
<[log in to unmask] To: [log in to unmask]
TMFWEB.NL> cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
Sent by: Aero/ST Group)
TechNet Subject: Re: [TN] 0402 tombstone problem
<[log in to unmask]
ORG>
04/11/02
01:30 AM
Please
respond to
"TechNet
E-Mail
Forum.";
Please
respond to
"D.Terstegge"
Hi Ed,
A good article called "TOMBSTONING OF 0402 AND 0201 COMPONENTS: A STUDY
EXAMINING THE EFFECTS OF VARIOUS PROCESS AND DESIGN PARAMETERS ON
ULTRA-SMALL PASSIVE DEVICES" used to be on the Plexus website.
Seems it disappeared when Plexus changed their website, but I uploaded the
document to my own webspace, where you can still download it at
http://www.smtinfo.net/docs/tombstoning.pdf.
What do you think, am I violating copyrights this way ? (comments welcome,
off-Technet would be best I guess)
Anyway, hope it gives you some clues...
Daan Terstegge
http://www.smtinfo.net
----- Original Message -----
From: Edward S. Wheeler
To: [log in to unmask]
Sent: Tuesday, April 09, 2002 7:59 PM
Subject: [TN] 0402 tombstone problem
Hi folks, we are running a new board with 0402 parts on it. It seems that
we are having a tombstone problem as well as a problem with parts not
staying centered on the pads. We are currently using 20 mil square pads on
the board, with 20 mils of spacing between them. Our stencil is 6 mils
thick, laser cut and electro polished. The trapezoidal walled apertures
are
slightly reduced, 17 mils square, and centered on the pads. It appears the
chip shooter is placing the parts perfectly. We are using eutectic solder
paste with an OA flux, and reflowing the parts using the recommended
profile.
Are there any suggestions any of you might have concerning this size of a
part? Is there a better stencil design, reflow profile, or pad design that
could help us out? I would appreciate any suggestions.
Thanks.
Ed
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Date: Thu, 11 Apr 2002 16:13:02 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: ESS Beginner looking for recommendations
X-To: Hinners Hans M Civ WRALC/LUGE <[log in to unmask]>
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Many congrats, Hans, but that was rather a short honeymoon period wasn't
it, if you're back in harness already?
Peter
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Date: Thu, 11 Apr 2002 16:25:19 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: connecting aluminum to copper
X-To: Phil Nutting <[log in to unmask]>
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Phil,
Especially of you're contemplating purely mechanical contact, I strongly
suspect there will be pronounced degradation of conductivity over a period
of time, owing to differential metal corrosion effects. This will be more
so when extra electricity is added. You will have to leave the aluminium
fairly free of protecting chemical treatments in order to make good initial
contact, but as aluminium naturally oxidises over time, and aluminium oxide
is non-conductive, I can bet good money your conductivity will get loused
up sooner rather than later.
I take it that you have a space problem, and don't want to use too much by
fitting connectors instead, huh? I don't have an answer t the problem
without knowing the space you have available. Soldering a stand-off at one
end might help, but the heat required and strong fluxes would be too much
for a poor board to cope with. You may have to electroplate the stand-offs
with gold maintain contact and give adequate protection against corrosion.
My poor thought for the day.
Peter
Phil Nutting
<PNutting@KAISERSY To: [log in to unmask]
STEMS.COM> cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
Sent by: TechNet Aero/ST Group)
<[log in to unmask]> Subject: [TN] connecting aluminum to copper
04/11/02 04:12 AM
Please respond to
"TechNet E-Mail
Forum."; Please
respond to Phil
Nutting
Good afternoon TechNet,
Would anyone like to share their knowledge about using an aluminum standoff
as a conductor when connecting two circuit boards together. I suspect that
if it were aluminum to copper there would be an issue, but what about
aluminum to HASL surface of circuit boards?
Thanks in advance for your wisdom,
Phil Nutting
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Date: Thu, 11 Apr 2002 05:46:40 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Matt Kehoe <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Matt Kehoe <[log in to unmask]>
Subject: SIPAD Shelf Life
Short shelf life is relative. We have documented the shelf life of SIPAD
boards of up to 14 months. We also have many samples that are more than 2
years old, have been stored in less than ideal conditions, (in my breif
case, car trunk etc), and they are still very tacky. Also, if for some
reason they do dry out, they can be cleaned and re-fluxed.
As far as a stacker is concerned, SIPAD boards were used in the Easi line
at the Assembly Technology Expo one year, with a stacker system that was
very clever. The boards were placed into the stacker paper side down. A
suction cup handler picked up the board, placed it on the conveyor where
it was carried over a small air knife that blew off the paper, dropping it
into a box underneath. The board transported into an inverter where it was
flipped, tacky side up now, and sent into the pick and place machine.
We have access to this equipment if you are interested.
mk
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Date: Thu, 11 Apr 2002 05:48:11 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Matt Kehoe <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Matt Kehoe <[log in to unmask]>
Subject: Flux application SIPAD
On Mon, 8 Apr 2002 05:32:36 -0500, Gary Camac <[log in to unmask]> wrote:
>Steve,
>
>I would bet you can't feed these on a destacker. What's is the category
of
>flux being used? It is applied on the entire board surface or just at the
>soldering locations?
>
>Gary
>
>Gary
>----- Original Message -----
>From: <[log in to unmask]>
>To: <[log in to unmask]>
>Sent: Friday, April 05, 2002 6:33 PM
>Subject: [TN] Any SIPAD users?
>
>
>> Hi All!
>>
>> I got a few sample boards that a solid solder deposit was applied
(SIPAD),
>> along with what they call adhesive flux, to play around with. I got some
>> dummy components and placed and reflowed them...I was very pleased with
>the
>> results!
>>
>> Do any of you use this technology? Any thoughts or opinions would be
>> appreciated.
>>
>> Thanks!!
>>
>> -Steve Gregory-
>>
>> ------------------------------------------------------------------------
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>-------
>>
>
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The flux is printed onto the smd pads only using the same stencil as the
paste.
mk
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Date: Thu, 11 Apr 2002 05:59:25 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Matt Kehoe <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Matt Kehoe <[log in to unmask]>
Subject: SIPAD flux choices
Dont forget, any adhesive flux can be used on SIPAD boards. The only hook
is, it must be applied just prior to placement, so that means printing it
yourself. Only the Promosol no-clean is designed to be applied and dried,
papered and shipped.
Printing flux is extremely forgiving and easy to do. No hi tech printer
needed, just a hand screening table will do. Kester makes the TSF line
which comes in no-clean, H2O, and others exist. The paste will already be
there in solid form. Just print the flux and send it into the chip
shooter. The stencil can be shipped with the boards to avoid extra cost.
mk
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Date: Thu, 11 Apr 2002 07:35:05 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Randy Bock Sr." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Randy Bock Sr." <[log in to unmask]>
Subject: Re: Benchmarking Quality in Electronics Contract Manufacturing
X-To: Kevin Stokes <[log in to unmask]>
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="----=_NextPart_000_006F_01C1E12B.665E8B80"
This is a multi-part message in MIME format.
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charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
Benchmarking Quality in Electronics Contract Manufacturingwww,asq.org
This is the ASQ Web Site. Customer Service can help you on this.
or 414 272-8575 / 800 248-1946
Regards,
Randy Bock Sr.
Quality Manager
Bryce Office Systems LL
email [log in to unmask]
----- Original Message -----=20
From: Kevin Stokes=20
To: [log in to unmask]
Sent: Wednesday, April 10, 2002 4:55 PM
Subject: [TN] Benchmarking Quality in Electronics Contract =
Manufacturing
Does anyone have an idea where I can find some benchmark information =
on quality support within electronics contract manufacturing facilities?
Something like:=20
# of quality personnel/total sales=20
cost of quality/total sales=20
Please help,=20
Kevin=20
------=_NextPart_000_006F_01C1E12B.665E8B80
Content-Type: text/html;
charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD><TITLE>Benchmarking Quality in Electronics Contract =
Manufacturing</TITLE>
<META content=3D"text/html; charset=3Diso-8859-1" =
http-equiv=3DContent-Type>
<META content=3D"MSHTML 5.00.2614.3500" name=3DGENERATOR>
<STYLE></STYLE>
</HEAD>
<BODY bgColor=3D#ffffff>
<DIV><FONT size=3D2>www,asq.org</FONT></DIV>
<DIV> </DIV>
<DIV><FONT size=3D2>This is the ASQ Web Site. Customer Service can =
help you=20
on this.</FONT></DIV>
<DIV> </DIV>
<DIV><FONT size=3D2>or 414 272-8575 / 800 =
248-1946</FONT></DIV>
<DIV> </DIV>
<DIV> </DIV>
<DIV><FONT size=3D2>Regards,</FONT></DIV>
<DIV> </DIV>
<DIV><FONT size=3D2>Randy Bock Sr.</FONT></DIV>
<DIV><FONT size=3D2>Quality Manager</FONT></DIV>
<DIV><FONT size=3D2>Bryce Office Systems LL</FONT></DIV>
<DIV><FONT size=3D2>email <A=20
href=3D"mailto:[log in to unmask]">[log in to unmask]</A></FONT></DIV>
<DIV> </DIV>
<BLOCKQUOTE=20
style=3D"BORDER-LEFT: #000000 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: =
0px; PADDING-LEFT: 5px; PADDING-RIGHT: 0px">
<DIV style=3D"FONT: 10pt arial">----- Original Message ----- </DIV>
<DIV=20
style=3D"BACKGROUND: #e4e4e4; FONT: 10pt arial; font-color: =
black"><B>From:</B>=20
<A href=3D"mailto:[log in to unmask]" =
[log in to unmask]>Kevin=20
Stokes</A> </DIV>
<DIV style=3D"FONT: 10pt arial"><B>To:</B> <A =
href=3D"mailto:[log in to unmask]"=20
[log in to unmask]>[log in to unmask]</A> </DIV>
<DIV style=3D"FONT: 10pt arial"><B>Sent:</B> Wednesday, April 10, 2002 =
4:55=20
PM</DIV>
<DIV style=3D"FONT: 10pt arial"><B>Subject:</B> [TN] Benchmarking =
Quality in=20
Electronics Contract Manufacturing</DIV>
<DIV><BR></DIV>
<P><FONT size=3D2>Does anyone have an idea where I can find some =
benchmark=20
information on quality support within electronics contract =
manufacturing=20
facilities?</FONT></P>
<P><FONT size=3D2>Something like:</FONT>=20
<BR> <FONT size=3D2># of =
quality=20
personnel/total sales</FONT> =
<BR> =20
<FONT size=3D2>cost of quality/total sales</FONT> </P>
<P><FONT size=3D2>Please help,</FONT> </P>
<P><FONT size=3D2>Kevin</FONT> </P></BLOCKQUOTE></BODY></HTML>
------=_NextPart_000_006F_01C1E12B.665E8B80--
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Date: Thu, 11 Apr 2002 08:52:43 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Marsico, James" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Marsico, James" <[log in to unmask]>
Subject: Re: SIPAD flux choices
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Can a SIPAD board be produced that is 30" x 8"?
Jim Marsico
Senior Engineer
Production Engineering
EDO Electronics Systems Group
[log in to unmask] <mailto:[log in to unmask]>
631-595-5879
-----Original Message-----
From: Matt Kehoe [SMTP:[log in to unmask]]
Sent: Thursday, April 11, 2002 6:59 AM
To: [log in to unmask]
Subject: [TN] SIPAD flux choices
Dont forget, any adhesive flux can be used on SIPAD boards. The only
hook
is, it must be applied just prior to placement, so that means
printing it
yourself. Only the Promosol no-clean is designed to be applied and
dried,
papered and shipped.
Printing flux is extremely forgiving and easy to do. No hi tech
printer
needed, just a hand screening table will do. Kester makes the TSF
line
which comes in no-clean, H2O, and others exist. The paste will
already be
there in solid form. Just print the flux and send it into the chip
shooter. The stencil can be shipped with the boards to avoid extra
cost.
mk
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Date: Thu, 11 Apr 2002 06:54:39 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Houston, Terri" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Houston, Terri" <[log in to unmask]>
Subject: Coloration differences between batches of flex circuits
Hi folks,
We recently received a batch of 3-layer flex circuits, which were much
darker in color from the previous batch received (think copper colored vs.
chocolate colored).
I was told that the darker batch received a longer bake and that the
coloration difference was cosmetic.
Since I don't have a lot of experience with flex, I'm looking for input from
flex manufacturers/users on whether color differences between batches are
common and acceptable.
Thanks in advance,
Terri
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Date: Thu, 11 Apr 2002 07:52:09 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Jim Jenkins <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Jim Jenkins <[log in to unmask]>
Subject: Hand cleaners
Hi everyone,
I know this may be a minor concern, but I get a lot of complaints from
operators that they have nothing that will get rosin flux residue off their
hands. Some are very concerned about what the residue is doing to their
health. Do any of you know of a good hand cleaner (especially one that
comes in an industrial size dispenser) that removes rosin flux?
Thanks and have fun,
Jim Jenkins
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Date: Thu, 11 Apr 2002 08:15:01 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Kathy Kuhlow <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Kathy Kuhlow <[log in to unmask]>
Subject: Re: Through hole components in Reflow
Mime-Version: 1.0
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consider changing to a mail reader or gateway that understands how to
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I would look at the plastic construction and maybe go through the UL file =
requirements for that plastic. They are probably the answer on what the =
flammability rating would be with data to support it. Maybe looking at =
the UL tests you could find reasoning that your customer would accept.
Interesting problem though. We don't currently have products were pin to =
paste is possible due to several factors so I have not had to look at =
components for this recommendation. Are component manufacturer's testing =
and making recommendations for pin to paste processes (other than this =
part) or has the industry missed the boat and this will become a larger =
issue as the technology grows? =20
Kathy=20
--=_1D409970.1E7F12CA
Content-Type: text/plain
Content-Disposition: attachment; filename="TEXT.htm"
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META http-equiv=Content-Type content="text/html; charset=iso-8859-1">
<META content="MSHTML 6.00.2713.1100" name=GENERATOR></HEAD>
<BODY style="MARGIN-TOP: 2px; FONT: 10pt MS Sans Serif; MARGIN-LEFT: 2px">
<DIV>I would look at the plastic construction and maybe go through the UL file
requirements for that plastic. They are probably the answer on what the
flammability rating would be with data to support it. Maybe looking at the
UL tests you could find reasoning that your customer would accept.</DIV>
<DIV> </DIV>
<DIV>Interesting problem though. We don't currently have products were pin
to paste is possible due to several factors so I have not had to look at
components for this recommendation. Are component manufacturer's testing
and making recommendations for pin to paste processes (other than this part) or
has the industry missed the boat and this will become a larger issue as the
technology grows? </DIV>
<DIV> </DIV>
<DIV>Kathy </DIV></BODY></HTML>
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Date: Thu, 11 Apr 2002 09:34:09 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Matt Kehoe <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Matt Kehoe <[log in to unmask]>
Subject: Re: SIPAD flux choices
X-To: "Marsico, James" <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit
Sooooo Sorry, 12 x 16 is maximum size.
mk
Matt Kehoe
SIPAD Systems Inc.
360-C Winkler Drive
Alpharetta, GA. 30004
770-475-4576 fon
770-475-1597 fax
[log in to unmask]
www.sipad.net
----- Original Message -----
From: "Marsico, James" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Thursday, April 11, 2002 8:52 AM
Subject: Re: [TN] SIPAD flux choices
> Can a SIPAD board be produced that is 30" x 8"?
> Jim Marsico
> Senior Engineer
> Production Engineering
> EDO Electronics Systems Group
> [log in to unmask] <mailto:[log in to unmask]>
> 631-595-5879
>
>
> -----Original Message-----
> From: Matt Kehoe [SMTP:[log in to unmask]]
> Sent: Thursday, April 11, 2002 6:59 AM
> To: [log in to unmask]
> Subject: [TN] SIPAD flux choices
>
> Dont forget, any adhesive flux can be used on SIPAD boards. The
only
> hook
> is, it must be applied just prior to placement, so that means
> printing it
> yourself. Only the Promosol no-clean is designed to be applied and
> dried,
> papered and shipped.
>
> Printing flux is extremely forgiving and easy to do. No hi tech
> printer
> needed, just a hand screening table will do. Kester makes the TSF
> line
> which comes in no-clean, H2O, and others exist. The paste will
> already be
> there in solid form. Just print the flux and send it into the chip
> shooter. The stencil can be shipped with the boards to avoid extra
> cost.
>
> mk
>
>
> --------------------------------------------------------------------------
--
> -----
> Technet Mail List provided as a free service by IPC using LISTSERV
> 1.8d
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> text in
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> http://listserv.ipc.org/archives
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> additional
> information, or contact Keach Sasamori at [log in to unmask] or
> 847-509-9700 ext.5315
>
> --------------------------------------------------------------------------
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> -----
>
> --------------------------------------------------------------------------
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ext.5315
> --------------------------------------------------------------------------
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>
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Date: Thu, 11 Apr 2002 10:18:03 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Guy Ramsey <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Guy Ramsey <[log in to unmask]>
Subject: Re: Voids on BGA
X-To: Antonio Souza <[log in to unmask]>
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit
Some pastes are more likely to produce voids than other pastes. Talk to your
supplier. They may know something. We use many different brands and types of
paste because of our place in the industry. We saw a sudden increase in
voids, discussed it with the paste supplier, they suggested we change paste
type, we did and the problem went away.
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Antonio Souza
> Sent: Wednesday, April 10, 2002 8:25 AM
> To: [log in to unmask]
> Subject: [TN] Voids on BGA
>
>
> Does anybody know the main causes for Voids on BGA solder joints?
>
> Thanks
>
> Antonio
> Brazil
>
> ------------------------------------------------------------------
> ---------------
> Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
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> ------------------------------------------------------------------
> ---------------
>
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Date: Thu, 11 Apr 2002 10:16:30 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Randy Bock Sr." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Randy Bock Sr." <[log in to unmask]>
Subject: Re: Coloration differences between batches of flex circuits
X-To: "Houston, Terri" <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit
Info you got is true. Also, the solder mask may be a darker color.
Normally there is no
effect on the board function/reliability
Randy Bock Sr.
Quality Manager
Bryce Office Systems LLC
email [log in to unmask]
----- Original Message -----
From: Houston, Terri <[log in to unmask]>
To: <[log in to unmask]>
Sent: Thursday, April 11, 2002 8:54 AM
Subject: [TN] Coloration differences between batches of flex circuits
> Hi folks,
>
> We recently received a batch of 3-layer flex circuits, which were much
> darker in color from the previous batch received (think copper colored vs.
> chocolate colored).
>
> I was told that the darker batch received a longer bake and that the
> coloration difference was cosmetic.
>
> Since I don't have a lot of experience with flex, I'm looking for input
from
> flex manufacturers/users on whether color differences between batches are
> common and acceptable.
>
> Thanks in advance,
>
> Terri
>
> --------------------------------------------------------------------------
-------
> Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
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> Please visit IPC web site http://www.ipc.org/html/forum.htm for additional
> information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700
ext.5315
> --------------------------------------------------------------------------
-------
>
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Date: Thu, 11 Apr 2002 10:19:49 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Randy Bock Sr." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Randy Bock Sr." <[log in to unmask]>
Subject: Re: Hand cleaners
X-To: Jim Jenkins <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit
An orange cleaner is a good industrial cleaner. I believe there is a hand
cream that acts like invisible skin that will help the flux from sticking to
your skin, I do not know its name however.
----- Original Message -----
From: Jim Jenkins <[log in to unmask]>
To: <[log in to unmask]>
Sent: Thursday, April 11, 2002 8:52 AM
Subject: [TN] Hand cleaners
> Hi everyone,
>
> I know this may be a minor concern, but I get a lot of complaints from
> operators that they have nothing that will get rosin flux residue off
their
> hands. Some are very concerned about what the residue is doing to their
> health. Do any of you know of a good hand cleaner (especially one that
> comes in an industrial size dispenser) that removes rosin flux?
>
> Thanks and have fun,
>
> Jim Jenkins
>
> --------------------------------------------------------------------------
-------
> Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
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> Please visit IPC web site http://www.ipc.org/html/forum.htm for additional
> information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700
ext.5315
> --------------------------------------------------------------------------
-------
>
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Date: Thu, 11 Apr 2002 10:22:44 EDT
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Hand cleaners
MIME-Version: 1.0
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Hi Jim!
As a matter of fact, I just received a sample bottle of a new hand cleaner
from Kyzen.
It's called "Dermaklenz" D8001. I gave it to our wave solder supervisor to
try it out and see how she liked it, and she said it works great! It's a
waterless hand cleaner too. She said it takes rosin flux off her hands no
problem.
They don't have anything up on their web page yet, but you can call them at:
(615) 831- 0888
It comes in a case of twelve 8-ounce bottles, and is $2.80 a bottle (get
cheaper if you buy more cases).
-Steve Gregory-
> Hi everyone,
>
> I know this may be a minor concern, but I get a lot of complaints from
> operators that they have nothing that will get rosin flux residue off their
> hands. Some are very concerned about what the residue is doing to their
> health. Do any of you know of a good hand cleaner (especially one that
> comes in an industrial size dispenser) that removes rosin flux?
>
> Thanks and have fun,
>
> Jim Jenkins
>
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<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>Hi Jim!
<BR>
<BR>As a matter of fact, I just received a sample bottle of a new hand cleaner from Kyzen.
<BR>It's called "Dermaklenz" D8001. I gave it to our wave solder supervisor to try it out and see how she liked it, and she said it works great! It's a waterless hand cleaner too. She said it takes rosin flux off her hands no problem.
<BR>
<BR>They don't have anything up on their web page yet, but you can call them at:
<BR>
<BR>(615) 831- 0888
<BR>
<BR>It comes in a case of twelve 8-ounce bottles, and is $2.80 a bottle (get cheaper if you buy more cases).
<BR>
<BR>-Steve Gregory-
<BR>
<BR>
<BR><BLOCKQUOTE TYPE=CITE style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">Hi everyone,
<BR>
<BR>I know this may be a minor concern, but I get a lot of complaints from
<BR>operators that they have nothing that will get rosin flux residue off their
<BR>hands. Some are very concerned about what the residue is doing to their
<BR>health. Do any of you know of a good hand cleaner (especially one that
<BR>comes in an industrial size dispenser) that removes rosin flux?
<BR>
<BR>Thanks and have fun,
<BR>
<BR>Jim Jenkins
<BR></FONT><FONT COLOR="#000000" SIZE=3 FAMILY="SANSSERIF" FACE="Arial" LANG="0"></BLOCKQUOTE>
<BR></FONT><FONT COLOR="#000000" SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0">
<BR></FONT></HTML>
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Date: Thu, 11 Apr 2002 17:34:22 +0300
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Brian Ellis <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Brian Ellis <[log in to unmask]>
Subject: Re: Hand cleaners
X-To: Jim Jenkins <[log in to unmask]>
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Good question, Jim. Traditionally, most people have used IPA or another
light alcohol for this, followed by a good, strong hand-detergent wash
(in the UK, there used to be a green jelly-like hand detergent which was
very good. It was called Swarfega, but I don't know whether it is still
available or whether it is exported). This is not a very good idea,
except for a VERY occasional accident. Light alcohols goes straight
through the skin like a sieve. Keep your hand in ethanol for 15 minutes
or so and see the increase in a breathalyser test! Do it with methanol
and you risk grave problems (long enough, and the grave may be the
result!). At one time, I used an industrial pink soap which was loaded
with an abrasive, possibly quartz sand. This was popular with garage
mechies as it was good at getting dirty oils and greases off. With
rosin, it worked, but it needed perserverance and a good 10 minutes. The
ladies don't like it, though, as it roughens the hands like no
washing-up liquid does. Similarly, I've sprinkled dishwasher powder onto
my wet, fairy-like mitts and this will both work but just about take the
skin off, as well.
I hesitate to recommend glycol-based products, some of which are quite
good, because the dermal uptake may be bad. However, I feel that a
terpene may be a good answer: they can dissolve rosin and the tricyclic
molecule would probably have difficulty in penetrating the skin to any
significant extent. My first try would therefore be common or garden
artists' turpentine, followed by a good hand-detergent wash. Do NOT use
one of the cheap turpentine substitutes which are based on white
spirits, though.
However, prevention is better than cure. The obvious answer is do not
get rosin on the hands. Gloves act as a preventitive, including those
chuck-away ones made of thin polyethylene. If, for any reason, these
cannot be used, then think about barrier creams (careful not to get any
on assemblies, though!). Analyse where the handling deposits rosin and
eliminate that operation - at least, in a contaminating way.
BTW, I don't think there could possibly be any health hazard associated
with rosin on the skin (normal people) but I agree that it's bloody
uncomfortable :-( After all, the sticky stuff on Band-Aids, Elastoplast,
Sparadrap and so on has a high percentage of rosin in it. Some
individuals do exhibit a cutaneous hypersensitivity reaction to rosin,
but these persons should not be working with the stuff, anyway.
You could always change to a water-soluble flux, as well :-)
Brian
Jim Jenkins wrote:
>
> Hi everyone,
>
> I know this may be a minor concern, but I get a lot of complaints from
> operators that they have nothing that will get rosin flux residue off their
> hands. Some are very concerned about what the residue is doing to their
> health. Do any of you know of a good hand cleaner (especially one that
> comes in an industrial size dispenser) that removes rosin flux?
>
> Thanks and have fun,
>
> Jim Jenkins
>
> ---------------------------------------------------------------------------------
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Date: Thu, 11 Apr 2002 10:45:40 EDT
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Rudy Sedlak <[log in to unmask]>
Subject: Re: Hand cleaners, Orange Oil based
MIME-Version: 1.0
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FYI
The orange oil which has become so popular of late is a very powerful
solvent, and a very good cleaner base, however, just because it is "natural",
does not imply that it is harmless.
Because it is such a powerful solvent, it can be irritating. I recommend if
you use it, make sure you remove it quickly, and completely. I use this kind
of hand cleaner occasionally, and think it is great, but actually wash my
hands with soap and water afterwards.
Rudy Sedlak
RD Chemical Company
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<HTML><FONT FACE=arial,helvetica><FONT SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0">FYI<BR>
<BR>
The orange oil which has become so popular of late is a very powerful solvent, and a very good cleaner base, however, just because it is "natural", does not imply that it is harmless.<BR>
<BR>
Because it is such a powerful solvent, it can be irritating. I recommend if you use it, make sure you remove it quickly, and completely. I use this kind of hand cleaner occasionally, and think it is great, but actually wash my hands with soap and water afterwards.<BR>
<BR>
Rudy Sedlak<BR>
RD Chemical Company</FONT></HTML>
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Date: Thu, 11 Apr 2002 07:48:22 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Crepeau, Phil" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Crepeau, Phil" <[log in to unmask]>
Subject: Re: Nickel Test
X-To: [log in to unmask]
MIME-Version: 1.0
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hi,
there is a classic text in chemistry by feigl that has to do with spot =
testing. that should get you what you want.
phil
-----Original Message-----
From: Rudy Sedlak [mailto:[log in to unmask]]
Sent: Wednesday, April 10, 2002 6:25 PM
To: [log in to unmask]
Subject: [TN] Nickel Test
I recall seeing a spot test for Nickel that involved using a solution of
Dimethylglyoxime in dilute Ammonia, + ???? as a spot test for gold =
porosity
to show presence of Nickel.
Does anyone have the exact details of this test? Does anyone know if it
works on Electroless Nickel? (Suspect it may not because EN is so much =
more
passive.)
Rudy Sedlak
RD Chemical Company
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Date: Thu, 11 Apr 2002 11:01:23 -0400
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Chris Christian <[log in to unmask]>
Subject: Re: Voids on BGA
X-To: Guy Ramsey <[log in to unmask]>
In-Reply-To: <[log in to unmask]>
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Also, depending on the paste, an adjusted profile can go a long way to
eliminate, reduce voiding.
Chris
Indium Corp.
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Guy Ramsey
Sent: Thursday, April 11, 2002 10:18 AM
To: [log in to unmask]
Subject: Re: [TN] Voids on BGA
Some pastes are more likely to produce voids than other pastes. Talk to your
supplier. They may know something. We use many different brands and types of
paste because of our place in the industry. We saw a sudden increase in
voids, discussed it with the paste supplier, they suggested we change paste
type, we did and the problem went away.
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Antonio Souza
> Sent: Wednesday, April 10, 2002 8:25 AM
> To: [log in to unmask]
> Subject: [TN] Voids on BGA
>
>
> Does anybody know the main causes for Voids on BGA solder joints?
>
> Thanks
>
> Antonio
> Brazil
>
> ------------------------------------------------------------------
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Date: Thu, 11 Apr 2002 09:57:43 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
[log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Richard Carruth <[log in to unmask]>
Subject: Re: Benchmarking Quality in Electronics Contract Manufacturing
X-To: Kevin Stokes <[log in to unmask]>
Mime-Version: 1.0
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You might want to check out the following web site www.ceeris.com
Richard
Kevin Stokes <[log in to unmask]> on 04/10/2002 03:55:52 PM
Please respond to "TechNet E-Mail Forum." <[log in to unmask]>; Please respond to
Kevin Stokes <[log in to unmask]>
To: [log in to unmask]
cc: (bcc: Richard Carruth/LABARGE)
Subject: [TN] Benchmarking Quality in Electronics Contract Manufacturing
Does anyone have an idea where I can find some benchmark information on
quality support within electronics contract manufacturing facilities?
Something like:
# of quality personnel/total sales
cost of quality/total sales
Please help,
Kevin
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Date: Thu, 11 Apr 2002 11:40:21 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Randy Bock Sr." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Randy Bock Sr." <[log in to unmask]>
Subject: Re: Hand cleaners, Orange Oil based
X-To: [log in to unmask]
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="----=_NextPart_000_002A_01C1E14D.A9B494C0"
This is a multi-part message in MIME format.
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Good info, thanks
----- Original Message -----=20
From: Rudy Sedlak=20
To: [log in to unmask]
Sent: Thursday, April 11, 2002 10:45 AM
Subject: Re: [TN] Hand cleaners, Orange Oil based
FYI
The orange oil which has become so popular of late is a very powerful =
solvent, and a very good cleaner base, however, just because it is =
"natural", does not imply that it is harmless.
Because it is such a powerful solvent, it can be irritating. I =
recommend if you use it, make sure you remove it quickly, and =
completely. I use this kind of hand cleaner occasionally, and think it =
is great, but actually wash my hands with soap and water afterwards.
Rudy Sedlak
RD Chemical Company=20
------=_NextPart_000_002A_01C1E14D.A9B494C0
Content-Type: text/html;
charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META content=3D"text/html; charset=3Diso-8859-1" =
http-equiv=3DContent-Type>
<META content=3D"MSHTML 5.00.2614.3500" name=3DGENERATOR>
<STYLE></STYLE>
</HEAD>
<BODY bgColor=3D#ffffff>
<DIV><FONT size=3D2>Good info, thanks</FONT></DIV>
<BLOCKQUOTE=20
style=3D"BORDER-LEFT: #000000 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: =
0px; PADDING-LEFT: 5px; PADDING-RIGHT: 0px">
<DIV style=3D"FONT: 10pt arial">----- Original Message ----- </DIV>
<DIV=20
style=3D"BACKGROUND: #e4e4e4; FONT: 10pt arial; font-color: =
black"><B>From:</B>=20
<A href=3D"mailto:[log in to unmask]" [log in to unmask]>Rudy =
Sedlak</A> </DIV>
<DIV style=3D"FONT: 10pt arial"><B>To:</B> <A =
href=3D"mailto:[log in to unmask]"=20
[log in to unmask]>[log in to unmask]</A> </DIV>
<DIV style=3D"FONT: 10pt arial"><B>Sent:</B> Thursday, April 11, 2002 =
10:45=20
AM</DIV>
<DIV style=3D"FONT: 10pt arial"><B>Subject:</B> Re: [TN] Hand =
cleaners, Orange=20
Oil based</DIV>
<DIV><BR></DIV><FONT face=3Darial,helvetica><FONT face=3DArial =
lang=3D0 size=3D2=20
FAMILY=3D"SANSSERIF">FYI<BR><BR>The orange oil which has become so =
popular of=20
late is a very powerful solvent, and a very good cleaner base, =
however, just=20
because it is "natural", does not imply that it is =
harmless.<BR><BR>Because it=20
is such a powerful solvent, it can be irritating. I recommend if =
you use=20
it, make sure you remove it quickly, and completely. I use this =
kind of=20
hand cleaner occasionally, and think it is great, but actually wash my =
hands=20
with soap and water afterwards.<BR><BR>Rudy Sedlak<BR>RD Chemical=20
Company</FONT> </FONT></BLOCKQUOTE></BODY></HTML>
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Date: Thu, 11 Apr 2002 10:42:45 -0500
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Glenn Wells <[log in to unmask]>
Subject: Humorous Stories
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Do you have any funny or humorous stories to share about anything relating
to printed circuit design, fab, assembly, test, etc.?
If you have any humorous stories to share about anything relating to printed
circuit boards please PM them directly to me.
Please do not use any names of individuals that may have been involved in
the stories.
Glenn
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Date: Thu, 11 Apr 2002 11:53:03 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Goldman, Patricia J." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Goldman, Patricia J." <[log in to unmask]>
Subject: Re: Nickel Test
X-To: "[log in to unmask]" <[log in to unmask]>
MIME-Version: 1.0
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I have used this test. It is a great test for gold porosity, as nickel shows up red and copper shows up green. However, you must apply current to run the test. I believe there is an IPC test method for it but don't have time to dig through the online TM's. If not, I may be able to locate it here. It sure beat using nitric acid.
I think the original procedure I saw came from IBM, about 15-20 or so years ago.
Patty
Patricia J. Goldman
PPG Industries, Inc.
724-274-3417
[log in to unmask]
-----Original Message-----
From: Rudy Sedlak [mailto:[log in to unmask]]
Sent: Wednesday, April 10, 2002 9:25 PM
To: [log in to unmask]
Subject: [TN] Nickel Test
I recall seeing a spot test for Nickel that involved using a solution of
Dimethylglyoxime in dilute Ammonia, + ???? as a spot test for gold porosity
to show presence of Nickel.
Does anyone have the exact details of this test? Does anyone know if it
works on Electroless Nickel? (Suspect it may not because EN is so much more
passive.)
Rudy Sedlak
RD Chemical Company
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Date: Thu, 11 Apr 2002 09:02:09 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Barmuta, Mike" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Barmuta, Mike" <[log in to unmask]>
Subject: Re: Nickel Test
X-To: "[log in to unmask]" <[log in to unmask]>
MIME-Version: 1.0
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Rudy: I've used a solution made up of conc reagent grade; alcohol 100ml +
ammonia 50ml + dimethylglyoxime 2gm.
Do a drop or spot test on the plating sample. If nickel is present a pink to
red fleck of Ni-dimethylglyoxime will form.
Rubbing with filter paper will help bring out the color, as it is hard to
see against the Au.
Regards
Michael Barmuta
Staff Engineer
Fluke Corp.
Everett WA
$25-356-6076
-----Original Message-----
From: Rudy Sedlak [mailto:[log in to unmask]]
Sent: Wednesday, April 10, 2002 6:25 PM
To: [log in to unmask]
Subject: [TN] Nickel Test
I recall seeing a spot test for Nickel that involved using a solution of
Dimethylglyoxime in dilute Ammonia, + ???? as a spot test for gold porosity
to show presence of Nickel.
Does anyone have the exact details of this test? Does anyone know if it
works on Electroless Nickel? (Suspect it may not because EN is so much more
passive.)
Rudy Sedlak
RD Chemical Company
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Date: Thu, 11 Apr 2002 12:13:53 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Steve Kelly <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Steve Kelly <[log in to unmask]>
Subject: Re: Coloration differences between batches of flex circuits
X-To: "Houston, Terri" <[log in to unmask]>
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
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In my opinion slight colouration differences between batches is not abnormal
but I do mean slight. I would need to know the material build to determine
if it could be a problem. Regards Steve Kelly
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Houston, Terri
Sent: Thursday, April 11, 2002 8:55 AM
To: [log in to unmask]
Subject: [TN] Coloration differences between batches of flex circuits
Hi folks,
We recently received a batch of 3-layer flex circuits, which were much
darker in color from the previous batch received (think copper colored vs.
chocolate colored).
I was told that the darker batch received a longer bake and that the
coloration difference was cosmetic.
Since I don't have a lot of experience with flex, I'm looking for input from
flex manufacturers/users on whether color differences between batches are
common and acceptable.
Thanks in advance,
Terri
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Date: Thu, 11 Apr 2002 09:36:08 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Jana Carraway <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Jana Carraway <[log in to unmask]>
Subject: Re: Chemistry of discoloration?
X-To: "Randy Bock Sr." <[log in to unmask]>
In-Reply-To: <000801c1e163$7a73b5e0$0302a8c0@randy>
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Can someone explain the reactions of the discoloration for polyimide and
soldermask? These materials would continue to cure with exposure to
extended heat cycles, what is the mechanism of the discoloration? The
materials continue to cross-link, which in the case of soldermask leads to
brittle mask, but what other reactions are taking place and why the color
change?
This just seems like a good day for a chemistry lesson!
Thanks,
Jana Carraway
MSEI
PS - Hans Hinner, how does getting married make your a spud? I come from
Idaho, the potato state, and hence am a "spud"...regardless of marital
state!
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Date: Thu, 11 Apr 2002 11:37:58 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Bill Butman <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Bill Butman <[log in to unmask]>
Subject: Re: Chemistry of discoloration?
X-To: Jana Carraway <[log in to unmask]>
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
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HI Jana,
I can't answer the chemistry question, but regarding
your question to Hans ----- I thought he made a
spelling error when he spelled spud!??
thanx
Bill
--- Jana Carraway <[log in to unmask]> wrote:
> Can someone explain the reactions of the
> discoloration for polyimide and
> soldermask? These materials would continue to cure
> with exposure to
> extended heat cycles, what is the mechanism of the
> discoloration? The
> materials continue to cross-link, which in the case
> of soldermask leads to
> brittle mask, but what other reactions are taking
> place and why the color
> change?
>
> This just seems like a good day for a chemistry
> lesson!
>
> Thanks,
> Jana Carraway
> MSEI
>
> PS - Hans Hinner, how does getting married make your
> a spud? I come from
> Idaho, the potato state, and hence am a
> "spud"...regardless of marital
> state!
>
>
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Date: Thu, 11 Apr 2002 15:10:48 EDT
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Rudy Sedlak <[log in to unmask]>
Subject: Re: Chemistry of discoloration?
MIME-Version: 1.0
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Jana:
You have asked a BIG question.
There really is no known absolute answer.
Organics tend to discolor, if they have any sort of reactivity left in them,
and often, under the right circumstances even if they do not have any
reactivity left in them.
The general rule is they turn dark(er). The reactions are many, and clearly
going to be dependent on the base material. Discoloration is driven by heat,
and often exposure to sunlight.
Not to get too technical, but polymers (laminate, and soldermask, for
example) only rarely really react fully, and there is almost always some
unreacted polymer (called monomer when it is totally unreacted, and oligomer
when it is partially reacted) lurking in the matrix. When this contacts air,
water, and heat and UV, all sorts of unexpected things happen. In fact,
these very polymers often have added "preservatives" to prevent these
post-polymerization reactions from occurring.
The bottom line is (as if this really has ANY significanse in our industry)
that this discoloration rarely affects the physical properties of the
polymer. I think a great English playwright described this situation
centuries ago..."Much ado about nothing"?
Rudy Sedlak
RD Chemical Company
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Date: Thu, 11 Apr 2002 14:54:21 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Charles Caswell <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Charles Caswell <[log in to unmask]>
Subject: Re: Hand cleaners
MIME-Version: 1.0
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I used to keep a bar of naptha soap in the restroom when I was working =
wave solder . Works for the rosin and the grease. Also good to take it =
out of clothes.
Charles Caswell
Process Lead, PCB
Frontier Electronic Systems=20
-----Original Message-----
From: Jim Jenkins [mailto:[log in to unmask]]
Sent: Thursday, April 11, 2002 7:52 AM
To: [log in to unmask]
Subject: [TN] Hand cleaners
Hi everyone,
I know this may be a minor concern, but I get a lot of complaints from
operators that they have nothing that will get rosin flux residue off =
their
hands. Some are very concerned about what the residue is doing to their
health. Do any of you know of a good hand cleaner (especially one that
comes in an industrial size dispenser) that removes rosin flux?
Thanks and have fun,
Jim Jenkins
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Date: Thu, 11 Apr 2002 16:41:23 EDT
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Pot washers!
MIME-Version: 1.0
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Although they are not in UK as requested, EMC introduced an excellent unit of
this description at APEX.
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Date: Thu, 11 Apr 2002 16:56:04 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Hinners Hans M Civ WRALC/LUGE <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Hinners Hans M Civ WRALC/LUGE <[log in to unmask]>
Subject: Off Topic - The Married Spud & other burning questions
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Hey All,
Whew! Projects pop out of the woodwork when you're going on holiday.
I passed pics onto Steve - so you don't have to go to the Post Office to see
what I look like. LOL
Why am I still at work?
We are going on a honeymoon cruise and it leaves this weekend. Eastern
Caribbean - Puerto Rico, St. Thomas, St. Marteen, & Bahamas
I'm a married spud because . . .
A reference to Toy Story 2. Mr. Potato head keeps repeating "I'm a married
spud." when they are in the Toy Store. If I really lose it I might start
talking in nothing but movie quotes - product of a wasted childhood &
hanging out with Cinema students at USC.
Tech Net Advice on Marriage?
My better half, Shannan, has been discussing our wedding plans on her list @
http://www.ultimatewedding.com/
Her newlywed journal is @
http://www.weddingchat.com/showthread.php?s=&threadid=116583
All right I'll bite - what advice would the list share? Off line for
netiquette sake.
Hans
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Date: Thu, 11 Apr 2002 14:04:51 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Jana Carraway <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Jana Carraway <[log in to unmask]>
Subject: Re: Chemistry of discoloration?
X-To: [log in to unmask]
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="us-ascii"
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Rudy, you can even use "free radical initiation"! There must be some
formulations folks out there who can divulge a bit more about the reactions
without giving away formulation secrets! Dr. Roos, you out there???
Thanks for the info Rudy,
Jana Carraway
MSEI
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Rudy Sedlak
Sent: Thursday, April 11, 2002 12:11 PM
To: [log in to unmask]
Subject: Re: [TN] Chemistry of discoloration?
Jana:
You have asked a BIG question.
There really is no known absolute answer.
Organics tend to discolor, if they have any sort of reactivity left in them,
and often, under the right circumstances even if they do not have any
reactivity left in them.
The general rule is they turn dark(er). The reactions are many, and clearly
going to be dependent on the base material. Discoloration is driven by
heat,
and often exposure to sunlight.
Not to get too technical, but polymers (laminate, and soldermask, for
example) only rarely really react fully, and there is almost always some
unreacted polymer (called monomer when it is totally unreacted, and oligomer
when it is partially reacted) lurking in the matrix. When this contacts
air,
water, and heat and UV, all sorts of unexpected things happen. In fact,
these very polymers often have added "preservatives" to prevent these
post-polymerization reactions from occurring.
The bottom line is (as if this really has ANY significanse in our industry)
that this discoloration rarely affects the physical properties of the
polymer. I think a great English playwright described this situation
centuries ago..."Much ado about nothing"?
Rudy Sedlak
RD Chemical Company
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Date: Thu, 11 Apr 2002 16:02:23 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Ed Popielarski <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Ed Popielarski <[log in to unmask]>
Subject: Solder Ball Wrinkles
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Larry,
I may have seen those wrinkles on re-balled devices. Try spraying some =
wave solder flux on them and re-run through the reflow oven. If they go =
away, it's most likely caused by oxides. The theory is that the oxides =
formed on the surface act like a "skin" held intact via surface tension. =
As the ball reflows, some of the "good solder" inside the ball wets out =
to the pad surfaces and forms a fillet, thereby decreasing the actual =
volume of "good solder" inside the "skin" of oxide. This behaves =
somewhat like partially deflating a beach ball and the surface crinkles, =
sometimes looking like it has scales.
I have a few pics if you'd like to see what I've experienced (or perhaps =
Steve might like to add them to his gallery of fame and flame!?)
Regards,
Ed Popielarski
QTA Machine
10 Mc Laren, Ste D
Irvine, Ca. 92618
Phone:949-581-6601
Fax: 949-581-2448
Cel: 949-337-2578
WWW.QTA.NET
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charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META http-equiv=3DContent-Type content=3D"text/html; =
charset=3Diso-8859-1">
<META content=3D"MSHTML 5.50.4807.2300" name=3DGENERATOR>
<STYLE></STYLE>
</HEAD>
<BODY bgColor=3D#ffffff>
<DIV><FONT face=3DArial size=3D2>Larry,</FONT></DIV>
<DIV><FONT face=3DArial size=3D2></FONT> </DIV>
<DIV><FONT face=3DArial size=3D2>I may have seen those wrinkles on =
re-balled=20
devices. Try spraying some wave solder flux on them and re-run through =
the=20
reflow oven. If they go away, it's most likely caused by oxides. The =
theory is=20
that the oxides formed on the surface act like a "skin" held intact via =
surface=20
tension. As the ball reflows, some of the "good solder" inside the ball =
wets out=20
to the pad surfaces and forms a fillet, thereby decreasing the actual =
volume of=20
"good solder" inside the "skin" of oxide. This behaves somewhat like =
partially=20
deflating a beach ball and the surface crinkles, sometimes looking like =
it has=20
scales.</FONT></DIV>
<DIV><FONT face=3DArial size=3D2></FONT> </DIV>
<DIV><FONT face=3DArial size=3D2>I have a few pics if you'd like to see =
what I've=20
experienced (or perhaps Steve might like to add them to his gallery of =
fame and=20
flame!?)</FONT></DIV>
<DIV><FONT face=3DArial size=3D2></FONT> </DIV>
<DIV><FONT face=3DArial size=3D2>Regards,</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=3DArial size=3D2>Ed Popielarski<BR>QTA Machine<BR>10 Mc =
Laren, Ste=20
D<BR>Irvine, Ca. 92618</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=3DArial size=3D2>Phone:949-581-6601<BR>Fax: =
949-581-2448<BR>Cel:=20
949-337-2578</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=3DArial size=3D2><A=20
href=3D"http://www.QTA.NET">WWW.QTA.NET</A></FONT></DIV></BODY></HTML>
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Date: Fri, 12 Apr 2002 07:49:02 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Hand cleaners
X-To: Jim Jenkins <[log in to unmask]>
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The 'deb' Company that makes Swarfega (for those with a green slime fettish
and oily/greasey hands), also make a very good hand cleaner for resin and
adhesive. Can't quite recall the name of it, but it's effective, even
though it smells quite acrid/pungent, is gritty and stings rather if it
gets into cuts in the skin.
Peter
Jim Jenkins
<jjenki09@HAR To: [log in to unmask]
RIS.COM> cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
Sent by: Aero/ST Group)
TechNet Subject: [TN] Hand cleaners
<[log in to unmask]
ORG>
04/11/02
08:52 PM
Please
respond to
"TechNet
E-Mail
Forum.";
Please
respond to
Jim Jenkins
Hi everyone,
I know this may be a minor concern, but I get a lot of complaints from
operators that they have nothing that will get rosin flux residue off their
hands. Some are very concerned about what the residue is doing to their
health. Do any of you know of a good hand cleaner (especially one that
comes in an industrial size dispenser) that removes rosin flux?
Thanks and have fun,
Jim Jenkins
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Date: Thu, 11 Apr 2002 16:49:26 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Keel, Mike" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Keel, Mike" <[log in to unmask]>
Subject: Re: Off Topic - The Married Spud & other burning questions
X-To: Hinners Hans M Civ WRALC/LUGE <[log in to unmask]>
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is
netiquette sake
rice wine, made in France ? ?
eye believe we owe our families, and associates
a light-hearted attitude . . .
although eye am sure not everyone will agree
M Keel
E. O. S.
-----Original Message-----
From: Hinners Hans M Civ WRALC/LUGE [mailto:[log in to unmask]]
Sent: Thursday, April 11, 2002 9:56 PM
To: [log in to unmask]
Subject: [TN] Off Topic - The Married Spud & other burning questions
Hey All,
Whew! Projects pop out of the woodwork when you're going on holiday.
I passed pics onto Steve - so you don't have to go to the Post Office to see
what I look like. LOL
Why am I still at work?
We are going on a honeymoon cruise and it leaves this weekend. Eastern
Caribbean - Puerto Rico, St. Thomas, St. Marteen, & Bahamas
I'm a married spud because . . .
A reference to Toy Story 2. Mr. Potato head keeps repeating "I'm a married
spud." when they are in the Toy Store. If I really lose it I might start
talking in nothing but movie quotes - product of a wasted childhood &
hanging out with Cinema students at USC.
Tech Net Advice on Marriage?
My better half, Shannan, has been discussing our wedding plans on her list @
http://www.ultimatewedding.com/
Her newlywed journal is @
http://www.weddingchat.com/showthread.php?s=&threadid=116583
All right I'll bite - what advice would the list share? Off line for
netiquette sake.
Hans
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Date: Thu, 11 Apr 2002 19:24:46 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Richard Martin <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Richard Martin <[log in to unmask]>
Subject: Re: SIPAD Shelf Life
On Thu, 11 Apr 2002 05:46:40 -0500, Matt Kehoe <[log in to unmask]> wrote:
>Short shelf life is relative. We have documented the shelf life of SIPAD
>boards of up to 14 months. We also have many samples that are more than 2
>years old, have been stored in less than ideal conditions, (in my breif
>case, car trunk etc), and they are still very tacky. Also, if for some
>reason they do dry out, they can be cleaned and re-fluxed.
>
>As far as a stacker is concerned, SIPAD boards were used in the Easi line
>at the Assembly Technology Expo one year, with a stacker system that was
>very clever. The boards were placed into the stacker paper side down. A
>suction cup handler picked up the board, placed it on the conveyor where
>it was carried over a small air knife that blew off the paper, dropping it
>into a box underneath. The board transported into an inverter where it was
>flipped, tacky side up now, and sent into the pick and place machine.
>
>We have access to this equipment if you are interested.
>
>mk
>
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Date: Fri, 12 Apr 2002 08:51:39 +0100
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Mike Fenner <[log in to unmask]>
Subject: Re: connecting aluminum to copper
X-To: Phil Nutting <[log in to unmask]>
In-Reply-To: <[log in to unmask]>
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Aluminium to anything will fairly quickly go electrically open circuit,
although you will retain thermal conductivity. Depending on the conditions
of use and the contact metal you will next slowly or quickly achieve all
sorts of corrosion issues. Immunise the aluminium from the outside world
with something more stable like nickel
Kind Regards
Mike Fenner
Applications Engineer, European Operations
Indium Corporation
T: + 44 1908 580 400
M: + 44 7810 526 317
F: + 44 1908 580 411
E: [log in to unmask]
W: www.indium.com
Leadfree: www.Pb-Free.com
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Phil Nutting
Sent: Wednesday, April 10, 2002 9:12 PM
To: [log in to unmask]
Subject: [TN] connecting aluminum to copper
Good afternoon TechNet,
Would anyone like to share their knowledge about using an aluminum standoff
as a conductor when connecting two circuit boards together. I suspect that
if it were aluminum to copper there would be an issue, but what about
aluminum to HASL surface of circuit boards?
Thanks in advance for your wisdom,
Phil Nutting
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Date: Fri, 12 Apr 2002 09:02:31 +0100
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Mike Fenner <[log in to unmask]>
Subject: Re: Hand cleaners
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
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I can't quite remember the name of it either although I have used it and it
works well. These sorts of resin cleaners are all quite powerful so repeated
use will defeat the skin quite strongly - suggest you also get their skin
cream, will stop skin cracking, etc. Use of IPA, flux thinners flux
removers etc should be seriously discouraged, repeated and deliberate
contact with these is bad for you.
Kind Regards
Mike Fenner
Applications Engineer, European Operations
Indium Corporation
T: + 44 1908 580 400
M: + 44 7810 526 317
F: + 44 1908 580 411
E: [log in to unmask]
W: www.indium.com
Leadfree: www.Pb-Free.com
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of
[log in to unmask]
Sent: Friday, April 12, 2002 12:49 AM
To: [log in to unmask]
Subject: Re: [TN] Hand cleaners
The 'deb' Company that makes Swarfega (for those with a green slime fettish
and oily/greasey hands), also make a very good hand cleaner for resin and
adhesive. Can't quite recall the name of it, but it's effective, even
though it smells quite acrid/pungent, is gritty and stings rather if it
gets into cuts in the skin.
Peter
----
Hi everyone,
I know this may be a minor concern, but I get a lot of complaints from
operators that they have nothing that will get rosin flux residue off their
hands. Some are very concerned about what the residue is doing to their
health. Do any of you know of a good hand cleaner (especially one that
comes in an industrial size dispenser) that removes rosin flux?
Thanks and have fun,
Jim Jenkins
---------------------------------------------------------------------------------
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Date: Fri, 12 Apr 2002 09:01:22 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Bev Christian <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Bev Christian <[log in to unmask]>
Subject: Re: Solder Ball Wrinkles
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Larry,
Ed's analogy is very good. It might be extenuated by incomplete reflow.
Now when I say that I am not talking about a serious situation. Let me
explain. We have seen this phenomenon for reflowed solder balls on
components attached to boards. When we cross-section there are good bonds to
the component and board, but the balls have the surface texture you
describe. The microstructure shows the ball could have stood just a hair
more time/temperature at the reflow peak.
regards,
Bev Christian
Research in Motion
-----Original Message-----
From: Ed Popielarski [mailto:[log in to unmask]]
Sent: April 11, 2002 7:02 PM
To: [log in to unmask]
Subject: [TN] Solder Ball Wrinkles
Larry,
I may have seen those wrinkles on re-balled devices. Try spraying some wave
solder flux on them and re-run through the reflow oven. If they go away,
it's most likely caused by oxides. The theory is that the oxides formed on
the surface act like a "skin" held intact via surface tension. As the ball
reflows, some of the "good solder" inside the ball wets out to the pad
surfaces and forms a fillet, thereby decreasing the actual volume of "good
solder" inside the "skin" of oxide. This behaves somewhat like partially
deflating a beach ball and the surface crinkles, sometimes looking like it
has scales.
I have a few pics if you'd like to see what I've experienced (or perhaps
Steve might like to add them to his gallery of fame and flame!?)
Regards,
Ed Popielarski
QTA Machine
10 Mc Laren, Ste D
Irvine, Ca. 92618
Phone:949-581-6601
Fax: 949-581-2448
Cel: 949-337-2578
WWW.QTA.NET <http://www.QTA.NET>
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</HEAD>
<BODY bgColor=#ffffff>
<DIV><SPAN class=019415512-12042002><FONT face=Arial color=#0000ff
size=2>Larry,</FONT></SPAN></DIV>
<DIV><SPAN class=019415512-12042002><FONT face=Arial color=#0000ff size=2>Ed's
analogy is very good. It might be extenuated by incomplete
reflow. Now when I say that I am not talking about a serious
situation. Let me explain. We have seen this phenomenon for reflowed
solder balls on components attached to boards. When we cross-section there are
good bonds to the component and board, but the balls have the surface texture
you describe. The microstructure shows the ball could have stood just a
hair more time/temperature at the reflow peak.</FONT></SPAN></DIV>
<DIV><SPAN class=019415512-12042002><FONT face=Arial color=#0000ff
size=2></FONT></SPAN> </DIV>
<DIV><SPAN class=019415512-12042002><FONT face=Arial color=#0000ff
size=2>regards,</FONT></SPAN></DIV>
<DIV><SPAN class=019415512-12042002><FONT face=Arial color=#0000ff size=2>Bev
Christian</FONT></SPAN></DIV>
<DIV><SPAN class=019415512-12042002><FONT face=Arial color=#0000ff
size=2>Research in Motion</FONT></SPAN></DIV>
<BLOCKQUOTE dir=ltr style="MARGIN-RIGHT: 0px">
<DIV class=OutlookMessageHeader dir=ltr align=left><FONT face=Tahoma
size=2>-----Original Message-----<BR><B>From:</B> Ed Popielarski
[mailto:[log in to unmask]]<BR><B>Sent:</B> April 11, 2002 7:02
PM<BR><B>To:</B> [log in to unmask]<BR><B>Subject:</B> [TN] Solder Ball
Wrinkles<BR><BR></FONT></DIV>
<DIV><FONT face=Arial size=2>Larry,</FONT></DIV>
<DIV><FONT face=Arial size=2></FONT> </DIV>
<DIV><FONT face=Arial size=2>I may have seen those wrinkles on re-balled
devices. Try spraying some wave solder flux on them and re-run through the
reflow oven. If they go away, it's most likely caused by oxides. The theory is
that the oxides formed on the surface act like a "skin" held intact via
surface tension. As the ball reflows, some of the "good solder" inside the
ball wets out to the pad surfaces and forms a fillet, thereby decreasing the
actual volume of "good solder" inside the "skin" of oxide. This behaves
somewhat like partially deflating a beach ball and the surface crinkles,
sometimes looking like it has scales.</FONT></DIV>
<DIV><FONT face=Arial size=2></FONT> </DIV>
<DIV><FONT face=Arial size=2>I have a few pics if you'd like to see what I've
experienced (or perhaps Steve might like to add them to his gallery of fame
and flame!?)</FONT></DIV>
<DIV><FONT face=Arial size=2></FONT> </DIV>
<DIV><FONT face=Arial size=2>Regards,</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2>Ed Popielarski<BR>QTA Machine<BR>10 Mc Laren, Ste
D<BR>Irvine, Ca. 92618</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2>Phone:949-581-6601<BR>Fax: 949-581-2448<BR>Cel:
949-337-2578</FONT></DIV>
<DIV> </DIV>
<DIV><FONT face=Arial size=2><A
href="http://www.QTA.NET">WWW.QTA.NET</A></FONT></DIV></BLOCKQUOTE></BODY></HTML>
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Date: Fri, 12 Apr 2002 13:32:00 +0100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Peter Barton <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Peter Barton <[log in to unmask]>
Subject: Component reclaim
Mime-Version: 1.0
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Good day Technetters,
We have a quantity of bespoke PGA packaged components that originally had
nickel/gold plated leads. The product into which this part is incorporated
has a number of other components that are de-golded and re-tinned prior to
soldering into the PCB. In their infinite wisdom an operator took it upon
themselves to include the bespoke packaged PGA's in the batch of de-golding
for this manufacturing lot.
Unfortunately the PGA part is a socketed item and must NOT be de-golded and
tin/lead dipped. I can deal with the operator - but the parts are more
problematic.
These parts, being bespoke are both rare and have a high value and long lead
time so we have a problem. Is there anyone out there who can advise if the
leads can be reclaimed i.e. stripped back to the base material and replated?
And, if it is possible does anyone have any recommendations as to who would
be able to do this on a sub-contract basis, preferably here in the UK?
FYI the original plating specification for the pins on this part is
Electroless Ni to MIL-QQ-N-290A 100-350 microinches followed by Au to
MIL-G-45204C Type 3, Grade A,
Class 1 50-225 microinches thick. The pins are Kovar and are secured into
the package through glass hermetic seals. The package itself is nickel
plated Kovar.
Any information gratefully received,
Regards,
Peter Barton
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Date: Fri, 12 Apr 2002 06:51:07 -0700
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: off topic- married spud & hand cleaner
Hans,
That site with the newlywed's jounal requires one to sign up... The next time I get the urge to sign up for marriage, I'll find a woman I hate and buy her a house!
Since we're being silly this morning, remember the "good old days" when all the WSM operators had to do to get the rosin off thier hands was walk down to the vapor degreaser?
Regards from home, too early in ther morning,
Ed Popielarski
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Date: Fri, 12 Apr 2002 09:30:14 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Munie, Gregory" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Munie, Gregory" <[log in to unmask]>
Subject: Re: Hand cleaners
X-To: Brian Ellis <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
I don't know about those fancy hand cleaners. But for general car dirt and
grease cooking oil (any kind) or baby oil work just fine for me.
You might try it on rosin and see what happens.
Re health effects: it's unlikely that the rosin itself will do anything. Any
additives could be irritating to the skin.
Greg Munie
-----Original Message-----
From: Brian Ellis [mailto:[log in to unmask]]
Sent: Thursday, April 11, 2002 9:34 AM
To: [log in to unmask]
Subject: Re: [TN] Hand cleaners
Good question, Jim. Traditionally, most people have used IPA or another
light alcohol for this, followed by a good, strong hand-detergent wash
(in the UK, there used to be a green jelly-like hand detergent which was
very good. It was called Swarfega, but I don't know whether it is still
available or whether it is exported). This is not a very good idea,
except for a VERY occasional accident. Light alcohols goes straight
through the skin like a sieve. Keep your hand in ethanol for 15 minutes
or so and see the increase in a breathalyser test! Do it with methanol
and you risk grave problems (long enough, and the grave may be the
result!). At one time, I used an industrial pink soap which was loaded
with an abrasive, possibly quartz sand. This was popular with garage
mechies as it was good at getting dirty oils and greases off. With
rosin, it worked, but it needed perserverance and a good 10 minutes. The
ladies don't like it, though, as it roughens the hands like no
washing-up liquid does. Similarly, I've sprinkled dishwasher powder onto
my wet, fairy-like mitts and this will both work but just about take the
skin off, as well.
I hesitate to recommend glycol-based products, some of which are quite
good, because the dermal uptake may be bad. However, I feel that a
terpene may be a good answer: they can dissolve rosin and the tricyclic
molecule would probably have difficulty in penetrating the skin to any
significant extent. My first try would therefore be common or garden
artists' turpentine, followed by a good hand-detergent wash. Do NOT use
one of the cheap turpentine substitutes which are based on white
spirits, though.
However, prevention is better than cure. The obvious answer is do not
get rosin on the hands. Gloves act as a preventitive, including those
chuck-away ones made of thin polyethylene. If, for any reason, these
cannot be used, then think about barrier creams (careful not to get any
on assemblies, though!). Analyse where the handling deposits rosin and
eliminate that operation - at least, in a contaminating way.
BTW, I don't think there could possibly be any health hazard associated
with rosin on the skin (normal people) but I agree that it's bloody
uncomfortable :-( After all, the sticky stuff on Band-Aids, Elastoplast,
Sparadrap and so on has a high percentage of rosin in it. Some
individuals do exhibit a cutaneous hypersensitivity reaction to rosin,
but these persons should not be working with the stuff, anyway.
You could always change to a water-soluble flux, as well :-)
Brian
Jim Jenkins wrote:
>
> Hi everyone,
>
> I know this may be a minor concern, but I get a lot of complaints from
> operators that they have nothing that will get rosin flux residue off
their
> hands. Some are very concerned about what the residue is doing to their
> health. Do any of you know of a good hand cleaner (especially one that
> comes in an industrial size dispenser) that removes rosin flux?
>
> Thanks and have fun,
>
> Jim Jenkins
>
>
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Date: Fri, 12 Apr 2002 09:53:27 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Jack C. Olson" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Jack C. Olson" <[log in to unmask]>
Subject: Re: Humorous Stories
X-To: [log in to unmask]
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
Hey Glenn, are you a mind-reader or something?
I was just telling Ronda how the only thing I
really enjoy about the conference classes is
when the instructor gets off track and starts
telling humorous stories, anecdotes, interesting
solutions (and failures) to problems, etc.
Call me a nerd, but I am fascinated by that
stuff. Phil Zarrow and Rolf Funer classes were
great for that reason alone....
So now I'm envious because I wanted to start
collecting stuff like that, and then you go and
tell everyone to reply to you privately! wha..?
So, now you got me curious,
whatcha doin' with 'em?
Jack
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Date: Thu, 11 Apr 2002 10:42:45 -0500
From: Glenn Wells <[log in to unmask]>
Subject: Humorous Stories
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Do you have any funny or humorous stories to share about anything relating
to printed circuit design, fab, assembly, test, etc.?
If you have any humorous stories to share about anything relating to
printed
circuit boards please PM them directly to me.
Please do not use any names of individuals that may have been involved in
the stories.
Glenn
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Date: Fri, 12 Apr 2002 10:24:58 -0500
Reply-To: "[log in to unmask]" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Connie Korth <[log in to unmask]>
Organization: Reptron
Subject: Copper exposed on components
Hello Tech-Netters
Does anyone know where I can find a standard that addresses copper exposed
on leads from the tinning process? If my memory serves me correctly, as
long as the area required to be soldered is tinned, it is accptable. We
build to IPC 610, Class II and one of our customers is rejecting for this.
Thanks for any input,
Connie Korth
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Date: Fri, 12 Apr 2002 10:48:32 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Don Vischulis <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Don Vischulis <[log in to unmask]>
Subject: Interesting question
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit
Techies:
I received the following email today, and it aroused my curiosity. What
reasons exist for specifying dc track resistance when minimum resistance is
governed by a combination of copper weight and design width, and track
length? Is this a case of over zealous specification or is there a purpose
behind adding another test requirement to a product with extensive
specifications?
Don Vischulis
Original message:
You may be able to help me, as I would
like to know why - in addition to specifying
impedance - an increasing number of PCB designers
and PCB fabricators are also specifying DC resistance
of PCB tracks?
I have had an increasing number of clients ask
me about series resistance being specified on
PCB tracks, but no one seems to know why..
If you are able to help with some of the reasons
why, I would very much appreciate hearing from you.
Kind regards
Martyn Gaudion
www.polarinstruments.com
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Date: Fri, 12 Apr 2002 12:31:29 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Phil Nutting <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Phil Nutting <[log in to unmask]>
Subject: Re: Interesting question
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
They may be concerned that the copper track does not add sufficient =
resistance to change the circuit function.
-----Original Message-----
From: Don Vischulis [mailto:[log in to unmask]]
Sent: Friday, April 12, 2002 11:49 AM
To: [log in to unmask]
Subject: [TN] Interesting question
Techies:
I received the following email today, and it aroused my curiosity. What
reasons exist for specifying dc track resistance when minimum resistance =
is
governed by a combination of copper weight and design width, and track
length? Is this a case of over zealous specification or is there a =
purpose
behind adding another test requirement to a product with extensive
specifications?
Don Vischulis
Original message:
You may be able to help me, as I would
like to know why - in addition to specifying
impedance - an increasing number of PCB designers
and PCB fabricators are also specifying DC resistance
of PCB tracks?
I have had an increasing number of clients ask
me about series resistance being specified on
PCB tracks, but no one seems to know why..
If you are able to help with some of the reasons
why, I would very much appreciate hearing from you.
Kind regards
Martyn Gaudion
www.polarinstruments.com
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in
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SET Technet NOMAIL
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[log in to unmask]: SET Technet Digest
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http://listserv.ipc.org/archives
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additional
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ext.5315
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Date: Fri, 12 Apr 2002 13:29:54 EDT
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Off Topic - The Married Spud & other burning questions
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="part1_115.fcfe9f6.29e87392_boundary"
--part1_115.fcfe9f6.29e87392_boundary
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
Hey All!
I finally got Hans's pictures up...had a few technical difficulties. I
couldn't save my page after I added the pics, but they're there now. Go to:
http://www.stevezeva.homestead.com
When Hans sent me the pictures, he asked if could guess what kinda car he was
in,
I'm guessing a Cadillac.
-Steve Gregory-
> Hey All,
>
> Whew! Projects pop out of the woodwork when you're going on holiday.
>
> I passed pics onto Steve - so you don't have to go to the Post Office to see
> what I look like. LOL
>
> Why am I still at work?
> We are going on a honeymoon cruise and it leaves this weekend. Eastern
> Caribbean - Puerto Rico, St. Thomas, St. Marteen, & Bahamas
>
> I'm a married spud because . . .
> A reference to Toy Story 2. Mr. Potato head keeps repeating "I'm a married
> spud." when they are in the Toy Store. If I really lose it I might start
> talking in nothing but movie quotes - product of a wasted childhood &
> hanging out with Cinema students at USC.
>
> Tech Net Advice on Marriage?
> My better half, Shannan, has been discussing our wedding plans on her list @
> http://www.ultimatewedding.com/
> Her newlywed journal is @
> http://www.weddingchat.com/showthread.php?s=&threadid=116583
>
> All right I'll bite - what advice would the list share? Off line for
> netiquette sake.
>
> Hans
>
--part1_115.fcfe9f6.29e87392_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>Hey All!
<BR>
<BR>I finally got Hans's pictures up...had a few technical difficulties. I couldn't save my page after I added the pics, but they're there now. Go to:
<BR>
<BR>http://www.stevezeva.homestead.com
<BR>
<BR>When Hans sent me the pictures, he asked if could guess what kinda car he was in,
<BR>I'm guessing a Cadillac.
<BR>
<BR>-Steve Gregory-
<BR>
<BR>
<BR><BLOCKQUOTE TYPE=CITE style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">Hey All,
<BR>
<BR>Whew! Projects pop out of the woodwork when you're going on holiday.
<BR>
<BR>I passed pics onto Steve - so you don't have to go to the Post Office to see
<BR>what I look like. LOL
<BR>
<BR>Why am I still at work?
<BR>We are going on a honeymoon cruise and it leaves this weekend. Eastern
<BR>Caribbean - Puerto Rico, St. Thomas, St. Marteen, & Bahamas
<BR>
<BR>I'm a married spud because . . .
<BR>A reference to Toy Story 2. Mr. Potato head keeps repeating "I'm a married
<BR>spud." when they are in the Toy Store. If I really lose it I might start
<BR>talking in nothing but movie quotes - product of a wasted childhood &
<BR>hanging out with Cinema students at USC.
<BR>
<BR>Tech Net Advice on Marriage?
<BR>My better half, Shannan, has been discussing our wedding plans on her list @
<BR>http://www.ultimatewedding.com/
<BR>Her newlywed journal is @
<BR>http://www.weddingchat.com/showthread.php?s=&threadid=116583
<BR>
<BR>All right I'll bite - what advice would the list share? Off line for
<BR>netiquette sake.
<BR>
<BR>Hans
<BR></FONT><FONT COLOR="#000000" SIZE=3 FAMILY="SANSSERIF" FACE="Arial" LANG="0"></BLOCKQUOTE>
<BR></FONT><FONT COLOR="#000000" SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0">
<BR></FONT></HTML>
--part1_115.fcfe9f6.29e87392_boundary--
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=========================================================================
Date: Fri, 12 Apr 2002 13:30:15 -0400
Reply-To: "Valerie St. Cyr - Sun USOPS New Products"
<[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Valerie St. Cyr - Sun USOPS New Products"
<[log in to unmask]>
Subject: Re: Interesting question
X-To: [log in to unmask]
MIME-Version: 1.0
Content-Type: TEXT/plain; charset=us-ascii
While not an EE, my understanding is for the following:
devices have faster edge rates, high resistance traces
can hang a device.
while impedance may in fact be as specified, it can be
achieved by etch width reductions beyond what is allowable
also, and probably most important, trace resistance can
be increased locally by nicks, dishdowns, local reductions
(like to get past a too-close pad), fine fractures in
the copper trace from handling.....
there in fact may be other reasons, these are the ones
I know about ...
Valerie
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Date: Fri, 12 Apr 2002 10:48:32 -0500
From: Don Vischulis <[log in to unmask]>
Subject: [TN] Interesting question
To: [log in to unmask]
Techies:
I received the following email today, and it aroused my curiosity. What
reasons exist for specifying dc track resistance when minimum resistance is
governed by a combination of copper weight and design width, and track
length? Is this a case of over zealous specification or is there a purpose
behind adding another test requirement to a product with extensive
specifications?
Don Vischulis
Original message:
You may be able to help me, as I would
like to know why - in addition to specifying
impedance - an increasing number of PCB designers
and PCB fabricators are also specifying DC resistance
of PCB tracks?
I have had an increasing number of clients ask
me about series resistance being specified on
PCB tracks, but no one seems to know why..
If you are able to help with some of the reasons
why, I would very much appreciate hearing from you.
Kind regards
Martyn Gaudion
www.polarinstruments.com
--------------------------------------------------------------------------------
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Date: Fri, 12 Apr 2002 13:49:13 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Joseph Spicuzza <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Joseph Spicuzza <[log in to unmask]>
Subject: Re: Interesting question
X-To: Don Vischulis <[log in to unmask]>
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
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For what it's worth... here was my reply...
Hi Marty,
I think this would be critical especially if the circuit board is large.
Resistance is only a DC phenomenon, with AC it's impedance. I'm thinking
that if the board has controlled impedance and long runs with fairly small
traces the resistance might throw off the impedance reading. They are
probably looking for a constant to subtract from the impedance. Did that
make any sense?
Feel free to contact me. We design circuit boards as well as build some of
the latest designs and I may be able to tap into our collective experience
here.
Joseph Spicuzza
Quality Assurance Manager
Advanced Interconnect Products Division
Compunetics, Inc.
PH: 412 858-6166
FX: 412 373-8060
[log in to unmask]
-----Original Message-----
From: Martyn Gaudion [mailto:[log in to unmask]]
Sent: Friday, April 12, 2002 6:25 AM
To: [log in to unmask]
Subject: DC Track resistance - can you help me?
Dear Joseph,
You may be able to help me, as I would
like to know why - in addition to specifying
impedance - an increasing number of PCB designers
and PCB fabricators are also specifying DC resistance
of PCB tracks?
I have had an increasing number of clients ask
me about series resistance being specified on
PCB tracks, but no one seems to know why..
If you are able to help with some of the reasons
why, I would very much appreciate hearing from you.
Kind regards
Martyn Gaudion
www.polarinstruments.com
P.S. If you know a colleage or customer who may be
able to add more information, it would be much appreciated if you
could put me in touch..
Remove me:
If you would like to be removed from this list, please email:
[log in to unmask]
with Remove Si in the subject line.
Privacy policy:
www.polarinstruments.com/support/privacy.html
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Don Vischulis
Sent: Friday, April 12, 2002 11:49 AM
To: [log in to unmask]
Subject: [TN] Interesting question
Techies:
I received the following email today, and it aroused my curiosity. What
reasons exist for specifying dc track resistance when minimum resistance is
governed by a combination of copper weight and design width, and track
length? Is this a case of over zealous specification or is there a purpose
behind adding another test requirement to a product with extensive
specifications?
Don Vischulis
Original message:
You may be able to help me, as I would
like to know why - in addition to specifying
impedance - an increasing number of PCB designers
and PCB fabricators are also specifying DC resistance
of PCB tracks?
I have had an increasing number of clients ask
me about series resistance being specified on
PCB tracks, but no one seems to know why..
If you are able to help with some of the reasons
why, I would very much appreciate hearing from you.
Kind regards
Martyn Gaudion
www.polarinstruments.com
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Date: Fri, 12 Apr 2002 14:32:33 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Michael Khusid <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Michael Khusid <[log in to unmask]>
Subject: Re: Interesting question
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
I think the larger problem is the too much variation in track width which
will affect not only "regular" bulk resistance, but also high frequency
resistance of the track. The latter effect is known as skin effect.
Mike Khusid
> -----Original Message-----
> From: Phil Nutting [mailto:[log in to unmask]]
> Sent: Friday, April 12, 2002 12:31 PM
> To: [log in to unmask]
> Subject: Re: [TN] Interesting question
>
>
> They may be concerned that the copper track does not add
> sufficient resistance to change the circuit function.
>
> -----Original Message-----
> From: Don Vischulis [mailto:[log in to unmask]]
> Sent: Friday, April 12, 2002 11:49 AM
> To: [log in to unmask]
> Subject: [TN] Interesting question
>
>
> Techies:
>
> I received the following email today, and it aroused my
> curiosity. What
> reasons exist for specifying dc track resistance when minimum
> resistance is
> governed by a combination of copper weight and design width, and track
> length? Is this a case of over zealous specification or is
> there a purpose
> behind adding another test requirement to a product with extensive
> specifications?
>
> Don Vischulis
>
> Original message:
> You may be able to help me, as I would
> like to know why - in addition to specifying
> impedance - an increasing number of PCB designers
> and PCB fabricators are also specifying DC resistance
> of PCB tracks?
>
> I have had an increasing number of clients ask
> me about series resistance being specified on
> PCB tracks, but no one seems to know why..
>
> If you are able to help with some of the reasons
> why, I would very much appreciate hearing from you.
>
>
> Kind regards
> Martyn Gaudion
> www.polarinstruments.com
>
> --------------------------------------------------------------
> -------------------
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Date: Fri, 12 Apr 2002 19:46:32 +0100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Hinners Hans M Civ WRALC/LUGE <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Hinners Hans M Civ WRALC/LUGE <[log in to unmask]>
Subject: Re: Off Topic - The Married Spud & other burning questions
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This message is in MIME format. Since your mail reader does not understand
this format, some or all of this message may not be legible.
------=_NextPartTM-000-2d59173c-4e45-11d6-b575-00508bf7d80d
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boundary="----_=_NextPart_001_01C1E252.5D8A60B0"
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charset="iso-8859-1"
And you'd be wrong. It ain't a caddy but close.
-----Original Message-----
From: [log in to unmask] [mailto:[log in to unmask]]
Sent: Friday, April 12, 2002 1:30 PM
To: [log in to unmask]
Subject: Re: [TN] Off Topic - The Married Spud & other burning questions
Hey All!
I finally got Hans's pictures up...had a few technical difficulties. I
couldn't save my page after I added the pics, but they're there now. Go to:
http://www.stevezeva.homestead.com
When Hans sent me the pictures, he asked if could guess what kinda car he
was in,
I'm guessing a Cadillac.
-Steve Gregory-
Hey All,
Whew! Projects pop out of the woodwork when you're going on holiday.
I passed pics onto Steve - so you don't have to go to the Post Office to see
what I look like. LOL
Why am I still at work?
We are going on a honeymoon cruise and it leaves this weekend. Eastern
Caribbean - Puerto Rico, St. Thomas, St. Marteen, & Bahamas
I'm a married spud because . . .
A reference to Toy Story 2. Mr. Potato head keeps repeating "I'm a married
spud." when they are in the Toy Store. If I really lose it I might start
talking in nothing but movie quotes - product of a wasted childhood &
hanging out with Cinema students at USC.
Tech Net Advice on Marriage?
My better half, Shannan, has been discussing our wedding plans on her list @
http://www.ultimatewedding.com/
Her newlywed journal is @
http://www.weddingchat.com/showthread.php?s=&threadid=116583
All right I'll bite - what advice would the list share? Off line for
netiquette sake.
Hans
------_=_NextPart_001_01C1E252.5D8A60B0
Content-Type: text/html;
charset="iso-8859-1"
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=iso-8859-1">
<META content="MSHTML 6.00.2712.300" name=GENERATOR></HEAD>
<BODY>
<DIV><SPAN class=944564518-12042002><FONT color=#0000ff>And you'd be
wrong. It ain't a caddy but close.</FONT></SPAN></DIV>
<BLOCKQUOTE>
<DIV class=OutlookMessageHeader dir=ltr align=left><FONT face=Tahoma
size=2>-----Original Message-----<BR><B>From:</B> [log in to unmask]
[mailto:[log in to unmask]]<BR><B>Sent:</B> Friday, April 12, 2002 1:30
PM<BR><B>To:</B> [log in to unmask]<BR><B>Subject:</B> Re: [TN] Off Topic - The
Married Spud & other burning questions<BR><BR></FONT></DIV><FONT
face=arial,helvetica><FONT size=2>Hey All! <BR><BR>I finally got Hans's
pictures up...had a few technical difficulties. I couldn't save my page after
I added the pics, but they're there now. Go to:
<BR><BR>http://www.stevezeva.homestead.com <BR><BR>When Hans sent me the
pictures, he asked if could guess what kinda car he was in, <BR>I'm guessing a
Cadillac. <BR><BR>-Steve Gregory- <BR><BR><BR>
<BLOCKQUOTE
style="PADDING-LEFT: 5px; MARGIN-LEFT: 5px; BORDER-LEFT: #0000ff 2px solid; MARGIN-RIGHT: 0px"
TYPE="CITE">Hey All, <BR><BR>Whew! Projects pop out of the woodwork
when you're going on holiday. <BR><BR>I passed pics onto Steve - so you
don't have to go to the Post Office to see <BR>what I look like. LOL
<BR><BR>Why am I still at work? <BR>We are going on a honeymoon cruise and
it leaves this weekend. Eastern <BR>Caribbean - Puerto Rico, St.
Thomas, St. Marteen, & Bahamas <BR><BR>I'm a married spud because . . .
<BR>A reference to Toy Story 2. Mr. Potato head keeps repeating "I'm a
married <BR>spud." when they are in the Toy Store. If I really lose it
I might start <BR>talking in nothing but movie quotes - product of a wasted
childhood & <BR>hanging out with Cinema students at USC. <BR><BR>Tech
Net Advice on Marriage? <BR>My better half, Shannan, has been discussing our
wedding plans on her list @ <BR>http://www.ultimatewedding.com/ <BR>Her
newlywed journal is @
<BR>http://www.weddingchat.com/showthread.php?s=&threadid=116583
<BR><BR>All right I'll bite - what advice would the list share? Off
line for <BR>netiquette sake. <BR><BR>Hans <BR></FONT><FONT lang=0
face=Arial color=#000000 size=3
FAMILY="SANSSERIF"></BLOCKQUOTE><BR></FONT><FONT lang=0 face=Arial
color=#000000 size=2
FAMILY="SANSSERIF"><BR></BLOCKQUOTE></FONT></FONT></BODY></HTML>
------_=_NextPart_001_01C1E252.5D8A60B0--
------=_NextPartTM-000-2d59173c-4e45-11d6-b575-00508bf7d80d--
---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
=========================================================================
Date: Fri, 12 Apr 2002 15:18:40 EDT
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Werner Engelmaier <[log in to unmask]>
Subject: Re: Interesting question
MIME-Version: 1.0
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
Hi Don,
One reason has not been mentioned yet--unlike rolled copper, plated copper
does not have a fixed resisitivity.
Werner Engelmaier
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Date: Fri, 12 Apr 2002 15:22:13 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Phil Nutting <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Phil Nutting <[log in to unmask]>
Subject: Re: Off Topic - The Married Spud & other burning questions
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="----_=_NextPart_001_01C1E257.598E7528"
This is a multi-part message in MIME format.
------_=_NextPart_001_01C1E257.598E7528
Content-Type: text/plain;
charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
DeSoto
-----Original Message-----
From: Hinners Hans M Civ WRALC/LUGE [mailto:[log in to unmask]]
Sent: Friday, April 12, 2002 2:47 PM
To: [log in to unmask]
Subject: Re: [TN] Off Topic - The Married Spud & other burning questions
And you'd be wrong. It ain't a caddy but close.
-----Original Message-----
From: [log in to unmask] [mailto:[log in to unmask]]
Sent: Friday, April 12, 2002 1:30 PM
To: [log in to unmask]
Subject: Re: [TN] Off Topic - The Married Spud & other burning questions
Hey All!=20
I finally got Hans's pictures up...had a few technical difficulties. I =
couldn't save my page after I added the pics, but they're there now. Go =
to:=20
http://www.stevezeva.homestead.com=20
When Hans sent me the pictures, he asked if could guess what kinda car =
he was in,=20
I'm guessing a Cadillac.=20
-Steve Gregory-=20
Hey All,=20
Whew! Projects pop out of the woodwork when you're going on holiday.=20
I passed pics onto Steve - so you don't have to go to the Post Office to =
see=20
what I look like. LOL=20
Why am I still at work?=20
We are going on a honeymoon cruise and it leaves this weekend. Eastern=20
Caribbean - Puerto Rico, St. Thomas, St. Marteen, & Bahamas=20
I'm a married spud because . . .=20
A reference to Toy Story 2. Mr. Potato head keeps repeating "I'm a =
married=20
spud." when they are in the Toy Store. If I really lose it I might =
start=20
talking in nothing but movie quotes - product of a wasted childhood &=20
hanging out with Cinema students at USC.=20
Tech Net Advice on Marriage?=20
My better half, Shannan, has been discussing our wedding plans on her =
list @=20
http://www.ultimatewedding.com/=20
Her newlywed journal is @=20
http://www.weddingchat.com/showthread.php?s=3D&threadid=3D116583=20
All right I'll bite - what advice would the list share? Off line for=20
netiquette sake.=20
Hans=20
------_=_NextPart_001_01C1E257.598E7528
Content-Type: text/html;
charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META HTTP-EQUIV=3D"Content-Type" CONTENT=3D"text/html; =
charset=3Diso-8859-1">
<META content=3D"MSHTML 6.00.2712.300" name=3DGENERATOR></HEAD>
<BODY>
<DIV><SPAN class=3D908062219-12042002><FONT face=3DArial color=3D#0000ff =
size=3D2>DeSoto</FONT></SPAN></DIV>
<BLOCKQUOTE dir=3Dltr style=3D"MARGIN-RIGHT: 0px">
<DIV class=3DOutlookMessageHeader dir=3Dltr align=3Dleft><FONT =
face=3DTahoma=20
size=3D2>-----Original Message-----<BR><B>From:</B> Hinners Hans M Civ =
WRALC/LUGE [mailto:[log in to unmask]]<BR><B>Sent:</B> Friday, =
April=20
12, 2002 2:47 PM<BR><B>To:</B> [log in to unmask]<BR><B>Subject:</B> Re: =
[TN] Off=20
Topic - The Married Spud & other burning =
questions<BR><BR></FONT></DIV>
<DIV><SPAN class=3D944564518-12042002><FONT color=3D#0000ff>And you'd =
be=20
wrong. It ain't a caddy but close.</FONT></SPAN></DIV>
<BLOCKQUOTE>
<DIV class=3DOutlookMessageHeader dir=3Dltr align=3Dleft><FONT =
face=3DTahoma=20
size=3D2>-----Original Message-----<BR><B>From:</B> =
[log in to unmask]
[mailto:[log in to unmask]]<BR><B>Sent:</B> Friday, April 12, 2002 =
1:30=20
PM<BR><B>To:</B> [log in to unmask]<BR><B>Subject:</B> Re: [TN] Off =
Topic - The=20
Married Spud & other burning questions<BR><BR></FONT></DIV><FONT =
face=3Darial,helvetica><FONT size=3D2>Hey All! <BR><BR>I finally got =
Hans's=20
pictures up...had a few technical difficulties. I couldn't save my =
page=20
after I added the pics, but they're there now. Go to:=20
<BR><BR>http://www.stevezeva.homestead.com <BR><BR>When Hans sent me =
the=20
pictures, he asked if could guess what kinda car he was in, <BR>I'm =
guessing=20
a Cadillac. <BR><BR>-Steve Gregory- <BR><BR><BR>
<BLOCKQUOTE=20
style=3D"PADDING-LEFT: 5px; MARGIN-LEFT: 5px; BORDER-LEFT: #0000ff =
2px solid; MARGIN-RIGHT: 0px"=20
TYPE=3D"CITE">Hey All, <BR><BR>Whew! Projects pop out of the =
woodwork=20
when you're going on holiday. <BR><BR>I passed pics onto Steve - =
so you=20
don't have to go to the Post Office to see <BR>what I look like. =
LOL=20
<BR><BR>Why am I still at work? <BR>We are going on a honeymoon =
cruise and=20
it leaves this weekend. Eastern <BR>Caribbean - Puerto Rico, =
St.=20
Thomas, St. Marteen, & Bahamas <BR><BR>I'm a married spud =
because . .=20
. <BR>A reference to Toy Story 2. Mr. Potato head keeps =
repeating=20
"I'm a married <BR>spud." when they are in the Toy Store. If =
I=20
really lose it I might start <BR>talking in nothing but movie =
quotes -=20
product of a wasted childhood & <BR>hanging out with Cinema =
students=20
at USC. <BR><BR>Tech Net Advice on Marriage? <BR>My better half, =
Shannan,=20
has been discussing our wedding plans on her list @=20
<BR>http://www.ultimatewedding.com/ <BR>Her newlywed journal is @=20
=
<BR>http://www.weddingchat.com/showthread.php?s=3D&threadid=3D116583 =
<BR><BR>All right I'll bite - what advice would the list share? =
Off=20
line for <BR>netiquette sake. <BR><BR>Hans <BR></FONT><FONT =
lang=3D0=20
face=3DArial color=3D#000000 size=3D3=20
FAMILY=3D"SANSSERIF"></BLOCKQUOTE><BR></FONT><FONT lang=3D0 =
face=3DArial=20
color=3D#000000 size=3D2=20
FAMILY=3D"SANSSERIF"><BR></BLOCKQUOTE></BLOCKQUOTE></FONT></FONT></BODY><=
/HTML>
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Date: Fri, 12 Apr 2002 13:31:51 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Genny Gibbard <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Genny Gibbard <[log in to unmask]>
Subject: Re: Interesting question
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
I think Valerie had the best answer, so far:
also, and probably most important, trace resistance can
be increased locally by nicks, dishdowns, local reductions
(like to get past a too-close pad), fine fractures in
the copper trace from handling.....
With lighter copper weights becoming standard (1 oz is the standard we spec
for our boards, but I hear that is now heavy, and 1/2 oz is standard), nicks
and scratches are most likely the biggest concern, or too narrow traces.
Especially if any significant DC power is running thru those traces. You
might develop hot spots in the board.
-----Original Message-----
From: Don Vischulis [mailto:[log in to unmask]]
Sent: April 12, 2002 9:49 AM
To: [log in to unmask]
Subject: [TN] Interesting question
Techies:
I received the following email today, and it aroused my curiosity. What
reasons exist for specifying dc track resistance when minimum resistance is
governed by a combination of copper weight and design width, and track
length? Is this a case of over zealous specification or is there a purpose
behind adding another test requirement to a product with extensive
specifications?
Don Vischulis
Original message:
You may be able to help me, as I would
like to know why - in addition to specifying
impedance - an increasing number of PCB designers
and PCB fabricators are also specifying DC resistance
of PCB tracks?
I have had an increasing number of clients ask
me about series resistance being specified on
PCB tracks, but no one seems to know why..
If you are able to help with some of the reasons
why, I would very much appreciate hearing from you.
Kind regards
Martyn Gaudion
www.polarinstruments.com
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Date: Fri, 12 Apr 2002 16:34:20 -0400
Reply-To: "[log in to unmask]" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Lou Hart <[log in to unmask]>
Organization: Compunetix, Inc.
Subject: Re: Interesting question
Depending on the length of the trace and the tolerance on trace resistance,
a local trace width or thickness anomaly may or may not affect
acceptability of resistance. Trace anomalies will affect characteristic
impedance measurements. Characteristic impedance depends on spacing
between conductors, however they may be configured to achieve that
characteristic impedance, and the intervening dielectric(s), the properties
of which themselves vary with frequency. I could speculate that someone is
sending a constant current down the line along with an information-carrying
signal. By the way, I had occasion to talk with a fellow from Carnegie
Mellon University a few weeks ago, who is working on a project to use air
conditioning ducts as transmission lines, to avoid rewiring buildings for
networks. Lou Hart
-----Original Message-----
From: Genny Gibbard [SMTP:[log in to unmask]]
Sent: Friday, April 12, 2002 3:32 PM
To: [log in to unmask]
Subject: Re: [TN] Interesting question
I think Valerie had the best answer, so far:
also, and probably most important, trace resistance can
be increased locally by nicks, dishdowns, local reductions
(like to get past a too-close pad), fine fractures in
the copper trace from handling.....
With lighter copper weights becoming standard (1 oz is the standard we spec
for our boards, but I hear that is now heavy, and 1/2 oz is standard),
nicks
and scratches are most likely the biggest concern, or too narrow traces.
Especially if any significant DC power is running thru those traces. You
might develop hot spots in the board.
-----Original Message-----
From: Don Vischulis [mailto:[log in to unmask]]
Sent: April 12, 2002 9:49 AM
To: [log in to unmask]
Subject: [TN] Interesting question
Techies:
I received the following email today, and it aroused my curiosity. What
reasons exist for specifying dc track resistance when minimum resistance is
governed by a combination of copper weight and design width, and track
length? Is this a case of over zealous specification or is there a purpose
behind adding another test requirement to a product with extensive
specifications?
Don Vischulis
Original message:
You may be able to help me, as I would
like to know why - in addition to specifying
impedance - an increasing number of PCB designers
and PCB fabricators are also specifying DC resistance
of PCB tracks?
I have had an increasing number of clients ask
me about series resistance being specified on
PCB tracks, but no one seems to know why..
If you are able to help with some of the reasons
why, I would very much appreciate hearing from you.
Kind regards
Martyn Gaudion
www.polarinstruments.com
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Date: Fri, 12 Apr 2002 16:46:14 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Rob Legg <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Rob Legg <[log in to unmask]>
Subject: Re: Interesting question
X-To: Don Vischulis <[log in to unmask]>
MIME-Version: 1.0
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They may be using the track resistance as a low cost current sensing
element, in which case, ensuring that it meets intended tolerances only
makes sense.
A large fall-out tells the designers that they've got a problem that may
need attention - especially if it does have cost implications. Let them know
it.
Rob Legg
[log in to unmask]
----- Original Message -----
From: "Don Vischulis" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Friday, April 12, 2002 11:48 AM
Subject: [TN] Interesting question
> Techies:
>
> I received the following email today, and it aroused my curiosity. What
> reasons exist for specifying dc track resistance when minimum resistance
is
> governed by a combination of copper weight and design width, and track
> length? Is this a case of over zealous specification or is there a
purpose
> behind adding another test requirement to a product with extensive
> specifications?
>
> Don Vischulis
>
> Original message:
> You may be able to help me, as I would
> like to know why - in addition to specifying
> impedance - an increasing number of PCB designers
> and PCB fabricators are also specifying DC resistance
> of PCB tracks?
>
> I have had an increasing number of clients ask
> me about series resistance being specified on
> PCB tracks, but no one seems to know why..
>
> If you are able to help with some of the reasons
> why, I would very much appreciate hearing from you.
>
>
> Kind regards
> Martyn Gaudion
> www.polarinstruments.com
>
> --------------------------------------------------------------------------
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Date: Fri, 12 Apr 2002 14:10:17 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
JaMi Smith <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: JaMi Smith <[log in to unmask]>
Subject: Re: Off Topic - The Married Spud & other burning questions
MIME-Version: 1.0
Content-Type: text/plain; charset="us-ascii"
Content-Transfer-Encoding: quoted-printable
My first guess would be Packard, and the second would be Kaiser.
=20
=20
-----Original Message-----
From: Phil Nutting [mailto:[log in to unmask]]=20
Sent: Friday, April 12, 2002 12:22 PM
To: [log in to unmask]
Subject: Re: [TN] Off Topic - The Married Spud & other burning questions
=20
DeSoto
-----Original Message-----
From: Hinners Hans M Civ WRALC/LUGE
[mailto:[log in to unmask]]
Sent: Friday, April 12, 2002 2:47 PM
To: [log in to unmask]
Subject: Re: [TN] Off Topic - The Married Spud & other burning
questions
And you'd be wrong. It ain't a caddy but close.
-----Original Message-----
From: [log in to unmask] [mailto:[log in to unmask]]
Sent: Friday, April 12, 2002 1:30 PM
To: [log in to unmask]
Subject: Re: [TN] Off Topic - The Married Spud & other
burning questions
Hey All!=20
=09
I finally got Hans's pictures up...had a few technical
difficulties. I couldn't save my page after I added the pics, but
they're there now. Go to:=20
=09
http://www.stevezeva.homestead.com=20
=09
When Hans sent me the pictures, he asked if could guess
what kinda car he was in,=20
I'm guessing a Cadillac.=20
=09
-Steve Gregory-=20
=09
=09
=09
=09
Hey All,=20
=09
Whew! Projects pop out of the woodwork when you're
going on holiday.=20
=09
I passed pics onto Steve - so you don't have to go to
the Post Office to see=20
what I look like. LOL=20
=09
Why am I still at work?=20
We are going on a honeymoon cruise and it leaves this
weekend. Eastern=20
Caribbean - Puerto Rico, St. Thomas, St. Marteen, &
Bahamas=20
=09
I'm a married spud because . . .=20
A reference to Toy Story 2. Mr. Potato head keeps
repeating "I'm a married=20
spud." when they are in the Toy Store. If I really lose
it I might start=20
talking in nothing but movie quotes - product of a
wasted childhood &=20
hanging out with Cinema students at USC.=20
=09
Tech Net Advice on Marriage?=20
My better half, Shannan, has been discussing our wedding
plans on her list @=20
http://www.ultimatewedding.com/=20
Her newlywed journal is @=20
=09
http://www.weddingchat.com/showthread.php?s=3D&threadid=3D116583=20
=09
All right I'll bite - what advice would the list share?
Off line for=20
netiquette sake.=20
=09
Hans=20
=09
=09
=09
=09
=09
---------------------------------------------------------------------------------
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=========================================================================
Date: Fri, 12 Apr 2002 21:44:14 EDT
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Off Topic - The Married Spud & other burning questions
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="part1_2f.25a1f46b.29e8e76e_boundary"
--part1_2f.25a1f46b.29e8e76e_boundary
Content-Type: text/plain; charset="US-ASCII"
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Something about the chrome trim (arrowheads, and the indian head) seem to
point to Pontiac...but have not found a model that has that trim yet...is it
a Pontiac?
-Steve Gregory-
> And you'd be wrong. It ain't a caddy but close.
>
> >> -----Original Message-----
>> From: [log in to unmask] [mailto:[log in to unmask]]
>> Sent: Friday, April 12, 2002 1:30 PM
>> To: [log in to unmask]
>> Subject: Re: [TN] Off Topic - The Married Spud & other burning questions
>>
>>
>> Hey All!
>>
>> I finally got Hans's pictures up...had a few technical difficulties. I
>> couldn't save my page after I added the pics, but they're there now. Go
>> to:
>>
>> http://www.stevezeva.homestead.com
>>
>> When Hans sent me the pictures, he asked if could guess what kinda car he
>> was in,
>> I'm guessing a Cadillac.
>>
>> -Steve Gregory-
>>
>>
>> >>> Hey All,
>>>
>>> Whew! Projects pop out of the woodwork when you're going on holiday.
>>>
>>> I passed pics onto Steve - so you don't have to go to the Post Office to
>>> see
>>> what I look like. LOL
>>>
>>> Why am I still at work?
>>> We are going on a honeymoon cruise and it leaves this weekend. Eastern
>>> Caribbean - Puerto Rico, St. Thomas, St. Marteen, & Bahamas
>>>
>>> I'm a married spud because . . .
>>> A reference to Toy Story 2. Mr. Potato head keeps repeating "I'm a
>>> married
>>> spud." when they are in the Toy Store. If I really lose it I might start
>>>
>>> talking in nothing but movie quotes - product of a wasted childhood &
>>> hanging out with Cinema students at USC.
>>>
>>> Tech Net Advice on Marriage?
>>> My better half, Shannan, has been discussing our wedding plans on her
>>> list @
>>> http://www.ultimatewedding.com/
>>> Her newlywed journal is @
>>> http://www.weddingchat.com/showthread.php?s=&threadid=116583
>>>
>>> All right I'll bite - what advice would the list share? Off line for
>>> netiquette sake.
>>>
>>> Hans
>>>
>>
>
--part1_2f.25a1f46b.29e8e76e_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
<HTML><FONT FACE=arial,helvetica><FONT SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0">Something about the chrome trim (arrowheads, and the indian head) seem to point to Pontiac...but have not found a model that has that trim yet...is it a Pontiac?<BR>
<BR>
-Steve Gregory-<BR>
<BR>
<BR>
</FONT><FONT COLOR="#0000ff" style="BACKGROUND-COLOR: #ffffff" SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0"><BLOCKQUOTE TYPE=CITE style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">And you'd be wrong. It ain't a caddy but close.</FONT><FONT COLOR="#000000" style="BACKGROUND-COLOR: #ffffff" SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0"><BR>
<BR>
</FONT><FONT COLOR="#000000" style="BACKGROUND-COLOR: #ffffff" SIZE=2 FAMILY="SANSSERIF" FACE="Tahoma" LANG="0"><BLOCKQUOTE TYPE=CITE style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">-----Original Message-----<BR>
<B>From:</B> [log in to unmask] [mailto:[log in to unmask]]<BR>
<B>Sent:</B> Friday, April 12, 2002 1:30 PM<BR>
<B>To:</B> [log in to unmask]<BR>
<B>Subject:</B> Re: [TN] Off Topic - The Married Spud & other burning questions<BR>
<BR>
</FONT><FONT COLOR="#000000" style="BACKGROUND-COLOR: #ffffff" SIZE=3 FAMILY="SANSSERIF" FACE="Tahoma" LANG="0"><BR>
</FONT><FONT COLOR="#000000" style="BACKGROUND-COLOR: #ffffff" SIZE=2 FAMILY="SANSSERIF" FACE="arial" LANG="0">Hey All! <BR>
<BR>
I finally got Hans's pictures up...had a few technical difficulties. I couldn't save my page after I added the pics, but they're there now. Go to: <BR>
<BR>
http://www.stevezeva.homestead.com <BR>
<BR>
When Hans sent me the pictures, he asked if could guess what kinda car he was in, <BR>
I'm guessing a Cadillac. <BR>
<BR>
-Steve Gregory- <BR>
<BR>
<BR>
<BLOCKQUOTE TYPE=CITE style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">Hey All, <BR>
<BR>
Whew! Projects pop out of the woodwork when you're going on holiday. <BR>
<BR>
I passed pics onto Steve - so you don't have to go to the Post Office to see <BR>
what I look like. LOL <BR>
<BR>
Why am I still at work? <BR>
We are going on a honeymoon cruise and it leaves this weekend. Eastern <BR>
Caribbean - Puerto Rico, St. Thomas, St. Marteen, & Bahamas <BR>
<BR>
I'm a married spud because . . . <BR>
A reference to Toy Story 2. Mr. Potato head keeps repeating "I'm a married <BR>
spud." when they are in the Toy Store. If I really lose it I might start <BR>
talking in nothing but movie quotes - product of a wasted childhood & <BR>
hanging out with Cinema students at USC. <BR>
<BR>
Tech Net Advice on Marriage? <BR>
My better half, Shannan, has been discussing our wedding plans on her list @ <BR>
http://www.ultimatewedding.com/ <BR>
Her newlywed journal is @ <BR>
http://www.weddingchat.com/showthread.php?s=&threadid=116583 <BR>
<BR>
All right I'll bite - what advice would the list share? Off line for <BR>
netiquette sake. <BR>
<BR>
Hans <BR>
</BLOCKQUOTE><BR>
</FONT><FONT COLOR="#000000" style="BACKGROUND-COLOR: #ffffff" SIZE=3 FAMILY="SANSSERIF" FACE="Arial" LANG="0"></BLOCKQUOTE><BR>
</BLOCKQUOTE><BR>
<BR>
</FONT></HTML>
--part1_2f.25a1f46b.29e8e76e_boundary--
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=========================================================================
Date: Sat, 13 Apr 2002 09:05:34 +0300
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Brian Ellis <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Brian Ellis <[log in to unmask]>
Subject: Re: Interesting question
X-To: Don Vischulis <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
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Don
I received the same question and I replied as follows:
Martyn
I think there may be four reasons:
1. (probably the most prevalent) the specifiers don't have a clue
2. it is an easy way of ensuring and measuring that the copper thickness
on the board is adequate for the purpose (PCB fab guys are not skimping
on the plating thickness). At the same time, it would help to ensure the
correct Zo
3. maybe for DC reasons with lo-Z power circuitry
4. as you are better aware than I, L/C ratio, defining the Zo, ensures a
clean signal arriving at the load resistance and power is not
particularly significant for, say, high-speed switching. However, if the
load resistance is replaced by a, say, 1/4-wave antenna, giving a
non-reactive load resistance of c. 50 ohms, or a 1/2 wave dipole and c.
72 ohms, any distributed R in the feeder will reduce the power that
could effectively radiate from the antenna.
Personally, I doubt whether any of these would have any significant
effect, in practice, for transmission lines of less than, say, 30 cm,
provided there was no undue reflection anywhere. Interestingly, a high
distributed resistance would probably have a better damping effect in
cases of gross mismatch (e.g. Rload open-circuit), but the values we are
looking at are not significant.
FYI, the Vutrax CAD software (and possibly others) has had R calculation
features for any track or part thereof, for many years. It may be that,
because such a feature exists, users are finding supposed reasons for it
being there and are bugging everyone unnecessarily as a result.
Just some thoughts...
Brian
Don Vischulis wrote:
>
> Techies:
>
> I received the following email today, and it aroused my curiosity. What
> reasons exist for specifying dc track resistance when minimum resistance is
> governed by a combination of copper weight and design width, and track
> length? Is this a case of over zealous specification or is there a purpose
> behind adding another test requirement to a product with extensive
> specifications?
>
> Don Vischulis
>
> Original message:
> You may be able to help me, as I would
> like to know why - in addition to specifying
> impedance - an increasing number of PCB designers
> and PCB fabricators are also specifying DC resistance
> of PCB tracks?
>
> I have had an increasing number of clients ask
> me about series resistance being specified on
> PCB tracks, but no one seems to know why..
>
> If you are able to help with some of the reasons
> why, I would very much appreciate hearing from you.
>
> Kind regards
> Martyn Gaudion
> www.polarinstruments.com
>
> ---------------------------------------------------------------------------------
> Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
> To unsubscribe, send a message to [log in to unmask] with following text in
> the BODY (NOT the subject field): SIGNOFF Technet
> To temporarily halt delivery of Technet send e-mail to [log in to unmask]: SET Technet NOMAIL
> To receive ONE mailing per day of all the posts: send e-mail to [log in to unmask]: SET Technet Digest
> Search the archives of previous posts at: http://listserv.ipc.org/archives
> Please visit IPC web site http://www.ipc.org/html/forum.htm for additional
> information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700 ext.5315
> ---------------------------------------------------------------------------------
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=========================================================================
Date: Sat, 13 Apr 2002 15:36:00 +0100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Hinners Hans M Civ WRALC/LUGE <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Hinners Hans M Civ WRALC/LUGE <[log in to unmask]>
Subject: Re: Off Topic - The Married Spud & other burning questions
X-To: JaMi Smith <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Jami wins the virtual brownies!
It's a '53 Packard.
Hans
-----Original Message-----
From: JaMi Smith [mailto:[log in to unmask]]
Sent: Friday, April 12, 2002 5:10 PM
To: [log in to unmask]
Subject: Re: [TN] Off Topic - The Married Spud & other burning questions
My first guess would be Packard, and the second would be Kaiser.
-----Original Message-----
From: Phil Nutting [mailto:[log in to unmask]]
Sent: Friday, April 12, 2002 12:22 PM
To: [log in to unmask]
Subject: Re: [TN] Off Topic - The Married Spud & other burning questions
DeSoto
-----Original Message-----
From: Hinners Hans M Civ WRALC/LUGE
[mailto:[log in to unmask]]
Sent: Friday, April 12, 2002 2:47 PM
To: [log in to unmask]
Subject: Re: [TN] Off Topic - The Married Spud & other burning
questions
And you'd be wrong. It ain't a caddy but close.
-----Original Message-----
From: [log in to unmask] [mailto:[log in to unmask]]
Sent: Friday, April 12, 2002 1:30 PM
To: [log in to unmask]
Subject: Re: [TN] Off Topic - The Married Spud & other
burning questions
Hey All!
I finally got Hans's pictures up...had a few technical
difficulties. I couldn't save my page after I added the pics, but
they're there now. Go to:
http://www.stevezeva.homestead.com
When Hans sent me the pictures, he asked if could guess
what kinda car he was in,
I'm guessing a Cadillac.
-Steve Gregory-
Hey All,
Whew! Projects pop out of the woodwork when you're
going on holiday.
I passed pics onto Steve - so you don't have to go to
the Post Office to see
what I look like. LOL
Why am I still at work?
We are going on a honeymoon cruise and it leaves this
weekend. Eastern
Caribbean - Puerto Rico, St. Thomas, St. Marteen, &
Bahamas
I'm a married spud because . . .
A reference to Toy Story 2. Mr. Potato head keeps
repeating "I'm a married
spud." when they are in the Toy Store. If I really lose
it I might start
talking in nothing but movie quotes - product of a
wasted childhood &
hanging out with Cinema students at USC.
Tech Net Advice on Marriage?
My better half, Shannan, has been discussing our wedding
plans on her list @
http://www.ultimatewedding.com/
Her newlywed journal is @
http://www.weddingchat.com/showthread.php?s=&threadid=116583
All right I'll bite - what advice would the list share?
Off line for
netiquette sake.
Hans
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Date: Sat, 13 Apr 2002 12:59:56 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Howard Watson <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Howard Watson <[log in to unmask]>
Subject: Re: Through hole components in Reflow
X-To: Kathy Kuhlow <[log in to unmask]>
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Kathy,
Thanks for the feedback. The UL requirements might be something good to
look at. What I thought might be a concern is if the die bond to the case
could be damaged by the relatively high reflow temperature.
So far, I have only looked at datasheets from two component manufacturers,
neither of them address the through hole components in reflow, so maybe
they are missing the boat. I have read that through-hole reflow is the
future of soldering in the electronics industry. If so, the component
manufacturers must be there with the data to support this. Sure, most
through hole parts that will be reflow soldered are connectors, but there
may be some components where it makes sense to reflow instead of wave,
selective, or hand solder. It certainly makes sense for us with only 1 or
2 through hole parts on a board.
Howard Watson
Manufacturing Engineer
AMETEK/Dixson
Kathy Kuhlow <[log in to unmask]>
Sent by: TechNet <[log in to unmask]>
04/11/02 07:15 AM
Please respond to "TechNet E-Mail Forum."; Please respond to Kathy Kuhlow
To: [log in to unmask]
cc:
Subject: Re: [TN] Through hole components in Reflow
I would look at the plastic construction and maybe go through the UL file
requirements for that plastic. They are probably the answer on what the
flammability rating would be with data to support it. Maybe looking at
the UL tests you could find reasoning that your customer would accept.
Interesting problem though. We don't currently have products were pin to
paste is possible due to several factors so I have not had to look at
components for this recommendation. Are component manufacturer's testing
and making recommendations for pin to paste processes (other than this
part) or has the industry missed the boat and this will become a larger
issue as the technology grows?
Kathy
--=_alternative 005D1C6D87256B9A_=
Content-Type: text/html; charset="us-ascii"
<br><font size=2 face="sans-serif">Kathy,</font>
<br>
<br><font size=2 face="sans-serif">Thanks for the feedback. The UL requirements might be something good to look at. What I thought might be a concern is if the die bond to the case could be damaged by the relatively high reflow temperature.</font>
<br>
<br><font size=2 face="sans-serif">So far, I have only looked at datasheets from two component manufacturers, neither of them address the through hole components in reflow, so maybe they are missing the boat. I have read that through-hole reflow is the future of soldering in the electronics industry. If so, the component manufacturers must be there with the data to support this. Sure, most through hole parts that will be reflow soldered are connectors, but there may be some components where it makes sense to reflow instead of wave, selective, or hand solder. It certainly makes sense for us with only 1 or 2 through hole parts on a board.</font>
<br>
<br><font size=2 face="sans-serif">Howard Watson<br>
Manufacturing Engineer<br>
AMETEK/Dixson</font>
<br>
<br>
<br>
<table width=100%>
<tr valign=top>
<td>
<td><font size=1 face="sans-serif"><b>Kathy Kuhlow <[log in to unmask]></b></font>
<br><font size=1 face="sans-serif">Sent by: TechNet <[log in to unmask]></font>
<p><font size=1 face="sans-serif">04/11/02 07:15 AM</font>
<br><font size=1 face="sans-serif">Please respond to "TechNet E-Mail Forum."; Please respond to Kathy Kuhlow</font>
<br>
<td><font size=1 face="Arial"> </font>
<br><font size=1 face="sans-serif"> To: [log in to unmask]</font>
<br><font size=1 face="sans-serif"> cc: </font>
<br><font size=1 face="sans-serif"> Subject: Re: [TN] Through hole components in Reflow</font></table>
<br>
<br>
<br><font size=2 face="Courier New">I would look at the plastic construction and maybe go through the UL file requirements for that plastic. They are probably the answer on what the flammability rating would be with data to support it. Maybe looking at the UL tests you could find reasoning that your customer would accept.<br>
<br>
Interesting problem though. We don't currently have products were pin to paste is possible due to several factors so I have not had to look at components for this recommendation. Are component manufacturer's testing and making recommendations for pin to paste processes (other than this part) or has the industry missed the boat and this will become a larger issue as the technology grows? <br>
<br>
Kathy <br>
</font>
<br>
<br>
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<HTML><HEAD>
<META http-equiv=3DContent-Type content=3D"text/html; charset=3Diso-8859-1">
<META content=3D"MSHTML 6.00.2713.1100" name=3DGENERATOR></HEAD>
<BODY style=3D"MARGIN-TOP: 2px; FONT: 10pt MS Sans Serif; MARGIN-LEFT: 2px">
<DIV>I would look at the plastic construction and maybe go through the UL f=
ile
requirements for that plastic. They are probably the answer on what t=
he
flammability rating would be with data to support it. Maybe looking a=
t the
UL tests you could find reasoning that your customer would accept.</DIV>
<DIV> </DIV>
<DIV>Interesting problem though. We don't currently have products wer=
e pin
to paste is possible due to several factors so I have not had to look at
components for this recommendation. Are component manufacturer's test=
ing
and making recommendations for pin to paste processes (other than this part=
) or
has the industry missed the boat and this will become a larger issue as the
technology grows? </DIV>
<DIV> </DIV>
<DIV>Kathy </DIV></BODY></HTML>
--=_mixed 005D1C6C87256B9A_=--
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Date: Sat, 13 Apr 2002 16:30:25 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Jack Crawford <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Jack Crawford <[log in to unmask]>
Subject: IPC-A-610 has been DoD Adopted !
Mime-Version: 1.0
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consider changing to a mail reader or gateway that understands how to
properly handle MIME multipart messages.
--=_2479AD6B.D9B8D963
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IPC-A-610 Acceptability of Electronic Assemblies now has the same DoD =
adoption status as another industry standard IPC/EIA J-STD-001C Requirement=
s for Soldered Electrical and Electronic Assemblies, and the companion =
IPC-HDBK-001 w/Amendment 1 Handbook and Guide to Supplement J-STD-001 =
(Includes J-STD-001B to C Comparison).
I downloaded the adoption notice from the DODSSP QuickSearch Assist =
website http://astimage.daps.dla.mil/quicksearch/. This is an "open" site =
and anyone can download the notice. Give me a couple of days to work =
through the process and I'll also get the adoption notice downloadable =
from the IPC-A-610C description page in the online bookstore www.ipc.org/bo=
okstore.
Cordially
Jack
Text of the announcement is copied below:
ADOPTION NOTICE
IPC-A610, "Acceptability of Electronic Assemblies", was adopted on =
12-FEB-02 for use by the Department of Defense (DoD). Proposed changes by =
DoD activities must be submitted to the DoD Adopting Activity: Commander, =
US Army Tank-Automotive and Armaments Command, ATTN: AMSTA-TR-E/IE, =
Warren, MI 48397-5000. Copies of this document may be purchased from the =
The Institute for Interconnecting and Packaging Electronic Circuits, 2215 =
Sanders Rd, Suite 200 South, Northbrook, IL 60062.
http://www.ipc.org/=20
--=_2479AD6B.D9B8D963
Content-Type: text/html; charset=ISO-8859-1
Content-Transfer-Encoding: quoted-printable
Content-Description: HTML
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META http-equiv=3DContent-Type content=3D"text/html; charset=3Diso-8859-1"=
>
<META content=3D"MSHTML 5.50.4134.600" name=3DGENERATOR></HEAD>
<BODY style=3D"MARGIN-TOP: 2px; FONT: 8pt MS Sans Serif; MARGIN-LEFT: =
2px"><FONT=20
face=3D"MS Sans Serif" size=3D1>
<DIV><FONT size=3D1>IPC-A-610 Acceptability of Electronic Assemblies now =
has the=20
same DoD adoption status as another industry standard IPC/EIA J-STD-001C=20=
Requirements for Soldered Electrical and Electronic Assemblies, and the=20
companion IPC-HDBK-001 w/Amendment 1 Handbook and Guide to Supplement =
J-STD-001=20
(Includes J-STD-001B to C Comparison).</FONT></DIV>
<DIV><FONT size=3D1></FONT> </DIV>
<DIV><FONT size=3D1>I downloaded the adoption notice from the DODSSP=20
QuickSearch Assist website <A=20
href=3D"http://astimage.daps.dla.mil/quicksearch/">http://astimage.daps.dla=
.mil/quicksearch/</A>.=20
This is an "open" site and anyone can download the notice. G</FONT><FONT=20=
size=3D1>ive me a couple of days to work through the process and I'll also =
get the=20
adoption notice downloadable from </FONT><FONT size=3D1>the IPC-A-610C=
=20
description page in the online bookstore <A=20
href=3D"http://www.ipc.org/bookstore">www.ipc.org/bookstore</A>.</FONT></DI=
V>
<DIV><FONT size=3D1></FONT> </DIV>
<DIV><FONT size=3D1>Cordially</FONT></DIV>
<DIV><FONT size=3D1>Jack</FONT></DIV>
<DIV><FONT size=3D1></FONT> </DIV>
<DIV><FONT size=3D1>Text of the announcement is copied below:</FONT></DIV>
<DIV><FONT size=3D1></FONT> </DIV>
<DIV>ADOPTION NOTICE<BR>IPC-A610, "Acceptability of Electronic Assemblies",=
was=20
adopted on 12-FEB-02 for use by the Department of Defense (DoD). =
Proposed=20
changes by DoD activities must be submitted to the DoD Adopting =
Activity:=20
Commander, US Army Tank-Automotive and Armaments Command, ATTN: AMSTA-TR-E/=
IE,=20
Warren, MI 48397-5000. Copies of this document may be purchased from the =
The=20
Institute for Interconnecting and Packaging Electronic Circuits, 2215 =
Sanders=20
Rd, Suite 200 South, Northbrook, IL 60062.<BR><A=20
href=3D"http://www.ipc.org/">http://www.ipc.org/</A>=20
<BR></DIV></FONT></BODY></HTML>
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Date: Sun, 14 Apr 2002 13:02:31 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: IPC SMT FOOTPRINT DESIGN GUIDLINES VS SUPPLIERS
Folks,
Just a simple question really. How many folks use IPC SMT footprint
guidelines compared with supplier recommendations? There often is quite a
difference. As everyone on this planet uses IPC acceptance criteria, why
shouln't everyone use IPC design guidelines but for component supplier
liability issues?
MoonMan
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Date: Sun, 14 Apr 2002 22:15:45 +0200
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Matthias Mansfeld <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Matthias Mansfeld <[log in to unmask]>
Organization: Matthias Mansfeld Elektronik
Subject: Re: IPC SMT FOOTPRINT DESIGN GUIDLINES VS SUPPLIERS
In-Reply-To: <[log in to unmask]>
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On 14 Apr 2002 at 13:02, Earl Moon wrote:
> Folks,
>
> Just a simple question really. How many folks use IPC SMT footprint
> guidelines compared with supplier recommendations? There often is
> quite a difference. As everyone on this planet uses IPC acceptance
> criteria, why shouln't everyone use IPC design guidelines but for
> component supplier liability issues?
I use (where place is no issue) the IPC footprints, because my CAD
system has a quite good and complete IPC library. If place IS an
issue, I build my own or use manufacturer's or assembly house's
recommendations. For small passive and semiconductor stuff, I like
the former Philips Components Guidelines (not available any more) and
f=FCr ICs the Philips Databook IC26 (don't know whether still
available). They need much less place but also smaller tolerances.
Regards Matthias Mansfeld --
Matthias Mansfeld Elektronik
* Leiterplattenlayout, Bestueckung
Am Langhoelzl 11, 85540 Haar; Tel.: 089/4620 093-7, Fax: -8
Internet: http://www.mansfeld-elektronik.de
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Date: Sun, 14 Apr 2002 18:52:00 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Rob Legg <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Rob Legg <[log in to unmask]>
Subject: Re: IPC SMT FOOTPRINT DESIGN GUIDLINES VS SUPPLIERS
X-To: Earl Moon <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
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They are just guidelines.
IPC only documents industry practices, at a safe distance, after they are
'proven'. If you're in the process of proving what can be done, their
recommendations are only one of many reference points, any of which can be
used as valid justification for design practice.
RL
[log in to unmask]
----- Original Message -----
From: "Earl Moon" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Sunday, April 14, 2002 2:02 PM
Subject: [TN] IPC SMT FOOTPRINT DESIGN GUIDLINES VS SUPPLIERS
> Folks,
>
> Just a simple question really. How many folks use IPC SMT footprint
> guidelines compared with supplier recommendations? There often is quite a
> difference. As everyone on this planet uses IPC acceptance criteria, why
> shouln't everyone use IPC design guidelines but for component supplier
> liability issues?
>
> MoonMan
>
> --------------------------------------------------------------------------
-------
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> Please visit IPC web site http://www.ipc.org/html/forum.htm for additional
> information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700
ext.5315
> --------------------------------------------------------------------------
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>
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Date: Sun, 14 Apr 2002 21:47:48 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
David Bailey <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: David Bailey <[log in to unmask]>
Subject: 3D Pcb supplier info
I am interested in finding more info about 3d Pcb's. I have a product design
that could use this technique. I need some info on suppliers and costs,
potential design methods and general info about what can and can't be
achieved. Can anybody help.
Regards
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Date: Mon, 15 Apr 2002 01:20:02 EDT
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Joe Fjelstad <[log in to unmask]>
Subject: Re: 3D Pcb supplier info
MIME-Version: 1.0
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boundary="part1_59.1a2dba37.29ebbd02_boundary"
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Hello David
The assumption is that you are referring to molded circuits. There are a only
a few suppliers. Circuitwise is one. Have you considered using a flexible
circuit? They are the original 3D circuit and there are many more suppliers.
Kind regards,
Joe
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<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>Hello David
<BR>
<BR>The assumption is that you are referring to molded circuits. There are a only a few suppliers. Circuitwise is one. Have you considered using a flexible circuit? They are the original 3D circuit and there are many more suppliers.
<BR>
<BR>Kind regards,
<BR>Joe
<BR></FONT></HTML>
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Date: Mon, 15 Apr 2002 10:44:14 +0200
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Busko, Wolfgang" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Busko, Wolfgang" <[log in to unmask]>
Subject: Re: IPC SMT FOOTPRINT DESIGN GUIDLINES VS SUPPLIERS
X-To: Earl Moon <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
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Hi Earl,
I used to use all I could get, compared to IPC guidelines, looked at =
1:1
print until my eyes burned, looked what=B4s practical for the PCB-folks =
did
some trimming here and there and than gave it a go.
Always considered the means we had to work on the parts, it makes no =
sense
to design for just only a superduper-high-tech-future-assembly, it =
should
work here and in any other place with the same or better standards.
We had the most trouble in believing that QFP80 is QFP80 is QFP80 ....
.. and in the end =B4t wasn=B4t actually that much trouble for CAD to =
contact me
(or assembly) for new parts as was first believed...
Bet you know what works best
Wolfgang =20
=20
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Date: Mon, 15 Apr 2002 05:19:54 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: IPC SMT FOOTPRINT DESIGN GUIDLINES VS SUPPLIERS
X-To: [log in to unmask]
Thanks Wolfgang and others who have replied on and offline so far. I always
think I have the right answers but really know better.
I have several reasons for asking this question. The first relates to who is
doing what out there just out of curiousity. Next, IPC has developed
relatively new reliability and design requirements for surface mount solder
joints as 9701, 785, and 279 as examples in addition to 7095 and, of course,
782. Also, IPC, according to Jack, has had its great 610 adopted by the DoD.
Finally, while realizing 782 is a set of guidelines, as most all IPC
documents have been for years up until recently, I wonder how many folks
have the resources, or dedication like Wolfgang, to whittle, cut, scrape, or
otherwise come up with better, lesser, or more pad sizes.
I have worked with comanies as HP, Nortel, NG, and Celestica who used their
vast resources to come up with very different land patterns and pad sizes
for some parts. I recognize the component manufacturers also have the
wherewithall to do the same. Additionally, like the round pad string earlier
in this month's forum presented some interesting and, to me, realistic
possibilities for non BGA pads and the ability to minimize, mitigate, or
otherwise prevent small chip devices from tombstoning let alone moving - period.
What I'm really after, if we accept all our solder joints to IPC STANDARDS,
not guidelines, how can we not design to the guidelines without having to
spend so much extra effort refining them to be STANDARDS, or rules.
A very small company I am continuing my contract with, has reached a
critical point where they/I must decide what direction in which to proceed.
With but two designers, we are faced with decisions concerning a starting
and staying point and path. We can go all IPC, go with the "big boys proven"
land requirements, or go with component supplier recommendations.
Sure, I can use my stuff gathered and continually evolving over the years or
have a library created using available guidelines and hope to refine them
over the years. Furthermore, if all my suppliers are accepting in strict
accordance with IPC 610, as an example, surely I must design to them
especially in light of my first paragraph's important issues. These
reliability requirements are based on considerable research using IPC
guidelines, aren't they Werner and associates?
Earl Moon
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Date: Mon, 15 Apr 2002 08:04:12 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Guy Ramsey <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Guy Ramsey <[log in to unmask]>
Subject: Re: IPC SMT FOOTPRINT DESIGN GUIDLINES VS SUPPLIERS
X-To: Earl Moon <[log in to unmask]>
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
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In my experience the IPC guidelines (SM-782) usually are wide enough to
contain the set of supplier suggested designs for a given component. In some
cases the component supplier specifies a pattern outside the guidelines,
usually, optimised for component population density, these frequently create
problems in manufacturing (placement, moving components and insufficient
solder fillets).
The best solution, IMHO, is a custom library based a combination of supplier
provided patterns compared to IPC guidelines (which are optimised for
manufacturing yields and robust solder fillets), followed by lessons
learned. Which, as I read your message, is exactly what you do.
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Earl Moon
> Sent: Monday, April 15, 2002 6:20 AM
> To: [log in to unmask]
> Subject: Re: [TN] IPC SMT FOOTPRINT DESIGN GUIDLINES VS SUPPLIERS
>
>
> Thanks Wolfgang and others who have replied on and offline so
> far. I always
> think I have the right answers but really know better.
>
> I have several reasons for asking this question. The first
> relates to who is
> doing what out there just out of curiousity. Next, IPC has developed
> relatively new reliability and design requirements for surface
> mount solder
> joints as 9701, 785, and 279 as examples in addition to 7095 and,
> of course,
> 782. Also, IPC, according to Jack, has had its great 610 adopted
> by the DoD.
> Finally, while realizing 782 is a set of guidelines, as most all IPC
> documents have been for years up until recently, I wonder how many folks
> have the resources, or dedication like Wolfgang, to whittle, cut,
> scrape, or
> otherwise come up with better, lesser, or more pad sizes.
>
> I have worked with comanies as HP, Nortel, NG, and Celestica who
> used their
> vast resources to come up with very different land patterns and pad sizes
> for some parts. I recognize the component manufacturers also have the
> wherewithall to do the same. Additionally, like the round pad
> string earlier
> in this month's forum presented some interesting and, to me, realistic
> possibilities for non BGA pads and the ability to minimize, mitigate, or
> otherwise prevent small chip devices from tombstoning let alone
> moving - period.
>
> What I'm really after, if we accept all our solder joints to IPC
> STANDARDS,
> not guidelines, how can we not design to the guidelines without having to
> spend so much extra effort refining them to be STANDARDS, or rules.
>
> A very small company I am continuing my contract with, has reached a
> critical point where they/I must decide what direction in which
> to proceed.
> With but two designers, we are faced with decisions concerning a starting
> and staying point and path. We can go all IPC, go with the "big
> boys proven"
> land requirements, or go with component supplier recommendations.
>
> Sure, I can use my stuff gathered and continually evolving over
> the years or
> have a library created using available guidelines and hope to refine them
> over the years. Furthermore, if all my suppliers are accepting in strict
> accordance with IPC 610, as an example, surely I must design to them
> especially in light of my first paragraph's important issues. These
> reliability requirements are based on considerable research using IPC
> guidelines, aren't they Werner and associates?
>
> Earl Moon
>
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Date: Mon, 15 Apr 2002 08:05:55 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Maddox, Allen T" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Maddox, Allen T" <[log in to unmask]>
Subject: Re: IPC SMT FOOTPRINT DESIGN GUIDELINES VS SUPPLIERS
X-To: Earl Moon <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
We have our own manufacturing facility. I'm working on figuring out what
will work. Usually, the IC manufacture's suggested footprint doesn't.
Usually a modified variation on the IPC specs do. But, it's unique to this
plant.
Allen Maddox
Senior PCB Designer
GAI-Tronics
PO Box 1060
Reading, PA 19607-1060
Voice: 610-796-5854
FAX: 610-777-1870
www.gai-tronics.com
[log in to unmask]
-----Original Message-----
From: Earl Moon [mailto:[log in to unmask]]
Sent: Sunday, April 14, 2002 2:03 PM
To: [log in to unmask]
Subject: [TN] IPC SMT FOOTPRINT DESIGN GUIDLINES VS SUPPLIERS
Folks,
Just a simple question really. How many folks use IPC SMT footprint
guidelines compared with supplier recommendations? There often is quite a
difference. As everyone on this planet uses IPC acceptance criteria, why
shouln't everyone use IPC design guidelines but for component supplier
liability issues?
MoonMan
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Date: Mon, 15 Apr 2002 08:05:17 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Dieselberg, Ron" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Dieselberg, Ron" <[log in to unmask]>
Subject: Re: Off Topic - The Married Spud & other burning questions
X-To: Hinners Hans M Civ WRALC/LUGE <[log in to unmask]>
MIME-Version: 1.0
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I think it is a Hudson or a Packard. So which is it?
Mighty beautiful bride too. (errr if I were only 52 years younger.) Congrats
Hans.
Ron Dieselberg
Trainer/Auditor
CMC ELECTRONICS
CINCINNATI
[log in to unmask]
-----Original Message-----
From: Hinners Hans M Civ WRALC/LUGE [mailto:[log in to unmask]]
Sent: Friday, April 12, 2002 14:47 PM
To: [log in to unmask]
Subject: Re: [TN] Off Topic - The Married Spud & other burning questions
And you'd be wrong. It ain't a caddy but close.
-----Original Message-----
From: [log in to unmask] [mailto:[log in to unmask]]
Sent: Friday, April 12, 2002 1:30 PM
To: [log in to unmask]
Subject: Re: [TN] Off Topic - The Married Spud & other burning questions
Hey All!
I finally got Hans's pictures up...had a few technical difficulties. I
couldn't save my page after I added the pics, but they're there now. Go to:
http://www.stevezeva.homestead.com
When Hans sent me the pictures, he asked if could guess what kinda car he
was in,
I'm guessing a Cadillac.
-Steve Gregory-
Hey All,
Whew! Projects pop out of the woodwork when you're going on holiday.
I passed pics onto Steve - so you don't have to go to the Post Office to see
what I look like. LOL
Why am I still at work?
We are going on a honeymoon cruise and it leaves this weekend. Eastern
Caribbean - Puerto Rico, St. Thomas, St. Marteen, & Bahamas
I'm a married spud because . . .
A reference to Toy Story 2. Mr. Potato head keeps repeating "I'm a married
spud." when they are in the Toy Store. If I really lose it I might start
talking in nothing but movie quotes - product of a wasted childhood &
hanging out with Cinema students at USC.
Tech Net Advice on Marriage?
My better half, Shannan, has been discussing our wedding plans on her list @
http://www.ultimatewedding.com/
Her newlywed journal is @
http://www.weddingchat.com/showthread.php?s=&threadid=116583
All right I'll bite - what advice would the list share? Off line for
netiquette sake.
Hans
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charset="iso-8859-1"
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=iso-8859-1">
<META content="MSHTML 5.50.4522.1800" name=GENERATOR></HEAD>
<BODY>
<DIV><SPAN class=200340412-15042002><FONT face=Arial color=#0000ff>I think it is
a Hudson or a Packard. So which is it?</FONT></SPAN></DIV>
<DIV><SPAN class=200340412-15042002><FONT face=Arial color=#0000ff>Mighty
beautiful bride too. (errr if I were only 52 years younger.) Congrats
Hans.</FONT></SPAN></DIV>
<DIV> </DIV>
<P><FONT face=Arial size=2>Ron Dieselberg</FONT> <BR><FONT face=Arial
size=2>Trainer/Auditor</FONT> <BR><FONT face=Arial size=2>CMC ELECTRONICS</FONT>
<BR><FONT face=Arial size=2>CINCINNATI</FONT> <BR><FONT face=Arial
size=2>[log in to unmask]</FONT> </P>
<DIV> </DIV>
<BLOCKQUOTE dir=ltr style="MARGIN-RIGHT: 0px">
<DIV class=OutlookMessageHeader><FONT face="Times New Roman"
size=2>-----Original Message-----<BR><B>From:</B> Hinners Hans M Civ
WRALC/LUGE [mailto:[log in to unmask]]<BR><B>Sent:</B> Friday, April
12, 2002 14:47 PM<BR><B>To:</B> [log in to unmask]<BR><B>Subject:</B> Re: [TN]
Off Topic - The Married Spud & other burning
questions<BR><BR></FONT></DIV>
<DIV><SPAN class=944564518-12042002><FONT color=#0000ff>And you'd be
wrong. It ain't a caddy but close.</FONT></SPAN></DIV>
<BLOCKQUOTE>
<DIV class=OutlookMessageHeader dir=ltr align=left><FONT face=Tahoma
size=2>-----Original Message-----<BR><B>From:</B> [log in to unmask]
[mailto:[log in to unmask]]<BR><B>Sent:</B> Friday, April 12, 2002 1:30
PM<BR><B>To:</B> [log in to unmask]<BR><B>Subject:</B> Re: [TN] Off Topic - The
Married Spud & other burning questions<BR><BR></FONT></DIV><FONT
face=arial,helvetica><FONT size=2>Hey All! <BR><BR>I finally got Hans's
pictures up...had a few technical difficulties. I couldn't save my page
after I added the pics, but they're there now. Go to:
<BR><BR>http://www.stevezeva.homestead.com <BR><BR>When Hans sent me the
pictures, he asked if could guess what kinda car he was in, <BR>I'm guessing
a Cadillac. <BR><BR>-Steve Gregory- <BR><BR><BR>
<BLOCKQUOTE
style="PADDING-LEFT: 5px; MARGIN-LEFT: 5px; BORDER-LEFT: #0000ff 2px solid; MARGIN-RIGHT: 0px"
TYPE="CITE">Hey All, <BR><BR>Whew! Projects pop out of the woodwork
when you're going on holiday. <BR><BR>I passed pics onto Steve - so you
don't have to go to the Post Office to see <BR>what I look like. LOL
<BR><BR>Why am I still at work? <BR>We are going on a honeymoon cruise and
it leaves this weekend. Eastern <BR>Caribbean - Puerto Rico, St.
Thomas, St. Marteen, & Bahamas <BR><BR>I'm a married spud because . .
. <BR>A reference to Toy Story 2. Mr. Potato head keeps repeating
"I'm a married <BR>spud." when they are in the Toy Store. If I
really lose it I might start <BR>talking in nothing but movie quotes -
product of a wasted childhood & <BR>hanging out with Cinema students
at USC. <BR><BR>Tech Net Advice on Marriage? <BR>My better half, Shannan,
has been discussing our wedding plans on her list @
<BR>http://www.ultimatewedding.com/ <BR>Her newlywed journal is @
<BR>http://www.weddingchat.com/showthread.php?s=&threadid=116583
<BR><BR>All right I'll bite - what advice would the list share? Off
line for <BR>netiquette sake. <BR><BR>Hans <BR></FONT><FONT lang=0
face=Arial color=#000000 size=3
FAMILY="SANSSERIF"></BLOCKQUOTE><BR></FONT><FONT lang=0 face=Arial
color=#000000 size=2
FAMILY="SANSSERIF"><BR></BLOCKQUOTE></BLOCKQUOTE></FONT></FONT></BODY></HTML>
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Date: Mon, 15 Apr 2002 07:48:43 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: IPC SMT FOOTPRINT DESIGN GUIDELINES VS SUPPLIERS
X-To: "Allen T. Maddox" <[log in to unmask]>
Allan,
You've really hit the nail squarely. I just need to know upon what do you
make your decisions concerning, say, IPC pad parameters, say, based on 782
or does it go deeper as the design for reliability standards recently
released - or is it spacing alone?
Earl
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Date: Mon, 15 Apr 2002 10:31:00 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Jeff Seeger <[log in to unmask]>
Organization: Applied CAD Knowledge, Inc.
Subject: Re: IPC SMT FOOTPRINT DESIGN GUIDLINES VS SUPPLIERS
X-To: Earl Moon <[log in to unmask]>
MIME-Version: 1.0
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,
Earl,
I see where you're going and can find considerable empathy.
Decided long ago to *not* do just another ad-hoc yet work-
able and continuously improved library.
Consider parts footprints in shades of qualification:
- Generic (vendor supplied, who knows what info drove it)
- Broad Concensus (IPC)
- Narrow Concensus (OEM specific,w/buyin from 2+ CMs)
- Factory specific (published by each CM or OEM)
As 3rd party types, the burden of setting up & maintaining
multiple libraries this way is considerable. Having done
so, I've never once had an "Atta Boy" from a CM for giving
them designs set up to their spec, exactly, versus sending
in one to IPC spec. Seems if they want the business then
the IPC standards are sufficient to allow them to proceed.
The big problem w/782 is it takes so long for a broad con-
cencus to emerge, get argued, and get published. The next
issue regards space around components, even a 0402 casts a
large shadow in placement and ICT boundaries. Like the CM
specs that never get enforced, we see a lot of people tend
to throw out the boundaries and still succeed.
C'ya!
--
Jeff Seeger Applied CAD Knowledge Inc
Chief Technical Officer Tyngsboro, MA 01879
jseeger "at" appliedcad "dot" com 978 649 9800
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Date: Mon, 15 Apr 2002 08:22:46 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
phil bavaro <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: phil bavaro <[log in to unmask]>
Subject: Sealant Recommendations?
In-Reply-To: <[log in to unmask]
YWELL.COM>
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Ok, I've been around the sealant, conformal coating, potting, and general
adhesive world for 20 years and I have my own opinions and preferences when
it comes to specifying a compound for a production assembly, but I would
like to see what this group will suggest for this new assembly we are
designing:
We have a CCA on which is mounted a very large bulkhead type connector
which requires a form in place sealant around it where it interfaces with
(sticks through) the chassis. The connector is mechanically fastened to
the chassis with four screws but the application will see very tough
vibration exposure. The bond is between the connector flange (plastic)
and the chassis (cast aluminum) and must be capable of resisting constant
outdoor environment abuse such as high pressure water spray cleaning, motor
oils, fuels, and general dirt.
The temp range is -40 C to +85 C, and it will not be submerged (at least
not intentionally) for long periods of time but moisture is the primary
culprit that we are trying to defeat as the CCA will not be sealed with
conformal coating.
Please select your choice and tell me why? Remember, this is for
production so cure time, cost, and application ease are very important
factors. Please include whether or not the cast aluminum chassis needs to
be chem filmed, primed, or painted to seal its surface.
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Date: Mon, 15 Apr 2002 18:08:35 +0200
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Zweigart, Siegmund" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Zweigart, Siegmund" <[log in to unmask]>
Subject: Redesign Via in Pad
X-To: "[log in to unmask]" <[log in to unmask]>
MIME-Version: 1.0
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Hello to all
We have to redesign different board's because of Via in Pad:
Situation now:
FR4, thickness 1,5 mm, OCC finish
Through Hole Vias in Pads (middle, diameter 0,15..0,3 mm)
The problem is the sucking of solder form to the top to the bottom side
(causing low solder on top and bumps on test points on the bottom side)
Because of place limitations dog bones can't probably not be used.
What is your recommendation?
Using Blind Vias (problem of Voids in the solder joint?) ?
Epoxy (with Ag or what else) filled Vias?
Vias on the edge of the pad?
More ideas?
All input is welcome
Best regards
Siggi
------------------------------------------------------------------------=
----
-
Kind regards / Mit freundlichen Gr=FC=DFen
Dr. Siegmund Zweigart
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Date: Mon, 15 Apr 2002 11:29:02 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: IPC SMT FOOTPRINT DESIGN GUIDLINES VS SUPPLIERS
X-To: [log in to unmask]
Jeff,
Appreciate you time, input, and empathy. This story certainly is not new but
keeps getting more interesting and complex with time.
I'm held accountable by my CM's if the solder joints do not meet IPC
requirements. Ok, but I'm not able to directly correlate design guidelines
with acceptance criteria in IPC requirement - not guidelines especially now
that DoD has adopted and, essentially, validated the specifications - not
guidelines.
Werner serves as chair on three committees and co chair on some more, I
guess. The committees are composed of leaders in our industry putting forth
great stuff as I said before concerning design for reliability.
Component suppliers make up their rules as well. All I'm saying is there is
a gap and it seems to be getting wider especially for one or two man/woman
design teams tempted to go whichever way the wind blows whem enticed on a
particlular day.
Granted, there is much "slop" for forgiving designs, and the boards,
components, and assemblies representing them. However, with things going in
the obvious direction, as smaller/denser, something needs more attention and
less emotion as your greatly accepted empathy. Still, for my young design
team, I'm going all the way with IPC until proven wrong, or not.
Earl
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Date: Mon, 15 Apr 2002 09:55:32 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
David Douthit <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: David Douthit <[log in to unmask]>
Subject: Re: Sealant Recommendations?
X-To: phil bavaro <[log in to unmask]>
MIME-Version: 1.0
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Phil,
What class product is this? (2 or 3)
More importantly what is the "warranty" period for this product?
(Anything longer than 3 years will be a problem!)
David A. Douthit
Manager
LoCan LLC
David A. Douthit
Manager
LoCan LLC
phil bavaro wrote:
> Ok, I've been around the sealant, conformal coating, potting, and general
> adhesive world for 20 years and I have my own opinions and preferences when
> it comes to specifying a compound for a production assembly, but I would
> like to see what this group will suggest for this new assembly we are
> designing:
>
> We have a CCA on which is mounted a very large bulkhead type connector
> which requires a form in place sealant around it where it interfaces with
> (sticks through) the chassis. The connector is mechanically fastened to
> the chassis with four screws but the application will see very tough
> vibration exposure. The bond is between the connector flange (plastic)
> and the chassis (cast aluminum) and must be capable of resisting constant
> outdoor environment abuse such as high pressure water spray cleaning, motor
> oils, fuels, and general dirt.
>
> The temp range is -40 C to +85 C, and it will not be submerged (at least
> not intentionally) for long periods of time but moisture is the primary
> culprit that we are trying to defeat as the CCA will not be sealed with
> conformal coating.
>
> Please select your choice and tell me why? Remember, this is for
> production so cure time, cost, and application ease are very important
> factors. Please include whether or not the cast aluminum chassis needs to
> be chem filmed, primed, or painted to seal its surface.
>
> ---------------------------------------------------------------------------------
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> ---------------------------------------------------------------------------------
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Date: Mon, 15 Apr 2002 10:35:01 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Phil Bavaro <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Phil Bavaro <[log in to unmask]>
Subject: Re: Sealant Recommendations?
X-To: David Douthit <[log in to unmask]>
In-Reply-To: <[log in to unmask]>
Mime-Version: 1.0
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Sorry, definitely Class 2.
Warranty period of 3 years is acceptable although would like something
longer if possible.
At 09:55 AM 4/15/2002 -0700, David Douthit wrote:
>Phil,
>
>What class product is this? (2 or 3)
>More importantly what is the "warranty" period for this product?
>(Anything longer than 3 years will be a problem!)
>
>David A. Douthit
>Manager
>LoCan LLC
>
>David A. Douthit
>Manager
>LoCan LLC
>
>phil bavaro wrote:
>
> > Ok, I've been around the sealant, conformal coating, potting, and general
> > adhesive world for 20 years and I have my own opinions and preferences when
> > it comes to specifying a compound for a production assembly, but I would
> > like to see what this group will suggest for this new assembly we are
> > designing:
> >
> > We have a CCA on which is mounted a very large bulkhead type connector
> > which requires a form in place sealant around it where it interfaces with
> > (sticks through) the chassis. The connector is mechanically fastened to
> > the chassis with four screws but the application will see very tough
> > vibration exposure. The bond is between the connector flange (plastic)
> > and the chassis (cast aluminum) and must be capable of resisting constant
> > outdoor environment abuse such as high pressure water spray cleaning, motor
> > oils, fuels, and general dirt.
> >
> > The temp range is -40 C to +85 C, and it will not be submerged (at least
> > not intentionally) for long periods of time but moisture is the primary
> > culprit that we are trying to defeat as the CCA will not be sealed with
> > conformal coating.
> >
> > Please select your choice and tell me why? Remember, this is for
> > production so cure time, cost, and application ease are very important
> > factors. Please include whether or not the cast aluminum chassis needs to
> > be chem filmed, primed, or painted to seal its surface.
> >
> >
> ---------------------------------------------------------------------------------
> > Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
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> > information, or contact Keach Sasamori at [log in to unmask] or
> 847-509-9700 ext.5315
> >
> ---------------------------------------------------------------------------------
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Date: Mon, 15 Apr 2002 14:31:20 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Guy Ramsey <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Guy Ramsey <[log in to unmask]>
Subject: Re: IPC SMT FOOTPRINT DESIGN GUIDLINES VS SUPPLIERS
X-To: Earl Moon <[log in to unmask]>
In-Reply-To: <[log in to unmask]>
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Sounds like a good plan. I have seen problems with canned libraries (The
kind that are third party add-on). Usually they are okay but . . .
I have seen bad advice from component suppliers. But, I have never had a
problem when a pattern did conform to IPC guidelines. The land pattern
calculator does include provision for solder fillet characteristics (heel
fillet height, side joint length and so on).
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Earl Moon
> Sent: Monday, April 15, 2002 12:29 PM
> To: [log in to unmask]
> Subject: Re: [TN] IPC SMT FOOTPRINT DESIGN GUIDLINES VS SUPPLIERS
>
>
> Jeff,
>
> Appreciate you time, input, and empathy. This story certainly is
> not new but
> keeps getting more interesting and complex with time.
>
> I'm held accountable by my CM's if the solder joints do not meet IPC
> requirements. Ok, but I'm not able to directly correlate design guidelines
> with acceptance criteria in IPC requirement - not guidelines
> especially now
> that DoD has adopted and, essentially, validated the specifications - not
> guidelines.
>
> Werner serves as chair on three committees and co chair on some more, I
> guess. The committees are composed of leaders in our industry
> putting forth
> great stuff as I said before concerning design for reliability.
>
> Component suppliers make up their rules as well. All I'm saying
> is there is
> a gap and it seems to be getting wider especially for one or two man/woman
> design teams tempted to go whichever way the wind blows whem enticed on a
> particlular day.
>
> Granted, there is much "slop" for forgiving designs, and the boards,
> components, and assemblies representing them. However, with
> things going in
> the obvious direction, as smaller/denser, something needs more
> attention and
> less emotion as your greatly accepted empathy. Still, for my young design
> team, I'm going all the way with IPC until proven wrong, or not.
>
> Earl
>
> ------------------------------------------------------------------
> ---------------
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> ---------------
>
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Date: Mon, 15 Apr 2002 12:33:18 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Bloomquist, Ken" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Bloomquist, Ken" <[log in to unmask]>
Subject: Re: Off Topic - The Married Spud & other burning questions
MIME-Version: 1.0
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------_=_NextPart_001_01C1E4B4.652DC870
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charset="iso-8859-1"
It's a Packard!
Congratulations Hans, beautiful bride.
KennyB
-----Original Message-----
From: Dieselberg, Ron [mailto:[log in to unmask]]
Sent: Monday, April 15, 2002 5:05 AM
To: [log in to unmask]
Subject: Re: [TN] Off Topic - The Married Spud & other burning questions
I think it is a Hudson or a Packard. So which is it?
Mighty beautiful bride too. (errr if I were only 52 years younger.) Congrats
Hans.
Ron Dieselberg
------_=_NextPart_001_01C1E4B4.652DC870
Content-Type: text/html;
charset="iso-8859-1"
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=iso-8859-1">
<META content="MSHTML 5.00.3105.105" name=GENERATOR></HEAD>
<BODY>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN class=640363119-15042002>It's a
Packard!</SPAN></FONT></DIV>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN
class=640363119-15042002></SPAN></FONT> </DIV>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN
class=640363119-15042002>Congratulations Hans, beautiful
bride.</SPAN></FONT></DIV>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN
class=640363119-15042002></SPAN></FONT> </DIV>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN
class=640363119-15042002>KennyB</SPAN></FONT></DIV>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN
class=640363119-15042002></SPAN></FONT> </DIV>
<DIV align=left class=OutlookMessageHeader dir=ltr><FONT face=Tahoma
size=2>-----Original Message-----<BR><B>From:</B> Dieselberg, Ron
[mailto:[log in to unmask]]<BR><B>Sent:</B> Monday, April 15, 2002 5:05
AM<BR><B>To:</B> [log in to unmask]<BR><B>Subject:</B> Re: [TN] Off Topic - The
Married Spud & other burning questions<BR><BR></FONT></DIV>
<DIV><SPAN class=200340412-15042002><FONT color=#0000ff face=Arial>I think it is
a Hudson or a Packard. So which is it?</FONT></SPAN></DIV>
<DIV><SPAN class=200340412-15042002><FONT color=#0000ff face=Arial>Mighty
beautiful bride too. (errr if I were only 52 years younger.) Congrats
Hans.</FONT></SPAN></DIV>
<DIV> </DIV>
<P><FONT face=Arial size=2>Ron Dieselberg</FONT> <BR></P></BODY></HTML>
------_=_NextPart_001_01C1E4B4.652DC870--
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Date: Mon, 15 Apr 2002 14:50:22 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: IPC SMT FOOTPRINT DESIGN GUIDLINES VS SUPPLIERS
X-To: [log in to unmask]
Guy,
I hear you and share the concern. Hope all others do as well. Expected more
response but everyone seems quiet though I'm really not trying to stir the
pot but to save it from a fire too hot for my crew.
My "young" designers and engineers better be listening to this. You said it
right and I've seldom been wrong but for Arleen Weinberger.
MoonMan
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Date: Mon, 15 Apr 2002 13:09:25 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
David Douthit <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: David Douthit <[log in to unmask]>
Subject: Re: Sealant Recommendations?
X-To: Phil Bavaro <[log in to unmask]>
MIME-Version: 1.0
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Phil,
You are in a nasty position!
When moisture combines with motor oils, fuels, or most other man made hydrocarbon compounds
numerous acids are formed due to the chemistry of the additives. I have seen cases where this
combination will
"eat" aluminum, permeate double "O" rings, sealants, and torqued down screw combinations in 3 years.
The only choice you have is to apply a replaceable sacrificial coating over the "sealed" area and
periodically
remove and replace it (it will be fairly thick!). The main problem is finding something that will
withstand the vibration
and temperature as well as the chemical issues for a year or so.
If the rest of the CCA housing is hermetically sealed then you may have a fighting chance. If not then
you will need parylene coating on the CCA.
Good luck and please don't forget to do some serious testing of the design under operating conditions.
David a. Douthit
Manager
LoCan LLC
Phil Bavaro wrote:
> Sorry, definitely Class 2.
>
> Warranty period of 3 years is acceptable although would like something
> longer if possible.
>
> At 09:55 AM 4/15/2002 -0700, David Douthit wrote:
> >Phil,
> >
> >What class product is this? (2 or 3)
> >More importantly what is the "warranty" period for this product?
> >(Anything longer than 3 years will be a problem!)
> >
> >David A. Douthit
> >Manager
> >LoCan LLC
> >
> >David A. Douthit
> >Manager
> >LoCan LLC
> >
> >phil bavaro wrote:
> >
> > > Ok, I've been around the sealant, conformal coating, potting, and general
> > > adhesive world for 20 years and I have my own opinions and preferences when
> > > it comes to specifying a compound for a production assembly, but I would
> > > like to see what this group will suggest for this new assembly we are
> > > designing:
> > >
> > > We have a CCA on which is mounted a very large bulkhead type connector
> > > which requires a form in place sealant around it where it interfaces with
> > > (sticks through) the chassis. The connector is mechanically fastened to
> > > the chassis with four screws but the application will see very tough
> > > vibration exposure. The bond is between the connector flange (plastic)
> > > and the chassis (cast aluminum) and must be capable of resisting constant
> > > outdoor environment abuse such as high pressure water spray cleaning, motor
> > > oils, fuels, and general dirt.
> > >
> > > The temp range is -40 C to +85 C, and it will not be submerged (at least
> > > not intentionally) for long periods of time but moisture is the primary
> > > culprit that we are trying to defeat as the CCA will not be sealed with
> > > conformal coating.
> > >
> > > Please select your choice and tell me why? Remember, this is for
> > > production so cure time, cost, and application ease are very important
> > > factors. Please include whether or not the cast aluminum chassis needs to
> > > be chem filmed, primed, or painted to seal its surface.
> > >
> > >
> > ---------------------------------------------------------------------------------
> > > Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
> > > To unsubscribe, send a message to [log in to unmask] with following text in
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> > > Please visit IPC web site http://www.ipc.org/html/forum.htm for additional
> > > information, or contact Keach Sasamori at [log in to unmask] or
> > 847-509-9700 ext.5315
> > >
> > ---------------------------------------------------------------------------------
>
> ---------------------------------------------------------------------------------
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> information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700 ext.5315
> ---------------------------------------------------------------------------------
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Date: Mon, 15 Apr 2002 16:56:45 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
[log in to unmask]
Sender: TechNet <[log in to unmask]>
From: "Mark E. Schumacher" <[log in to unmask]>
Subject: Depanelization - Cracked Chip Caps
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
TechNet,
Does anyone out there have any good depanelization references or
guidelines?
Has anyone ever encountered similar problems with PCB depanelization per
below?
Problem -
We have encountered 1210 size chip capacitors failing, located near PCB
score edge, after depanelization with CAB Maestro 4M (automatic Pizza
cutter). Sectioned parts show classic flex cracks. PCBs are prescored with
30 deg and 1/3 web. The PCB edge has irregular shapes, therefore some
sections of the score line are routed. In addition, on advice from others,
we have added additional routes around the sensitive 1210 parts which were
cracking. As a consequence of these routes, we have made things worse, we
are now cracking 0805 parts (located at the end of the route) which never
were damaged before. The depanelizing cutter wheel impacts the PCB each
time it moves across a route and makes contact with the PCB. These added
routes just increased the number of impacts the PCB gets during
depanelization.
Questions -
1) Should routes around parts that are close to the score line be added
along the score line? Would I be better off getting rid of all routes in
the score line to eliminate cutter wheel impacts during depanelization? We
have noticed that we have no failures for PCBs which do not have routes in
the score line, (sore line is continuous),
2) What clearance from chip capacitors to score line should be followed as
a guideline?
3) How should parts be oriented along a score line, parrallel or
perpendicular?
Mark
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Date: Mon, 15 Apr 2002 16:57:59 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Mary Lin <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Mary Lin <[log in to unmask]>
Subject: aging test with metal plating
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Does anyone has experience with aging test of metal plating such as chrome,
aluminum on plastic chassis in a light industry environment? What I can think
of is the mixed flowing gas test, anything else I should be aware of?
Thanks for your time.
Mary
_________________________________________________________________________
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Date: Mon, 15 Apr 2002 17:16:03 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Rob Legg <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Rob Legg <[log in to unmask]>
Subject: Re: IPC SMT FOOTPRINT DESIGN GUIDLINES VS SUPPLIERS
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The adoption of guidelines as specifications always has ambivalent results.
With the military abandoning the costs of maintaining their own internal
standards, it would be unfortunate if this results in North American
commercial design initiatives being hobbled critically.
The history of technical design standardization is one of repeated attempts
to automate the process. The idea, supposedly, is that you can remove the
human tendency for error. Ideally, all you really need to produce every
widget on earth is one engineer and a lot of machines, both no doubt
polished by hordes of well-trained, inexpensive, technical acolytes.
Unfortunately, a surprisingly hefty chunk of invention and innovation is
prompted by just that human element; the smaller errors that may result and
their intelligent 'handling'. When extensively standardized, the tendency to
produce small random errors is not lost; instead it becomes systemic. This
can
generate potentially non-recoverable situations on a wide scale (e.g. the
atrophy of an entire industrial sector).
Let's not encourage anyone to turn guidelines into specifications, without a
good reason. You can always honestly say that you're following guidelines,
as guidelines, and still find out ways of getting more bang for the buck,
when it's possible.
Rob Legg
[log in to unmask]
----- Original Message -----
From: "Earl Moon" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Monday, April 15, 2002 12:29 PM
Subject: Re: [TN] IPC SMT FOOTPRINT DESIGN GUIDLINES VS SUPPLIERS
> Jeff,
>
> Appreciate you time, input, and empathy. This story certainly is not new
but
> keeps getting more interesting and complex with time.
>
> I'm held accountable by my CM's if the solder joints do not meet IPC
> requirements. Ok, but I'm not able to directly correlate design guidelines
> with acceptance criteria in IPC requirement - not guidelines especially
now
> that DoD has adopted and, essentially, validated the specifications - not
> guidelines.
>
> Werner serves as chair on three committees and co chair on some more, I
> guess. The committees are composed of leaders in our industry putting
forth
> great stuff as I said before concerning design for reliability.
>
> Component suppliers make up their rules as well. All I'm saying is there
is
> a gap and it seems to be getting wider especially for one or two man/woman
> design teams tempted to go whichever way the wind blows whem enticed on a
> particlular day.
>
> Granted, there is much "slop" for forgiving designs, and the boards,
> components, and assemblies representing them. However, with things going
in
> the obvious direction, as smaller/denser, something needs more attention
and
> less emotion as your greatly accepted empathy. Still, for my young design
> team, I'm going all the way with IPC until proven wrong, or not.
>
> Earl
>
> --------------------------------------------------------------------------
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Date: Mon, 15 Apr 2002 16:57:51 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: IPC SMT FOOTPRINT DESIGN GUIDLINES VS SUPPLIERS
X-To: [log in to unmask]
Well said and scary. No matter, no argument here. Just consider how many
folks living their lives between their legs by turning guidelines into
standards. Unbelievable, but true.
MoonMan
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Date: Mon, 15 Apr 2002 18:16:41 EDT
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Werner Engelmaier <[log in to unmask]>
Subject: Re: IPC SMT FOOTPRINT DESIGN GUIDLINES VS SUPPLIERS
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Hi Rob,
>Let's not encourage anyone to turn guidelines into specifications, without a
>good reason. You can always honestly say that you're following guidelines,
>as guidelines, and still find out ways of getting more bang for the buck,
>when it's possible.
You are absolutely right--that is why we turned the guidelines document
IPC-SM-785 into the standards document IPC-9701, even though some of the test
regimes are from a strictly technical point incorrect, but the only possible
practical compromise.
Werner Engelmaier
Engelmaier Associates, L.C.
Electronic Packaging, Interconnection and Reliability Consulting
7 Jasmine Run
Ormond Beach, FL 32174 USA
Phone: 386-437-8747, Fax: 386-437-8737
E-mail: [log in to unmask], Website: www.engelmaier.com
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Date: Mon, 15 Apr 2002 18:16:40 EDT
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Werner Engelmaier <[log in to unmask]>
Subject: Re: IPC SMT FOOTPRINT DESIGN GUIDLINES VS SUPPLIERS
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Hi MoonMan,
>OK, but I'm not able to directly correlate design guidelines
>with acceptance criteria in IPC requirement - not guidelines especially now
>that DoD has adopted and, essentially, validated the specifications - not
>guidelines.
IPC-610 ONLY assures SJ quality--that is not the same as reliability. While
quality of course is necessary for reliability, it is not sufficient--see
IPC-D-279.
So, now the Q is what is it you need to correlate. Also, I do not see the gap
you are referring to; please elucidate.
Werner Engelmaier
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Date: Mon, 15 Apr 2002 16:26:33 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Alex Krstic <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Alex Krstic <[log in to unmask]>
Subject: Re: Depanelization - Cracked Chip Caps
X-To: "[log in to unmask]" <[log in to unmask]>
Hi Mark, this is almost the same problem that we had with an 1812 multilayer
ceramic chip capacitor. For some guidance I give up the following URLs. Gotta
like that John Maxwell fella.
http://www.avxcorp.com/docs/techinfo/cracks.pdf
http://www.avxcorp.com/docs/techinfo/paramimp.pdf
http://www.avxcorp.com/docs/techinfo/assembly.pdf
http://www.avxcorp.com/docs/techinfo/smzero.pdf
http://www.kemet.com/KEMET/web/homepage/kechome.nsf/vapubfiles/f2111/$file/f2111
.pdf
Helped us, hope it helps others.
Regards,
Alex Krstic
NovAtel Inc.
Quality Engineering Services
-----Original Message-----
From: Mark E. Schumacher [mailto:[log in to unmask]]
Sent: Monday, April 15, 2002 2:57 PM
To: [log in to unmask]
Subject: [TN] Depanelization - Cracked Chip Caps
TechNet,
Does anyone out there have any good depanelization references or
guidelines?
Has anyone ever encountered similar problems with PCB depanelization per
below?
Problem -
We have encountered 1210 size chip capacitors failing, located near PCB
score edge, after depanelization with CAB Maestro 4M (automatic Pizza
cutter). Sectioned parts show classic flex cracks. PCBs are prescored with
30 deg and 1/3 web. The PCB edge has irregular shapes, therefore some
sections of the score line are routed. In addition, on advice from others,
we have added additional routes around the sensitive 1210 parts which were
cracking. As a consequence of these routes, we have made things worse, we
are now cracking 0805 parts (located at the end of the route) which never
were damaged before. The depanelizing cutter wheel impacts the PCB each
time it moves across a route and makes contact with the PCB. These added
routes just increased the number of impacts the PCB gets during
depanelization.
Questions -
1) Should routes around parts that are close to the score line be added
along the score line? Would I be better off getting rid of all routes in
the score line to eliminate cutter wheel impacts during depanelization? We
have noticed that we have no failures for PCBs which do not have routes in
the score line, (sore line is continuous),
2) What clearance from chip capacitors to score line should be followed as
a guideline?
3) How should parts be oriented along a score line, parrallel or
perpendicular?
Mark
--------------------------------------------------------------------------------
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Date: Mon, 15 Apr 2002 19:24:52 EDT
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Depanelization - Cracked Chip Caps
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="part1_131.c3f451e.29ecbb44_boundary"
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Content-Type: text/plain; charset="US-ASCII"
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Hi Mark!
Here's another *.PDF from Kemet that is pretty good:
http://www.kemet.com/KEMET/web/homepage/kechome.nsf/vapub
files/f2106/$file/f2106.pdf
I know it's a long filename, but type it in without any spaces...it talks
about MLC capacitor flex cracking...what happens with depanelizing.
One thing I must say though, a third, a third, and a third is pretty generic
when specifying scores. Yeah, that works a lot of the time, but it can burn
you more times than you would like...score depth really depends on laminate
lay-up, how the glass fibers are oriented to each other within each layer,
etc.
Also, one needs to verify that what you asked for is actually done. I've
ordered fabs from a shop that specified a score (the general 1/3, 1/3, and a
1/3) and found out after we populated the assemblies, the score was 1/3 on
one side, but barely kissed the surface on the other. So there I was with an
exacto-knife going back over the scores so I could singulate the boards
without fracturing parts...not fun. Luckily, this wasn't a high volume board.
-Steve Gregory-
>
>
> Hi Mark, this is almost the same problem that we had with an 1812
> multilayer
> ceramic chip capacitor. For some guidance I give up the following URLs.
> Gotta
> like that John Maxwell fella.
>
> http://www.avxcorp.com/docs/techinfo/cracks.pdf
>
> http://www.avxcorp.com/docs/techinfo/paramimp.pdf
>
> http://www.avxcorp.com/docs/techinfo/assembly.pdf
>
> http://www.avxcorp.com/docs/techinfo/smzero.pdf
>
>
>
>
>
>
> http://www.kemet.com/KEMET/web/homepage/kechome.nsf/vapubfiles/f2111/$file/f2111
> .pdf
>
>
>
> Helped us, hope it helps others.
>
> Regards,
>
> Alex Krstic
> NovAtel Inc.
> Quality Engineering Services
>
>
> -----Original Message-----
> From: Mark E. Schumacher [mailto:[log in to unmask]]
> Sent: Monday, April 15, 2002 2:57 PM
> To: [log in to unmask]
> Subject: [TN] Depanelization - Cracked Chip Caps
>
> TechNet,
> Does anyone out there have any good depanelization references or
> guidelines?
> Has anyone ever encountered similar problems with PCB depanelization per
> below?
>
> Problem -
> We have encountered 1210 size chip capacitors failing, located near PCB
> score edge, after depanelization with CAB Maestro 4M (automatic Pizza
> cutter). Sectioned parts show classic flex cracks. PCBs are prescored with
> 30 deg and 1/3 web. The PCB edge has irregular shapes, therefore some
> sections of the score line are routed. In addition, on advice from others,
> we have added additional routes around the sensitive 1210 parts which were
> cracking. As a consequence of these routes, we have made things worse, we
> are now cracking 0805 parts (located at the end of the route) which never
> were damaged before. The depanelizing cutter wheel impacts the PCB each
> time it moves across a route and makes contact with the PCB. These added
> routes just increased the number of impacts the PCB gets during
> depanelization.
>
> Questions -
> 1) Should routes around parts that are close to the score line be added
> along the score line? Would I be better off getting rid of all routes in
> the score line to eliminate cutter wheel impacts during depanelization? We
> have noticed that we have no failures for PCBs which do not have routes in
> the score line, (sore line is continuous),
> 2) What clearance from chip capacitors to score line should be followed as
> a guideline?
> 3) How should parts be oriented along a score line, parrallel or
> perpendicular?
>
>
> Mark
>
--part1_131.c3f451e.29ecbb44_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>Hi Mark!<BR>
<BR>
Here's another *.PDF from Kemet that is pretty good:<BR>
<BR>
http://www.kemet.com/KEMET/web/homepage/kechome.nsf/vapubfiles/f2106/$file/f2106.pdf<BR>
<BR>
I know it's a long filename, but type it in without any spaces...it talks about MLC capacitor flex cracking...what happens with depanelizing.<BR>
<BR>
One thing I must say though, a third, a third, and a third is pretty generic when specifying scores. Yeah, that works a lot of the time, but it can burn you more times than you would like...score depth really depends on laminate lay-up, how the glass fibers are oriented to each other within each layer, etc.<BR>
<BR>
Also, one needs to verify that what you asked for is actually done. I've ordered fabs from a shop that specified a score (the general 1/3, 1/3, and a 1/3) and found out after we populated the assemblies, the score was 1/3 on one side, but barely kissed the surface on the other. So there I was with an exacto-knife going back over the scores so I could singulate the boards without fracturing parts...not fun. Luckily, this wasn't a high volume board.<BR>
<BR>
-Steve Gregory-<BR>
<BR>
<BLOCKQUOTE TYPE=CITE style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px"><BR>
<BR>
Hi Mark, this is almost the same problem that we had with an 1812 multilayer<BR>
ceramic chip capacitor. For some guidance I give up the following URLs. Gotta<BR>
like that John Maxwell fella.<BR>
<BR>
http://www.avxcorp.com/docs/techinfo/cracks.pdf<BR>
<BR>
http://www.avxcorp.com/docs/techinfo/paramimp.pdf<BR>
<BR>
http://www.avxcorp.com/docs/techinfo/assembly.pdf<BR>
<BR>
http://www.avxcorp.com/docs/techinfo/smzero.pdf<BR>
<BR>
http://www.kemet.com/KEMET/web/homepage/kechome.nsf/vapubfiles/f2111/$file/f2111<BR>
.pdf<BR>
<BR>
<BR>
<BR>
Helped us, hope it helps others.<BR>
<BR>
Regards,<BR>
<BR>
Alex Krstic<BR>
NovAtel Inc.<BR>
Quality Engineering Services<BR>
<BR>
<BR>
-----Original Message-----<BR>
From: Mark E. Schumacher [mailto:[log in to unmask]]<BR>
Sent: Monday, April 15, 2002 2:57 PM<BR>
To: [log in to unmask]<BR>
Subject: [TN] Depanelization - Cracked Chip Caps<BR>
<BR>
TechNet,<BR>
Does anyone out there have any good depanelization references or<BR>
guidelines?<BR>
Has anyone ever encountered similar problems with PCB depanelization per<BR>
below?<BR>
<BR>
Problem -<BR>
We have encountered 1210 size chip capacitors failing, located near PCB<BR>
score edge, after depanelization with CAB Maestro 4M (automatic Pizza<BR>
cutter). Sectioned parts show classic flex cracks. PCBs are prescored with<BR>
30 deg and 1/3 web. The PCB edge has irregular shapes, therefore some<BR>
sections of the score line are routed. In addition, on advice from others,<BR>
we have added additional routes around the sensitive 1210 parts which were<BR>
cracking. As a consequence of these routes, we have made things worse, we<BR>
are now cracking 0805 parts (located at the end of the route) which never<BR>
were damaged before. The depanelizing cutter wheel impacts the PCB each<BR>
time it moves across a route and makes contact with the PCB. These added<BR>
routes just increased the number of impacts the PCB gets during<BR>
depanelization.<BR>
<BR>
Questions -<BR>
1) Should routes around parts that are close to the score line be added<BR>
along the score line? Would I be better off getting rid of all routes in<BR>
the score line to eliminate cutter wheel impacts during depanelization? We<BR>
have noticed that we have no failures for PCBs which do not have routes in<BR>
the score line, (sore line is continuous),<BR>
2) What clearance from chip capacitors to score line should be followed as<BR>
a guideline?<BR>
3) How should parts be oriented along a score line, parrallel or<BR>
perpendicular?<BR>
<BR>
<BR>
Mark<BR>
</BLOCKQUOTE><BR>
<BR>
</FONT></HTML>
--part1_131.c3f451e.29ecbb44_boundary--
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Date: Mon, 15 Apr 2002 19:35:38 EDT
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Depanelization - Cracked Chip Caps
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Hi again Mark,
One other thing I want to mention, is that I discovered that certain
dielectrics are very susceptable to cracking...don't have it off the top of
my head now, but when I get into work tomorrow I'll check the BOM of an
assembly that I observed that on and let you know...
-Steve Gregory-
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Date: Mon, 15 Apr 2002 19:12:24 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: IPC SMT FOOTPRINT DESIGN GUIDLINES VS SUPPLIERS
X-To: Werner Engelmaier <[log in to unmask]>
Ah Werner! You're out of your abode. Elucidate! Elucidate!
Elucidate this Sir. So we can correlate design RULE/STANDARD selection with
initial quality but not reliability, can we? Is there no correlation
possible no matter whether 279 is used as part of the equation? How do we
get there from here but for using 279 to run our own reliability testing? I
just answered my question, didn't I?
Anymore help greatly appreciated. This especially is true when attempting to
correlate initial quality acceptance, using 610, with design rules and
designing for reliability using 279.
A bit confusing, don't you think?
Earl
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Date: Mon, 15 Apr 2002 19:17:13 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Depanelization - Cracked Chip Caps
X-To: [log in to unmask]
Specify all the 1/3 or whatever but don't use cookey cutters on my MLB's no
mater the materials or constructions. You get what you ask and it usually is
cracked something. Specify routing after assembly.
MoonMan
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Date: Mon, 15 Apr 2002 21:06:42 EDT
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Depanelization - Cracked Chip Caps
X-To: [log in to unmask]
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Content-Transfer-Encoding: 7bit
Hey Earl,
I suppose that's fool-proof, but in reality, how many CM's have routers? When
I worked at a memory company, we did...all we did was SIMM's mostly, but that
was our market. At other CM's that I worked at, a router would be a strange
piece of equipment on the floor, and hard to justify.
Tab/route spec's with a "mouse bite" lessens the stress a bit, but again is
not fool-proof...and doesn't leave the smooth edge that people like (without
some extra sanding, or filing), and adds more cost to the fab (by the linear
inch for the route, and the extra holes for the mouse-bite, compared to a
straight-line score. Jump scoring is even better, makes the individual board
separate very easily, and still stay together during assembly...not many have
the machines to do that yet...boo-hoo!)
Is there not a scoring spec, and some design rules that can prevent problems?
I think there are...getting people to follow them is another story however...
-Steve "exacto-knife" Gregory-
> Specify all the 1/3 or whatever but don't use cookey cutters on my MLB's no
> mater the materials or constructions. You get what you ask and it usually
> is
> cracked something. Specify routing after assembly.
>
> MoonMan
>
--part1_8.24c07e95.29ecd322_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>Hey Earl,<BR>
<BR>
I suppose that's fool-proof, but in reality, how many CM's have routers? When I worked at a memory company, we did...all we did was SIMM's mostly, but that was our market. At other CM's that I worked at, a router would be a strange piece of equipment on the floor, and hard to justify.<BR>
<BR>
Tab/route spec's with a "mouse bite" lessens the stress a bit, but again is not fool-proof...and doesn't leave the smooth edge that people like (without some extra sanding, or filing), and adds more cost to the fab (by the linear inch for the route, and the extra holes for the mouse-bite, compared to a straight-line score. Jump scoring is even better, makes the individual board separate very easily, and still stay together during assembly...not many have the machines to do that yet...boo-hoo!)<BR>
<BR>
Is there not a scoring spec, and some design rules that can prevent problems? I think there are...getting people to follow them is another story however...<BR>
<BR>
-Steve "exacto-knife" Gregory-<BR>
<BR>
<BR>
<BLOCKQUOTE TYPE=CITE style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">Specify all the 1/3 or whatever but don't use cookey cutters on my MLB's no<BR>
mater the materials or constructions. You get what you ask and it usually is<BR>
cracked something. Specify routing after assembly.<BR>
<BR>
MoonMan<BR>
</BLOCKQUOTE><BR>
<BR>
</FONT></HTML>
--part1_8.24c07e95.29ecd322_boundary--
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Date: Mon, 15 Apr 2002 18:16:25 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
David Douthit <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: David Douthit <[log in to unmask]>
Subject: Re: aging test with metal plating
X-To: Mary Lin <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii; x-mac-type="54455854";
x-mac-creator="4D4F5353"
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Mary,
Mixed Flowing Gas tests have very little to do with reality. They are used to determine
the ability of various materials to resist certain reactive gases.
They are not designed to simulate expected conditions. They are stimulation type tests.
Correlating the results to real world conditions can be very problematic.
Telcordia (Bellcore) Spec GR-63-CORE has some interesting measured amounts of contaminants
for both indoors and outdoors. When you compare these numbers with MFG tests the divergence
is very apparent.
The real question is do you need to know what the long term effects
of exposures are or do you need to meet a contract requirement?
David A. Douthit
Manager
LoCan LLC
Mary Lin wrote:
> Does anyone has experience with aging test of metal plating such as chrome,
> aluminum on plastic chassis in a light industry environment? What I can think
> of is the mixed flowing gas test, anything else I should be aware of?
>
> Thanks for your time.
>
> Mary
> _________________________________________________________________________
>
> Live, laugh, and chat with friends about BMWs, Porsches, Jaguars and the new MINI
> at The World's Largest Auto Enthusiast Site
> http://www.roadfly.org/
>
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Date: Mon, 15 Apr 2002 20:08:54 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Depanelization - Cracked Chip Caps
X-To: [log in to unmask]
I hear you Steve. However, no pizza cutter does it right. All the "big"
companies I worked with used routers with ESD and dust safe processes
without rough edges. Just ask the fab folks and they'll agree but for price.
Hell, everything is a compromise. Just don't compromise my high layer count
PCB's with whatever components requiring rework.
Enjoy,
Earl
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Date: Mon, 15 Apr 2002 21:38:58 EDT
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Depanelization - Cracked Chip Caps
X-To: [log in to unmask]
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="part1_18a.682640b.29ecdab2_boundary"
--part1_18a.682640b.29ecdab2_boundary
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I hear you Earl, but what do you do when you have a teeny-tiny double-sided
SMT assembly, that has a pair of SMT female sockets installed on one side so
that it can plug into a pair of SMT headers on the main board? This assembly
is about 1/2-inch wide, by about 2-inches long...when I get back to work,
I'll take a picture of it and post it on my page...this was my exacto-knife
experience..
There's no tooling holes or PTH's to be able to locate the individual boards
on a routing fixture that you would need to have to route it, it's all
SMT...it's absolutely too small to try and run by itself, so you are left
with fabbing it in a panel and scoring it, or building it individually and
soldering it by hand..the latter is ludicroius...soldering caps by hand is
not a good thing as we all know...
Working at a CM as you know, means dealing with things that are thrown over
the wall...I luv it (not).
-Steve Gregory-
> I hear you Steve. However, no pizza cutter does it right. All the "big"
> companies I worked with used routers with ESD and dust safe processes
> without rough edges. Just ask the fab folks and they'll agree but for
> price.
>
> Hell, everything is a compromise. Just don't compromise my high layer count
> PCB's with whatever components requiring rework.
>
> Enjoy,
>
> Earl
>
--part1_18a.682640b.29ecdab2_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>I hear you Earl, but what do you do when you have a teeny-tiny double-sided SMT assembly, that has a pair of SMT female sockets installed on one side so that it can plug into a pair of SMT headers on the main board? This assembly is about 1/2-inch wide, by about 2-inches long...when I get back to work, I'll take a picture of it and post it on my page...this was my exacto-knife experience..<BR>
<BR>
There's no tooling holes or PTH's to be able to locate the individual boards on a routing fixture that you would need to have to route it, it's all SMT...it's absolutely too small to try and run by itself, so you are left with fabbing it in a panel and scoring it, or building it individually and soldering it by hand..the latter is ludicroius...soldering caps by hand is not a good thing as we all know...<BR>
<BR>
Working at a CM as you know, means dealing with things that are thrown over the wall...I luv it (not).<BR>
<BR>
-Steve Gregory-<BR>
<BR>
<BR>
<BLOCKQUOTE TYPE=CITE style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">I hear you Steve. However, no pizza cutter does it right. All the "big"<BR>
companies I worked with used routers with ESD and dust safe processes<BR>
without rough edges. Just ask the fab folks and they'll agree but for price.<BR>
<BR>
Hell, everything is a compromise. Just don't compromise my high layer count<BR>
PCB's with whatever components requiring rework.<BR>
<BR>
Enjoy,<BR>
<BR>
Earl<BR>
</BLOCKQUOTE><BR>
<BR>
</FONT></HTML>
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Date: Tue, 16 Apr 2002 04:39:24 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Matt Kehoe <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Matt Kehoe <[log in to unmask]>
Subject: Sign off
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SIGNOFF Technet
Matt Kehoe
SIPAD Systems Inc.
360-C Winkler Drive
Alpharetta, GA. 30004
770-475-4576 fon
770-475-1597 fax
[log in to unmask]
www.sipad.net
----- Original Message -----
From: "David Douthit" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Monday, April 15, 2002 9:16 PM
Subject: Re: [TN] aging test with metal plating
> Mary,
>
> Mixed Flowing Gas tests have very little to do with reality. They are used
to determine
> the ability of various materials to resist certain reactive gases.
>
> They are not designed to simulate expected conditions. They are
stimulation type tests.
> Correlating the results to real world conditions can be very problematic.
>
> Telcordia (Bellcore) Spec GR-63-CORE has some interesting measured amounts
of contaminants
> for both indoors and outdoors. When you compare these numbers with MFG
tests the divergence
> is very apparent.
>
> The real question is do you need to know what the long term effects
> of exposures are or do you need to meet a contract requirement?
>
> David A. Douthit
> Manager
> LoCan LLC
>
> Mary Lin wrote:
>
> > Does anyone has experience with aging test of metal plating such as
chrome,
> > aluminum on plastic chassis in a light industry environment? What I can
think
> > of is the mixed flowing gas test, anything else I should be aware of?
> >
> > Thanks for your time.
> >
> > Mary
> >
_________________________________________________________________________
> >
> > Live, laugh, and chat with friends about BMWs, Porsches, Jaguars and the
new MINI
> > at The World's Largest Auto Enthusiast Site
> > http://www.roadfly.org/
> >
>
> --------------------------------------------------------------------------
-------
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> > information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700
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>
> --------------------------------------------------------------------------
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>
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Date: Tue, 16 Apr 2002 05:12:55 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Depanelization - Cracked Chip Caps
X-To: [log in to unmask]
Steve,
For your, hopefully not my, teeny-tiny double sided SMT MLB assemblies I
either punt or do as you say with the knife. That is why you love it - for
sure. That is why I love it, or not but always fight, as you, the dummies
accepting the job in the first place and the dumb ass designers bowing to
either management or total ignorance. I try never to have to build those
type boards, and sure fight not to do them, especially without tooling holes
and a multiple fixturing system, as a carrier, placed on the routing surface.
For sure, being on the design end currently with a similar board, I won't
allow the design not to be routed and I'm fighting that issue right now.
Can't afford the broken part rework and/or delamination at the edges. What a
luxury, eh? Of course, with the board you describe, I can't imagine getting
a pizza chattering, tearing, dull bladed thing in there either, hence the
exacto munndo knife.
As for your last comment, and well said, I have a young production,
purchasing, document control, or not, manager condeming the whole damn
electronics industry because of more than the stuff we're discussing.
Carlile, you looking in?
Enjoy the design, fab, CM, test world we're in, or not. Hell, I can't
imagine another world but, then, I have nothing else or not that I can
remember or do anymore.
Earl
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Date: Tue, 16 Apr 2002 06:58:18 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Tostevin, Bruce" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Tostevin, Bruce" <[log in to unmask]>
Subject: Re: Sealant Recommendations?
X-To: phil bavaro <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain
Phil,
It's a bit messy and tricky to work with, but how about something like
Aviation Permatex? It will form in place, cure decently, certainly resist
oils, hydrocarbons and dirt. I would think that it's temperature range
probably about where you need it to be. I'm not sure how it'll affect your
plastic connector flange though.
Bruce Tostevin
Benchmark Electronics
Hudson, New Hampshire
> -----Original Message-----
> From: phil bavaro [SMTP:[log in to unmask]]
> Sent: Monday, April 15, 2002 11:23 AM
> To: [log in to unmask]
> Subject: [TN] Sealant Recommendations?
>
> Ok, I've been around the sealant, conformal coating, potting, and general
> adhesive world for 20 years and I have my own opinions and preferences
> when
> it comes to specifying a compound for a production assembly, but I would
> like to see what this group will suggest for this new assembly we are
> designing:
>
> We have a CCA on which is mounted a very large bulkhead type connector
> which requires a form in place sealant around it where it interfaces with
> (sticks through) the chassis. The connector is mechanically fastened to
> the chassis with four screws but the application will see very tough
> vibration exposure. The bond is between the connector flange (plastic)
> and the chassis (cast aluminum) and must be capable of resisting constant
> outdoor environment abuse such as high pressure water spray cleaning,
> motor
> oils, fuels, and general dirt.
>
> The temp range is -40 C to +85 C, and it will not be submerged (at least
> not intentionally) for long periods of time but moisture is the primary
> culprit that we are trying to defeat as the CCA will not be sealed with
> conformal coating.
>
> Please select your choice and tell me why? Remember, this is for
> production so cure time, cost, and application ease are very important
> factors. Please include whether or not the cast aluminum chassis needs
> to
> be chem filmed, primed, or painted to seal its surface.
>
> --------------------------------------------------------------------------
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Date: Tue, 16 Apr 2002 08:44:18 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"McMullen, Kerry" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "McMullen, Kerry" <[log in to unmask]>
Subject: Re: IPC SMT FOOTPRINT DESIGN GUIDLINES VS SUPPLIERS
X-To: Earl Moon <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Using IPC guidelines and some concurrent, proactive DFM review with my CM
has just about always worked for me. Mostly want to insure I get good toe
and heel............ AND NO VIA IN PAD :)
-----Original Message-----
From: Earl Moon [mailto:[log in to unmask]]
Sent: Monday, April 15, 2002 3:50 PM
To: [log in to unmask]
Subject: Re: [TN] IPC SMT FOOTPRINT DESIGN GUIDLINES VS SUPPLIERS
Guy,
I hear you and share the concern. Hope all others do as well. Expected more
response but everyone seems quiet though I'm really not trying to stir the
pot but to save it from a fire too hot for my crew.
My "young" designers and engineers better be listening to this. You said it
right and I've seldom been wrong but for Arleen Weinberger.
MoonMan
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Date: Tue, 16 Apr 2002 09:07:02 EDT
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Werner Engelmaier <[log in to unmask]>
Subject: Re: IPC SMT FOOTPRINT DESIGN GUIDLINES VS SUPPLIERS
X-To: [log in to unmask]
MIME-Version: 1.0
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Hi Earl,
No, I don't agree that things are confusing.
The whole point of 279 is that by using its DfR-guidelines reliability can be
assured without reliability testing. After properly designing your
electronics, manufacture to good quality completes the process of making good
product,
Best regards,
Werner Engelmaier
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Date: Tue, 16 Apr 2002 14:05:29 +0100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Geoff Layhe <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Geoff Layhe <[log in to unmask]>
Subject: Re: Nickel Test
X-To: "[log in to unmask]" <[log in to unmask]>
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A late reply on this but I knew I had some information on porosity testing
hidden away somewhere.
Dimethylglyoxime is a spot test reagent for nickel in the presence of
ammonia. As far as I can remember the dmg was dissolved in iso-propyl
alcohol (approx 2%)and ammonia added. This solution turns red in the
presence of nickel, and was used as a porosity test for gold on nickel.
I don't have this method for porosity but I do have one using nioxime. This
test was used for porosity of electroplated gold on electroplated nickel on
copper. The minimum coating thicknesses were 2.5 microns (0.0001")gold on 5
microns (0.0002") nickel.
The test uses pressure and current so I doubt if it will be OK for the thin
enig coatings.
If you want the text of the test let me know your fax No.
Geoff Layhe
www.lamar-uk.co.uk
-----Original Message-----
From: Rudy Sedlak [mailto:[log in to unmask]]
Sent: 11 April 2002 02:25
To: [log in to unmask]
Subject: [TN] Nickel Test
I recall seeing a spot test for Nickel that involved using a solution of
Dimethylglyoxime in dilute Ammonia, + ???? as a spot test for gold porosity
to show presence of Nickel.
Does anyone have the exact details of this test? Does anyone know if it
works on Electroless Nickel? (Suspect it may not because EN is so much more
passive.)
Rudy Sedlak
RD Chemical Company
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Date: Tue, 16 Apr 2002 09:13:53 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
[log in to unmask]
Sender: TechNet <[log in to unmask]>
From: "Mark E. Schumacher" <[log in to unmask]>
Subject: Re: Depanelization - Cracked Chip Caps
X-To: [log in to unmask]
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Steve,
What is jump scoring?
Mark
[log in to unmask]
COM To: [log in to unmask]
Sent by: cc:
TechNet Subject: Re: [TN] Depanelization - Cracked Chip Caps
<[log in to unmask]
RG>
04/15/02 09:06
PM
Please respond
to "TechNet
E-Mail
Forum.";
Please respond
to SteveZeva
Hey Earl,
I suppose that's fool-proof, but in reality, how many CM's have routers?
When I worked at a memory company, we did...all we did was SIMM's mostly,
but that was our market. At other CM's that I worked at, a router would be
a strange piece of equipment on the floor, and hard to justify.
Tab/route spec's with a "mouse bite" lessens the stress a bit, but again is
not fool-proof...and doesn't leave the smooth edge that people like
(without some extra sanding, or filing), and adds more cost to the fab (by
the linear inch for the route, and the extra holes for the mouse-bite,
compared to a straight-line score. Jump scoring is even better, makes the
individual board separate very easily, and still stay together during
assembly...not many have the machines to do that yet...boo-hoo!)
Is there not a scoring spec, and some design rules that can prevent
problems? I think there are...getting people to follow them is another
story however...
-Steve "exacto-knife" Gregory-
Specify all the 1/3 or whatever but don't use cookey cutters on my MLB's
no
mater the materials or constructions. You get what you ask and it usually
is
cracked something. Specify routing after assembly.
MoonMan
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Date: Tue, 16 Apr 2002 08:30:27 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: IPC SMT FOOTPRINT DESIGN GUIDLINES VS SUPPLIERS
X-To: Werner Engelmaier <[log in to unmask]>
I agree Werner but it takes more than you and me to get this stuff home to
the people who are supposed to be responsible and care enough to be.
Just trying to fight the fight to help win the war,
Earl
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Date: Tue, 16 Apr 2002 08:32:44 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: IPC SMT FOOTPRINT DESIGN GUIDLINES VS SUPPLIERS
X-To: [log in to unmask]
RIGHT ON, RIGHT ON and my apologies to sheik muhammad hole in pad for being
too crude and too ignorant by displaying my findings as objectively as
possible based on observation and experiments.
Earl
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Date: Tue, 16 Apr 2002 09:27:55 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
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From: Dave Hillman <[log in to unmask]>
Subject: Cracking Chip Resistors
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Hi folks! I have ran into a problem which has me baffled and the extra 20
ounces of Coke I consumed this morning didn't bring about any better
thought clarity so I would like to bounce the problem off the minds of
TechNet. I have been attempting to hand solder a chip resistor (50 x 100)
but have immediate cracking of the resistor across the width of the
component. The resistor is either Aluminum Nitride or BeO (I'm still trying
to find out which material). And yes, we are using proper soldering
technique(s) and the resistor pad geometries are our standard dimensions. I
know that the typical resistor body material is Alumina. Has anyone had
good or bad experiences in hand soldering AlN or BeO resistors? Have I run
into a material flexural strength issue?
Dave Hillman
Rockwell Collins
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Date: Tue, 16 Apr 2002 10:37:23 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Mary Lin <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Mary Lin <[log in to unmask]>
Subject: Re: aging test with metal plating
X-To: David Douthit <[log in to unmask]>
In-Reply-To: <[log in to unmask]>
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David-
Thanks for your response. I do need to know what the long term effects
of exposures are as we haven't applied this finish before. We are very
concerned about corrosion since chrome plating is vry shiney.And therefore MFG
test will clear up this concern.
Since this is metal on plastic, we consider doing thermal cycling test as CTE
is different. I don't know how to correlate this test with field aplication
over 5 years, i.e. what will be appropriate test cycles and dwell time at
extreme temperatures.
Thans again.
Mary
On Mon, 15 Apr 2002 18:16:25 -0700
David Douthit <[log in to unmask]> wrote:
>Mary,
>
>Mixed Flowing Gas tests have very little to do with reality. They are used to
>determine
>the ability of various materials to resist certain reactive gases.
>
>They are not designed to simulate expected conditions. They are stimulation
>type tests.
>Correlating the results to real world conditions can be very problematic.
>
>Telcordia (Bellcore) Spec GR-63-CORE has some interesting measured amounts of
>contaminants
>for both indoors and outdoors. When you compare these numbers with MFG tests
>the divergence
>is very apparent.
>
>The real question is do you need to know what the long term effects
>of exposures are or do you need to meet a contract requirement?
>
>David A. Douthit
>Manager
>LoCan LLC
>
>Mary Lin wrote:
>
>> Does anyone has experience with aging test of metal plating such as chrome,
>> aluminum on plastic chassis in a light industry environment? What I can
>>think
>> of is the mixed flowing gas test, anything else I should be aware of?
>>
>> Thanks for your time.
>>
>> Mary
>> _________________________________________________________________________
>>
>> Live, laugh, and chat with friends about BMWs, Porsches, Jaguars and the new
>>MINI
>> at The World's Largest Auto Enthusiast Site
>> http://www.roadfly.org/
>>
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>
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Date: Tue, 16 Apr 2002 09:53:00 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Jack C. Olson" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Jack C. Olson" <[log in to unmask]>
Subject: Re: IPC SMT FOOTPRINT DESIGN GUIDLINES VS SUPPLIERS
X-cc: [log in to unmask]
MIME-Version: 1.0
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Great question!
We have wasted SO much time designing custom libraries
for specific vendors, its to the point of being ridiculous.
Here is what I would do if I was starting over:
- Design to IPC unless I had a GOOD reason not to.
- NEVER use a component data sheet. can't trust 'em.
- If a vendor had a reason supported by SCIENTIFIC
DATA to suggest a change, DOCUMENT IT!
The ideal (in my opinion) would be to say "All footprints
conform to IPC with the exception of..." and for those
exceptions explain WHY YOU CHANGED IT. (including
high density versions, wave solder alternates, whatever)
best wishes,
Jack
-----Original Message-----
From: Earl Moon [mailto:[log in to unmask]]
Sent: Sunday, April 14, 2002 2:03 PM
To: [log in to unmask]
Subject: [TN] IPC SMT FOOTPRINT DESIGN GUIDLINES VS SUPPLIERS
Folks,
Just a simple question really. How many folks use IPC SMT footprint
guidelines compared with supplier recommendations? There often is quite a
difference. As everyone on this planet uses IPC acceptance criteria, why
shouln't everyone use IPC design guidelines but for component supplier
liability issues?
MoonMan
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Date: Tue, 16 Apr 2002 10:56:13 EDT
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Depanelization - Cracked Chip Caps
X-To: [log in to unmask]
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Content-Type: multipart/alternative;
boundary="part1_ca.a0d27a9.29ed958d_boundary"
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Hi Mark!
Jump scoring is a method in which the score is done for individual boards in
the panel, but does not continue all the way out to the edge of the panel.
What this does is to make the panel strong enough to not fall apart during
the assembly process, but yet still have a score deep enough along the
individual boards so as to separate easily.
Go to:
http://www.accusystemscorp.com/FAQ's%20-%20Index.htm
There they have a really good FAQ about scoring...has a section about Jump
scoring too...
-Steve Gregory-
--part1_ca.a0d27a9.29ed958d_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>Hi Mark!
<BR>
<BR>Jump scoring is a method in which the score is done for individual boards in the panel, but does not continue all the way out to the edge of the panel. What this does is to make the panel strong enough to not fall apart during the assembly process, but yet still have a score deep enough along the individual boards so as to separate easily.
<BR>
<BR>Go to:
<BR>
<BR>http://www.accusystemscorp.com/FAQ's%20-%20Index.htm
<BR>
<BR>There they have a really good FAQ about scoring...has a section about Jump scoring too...
<BR>
<BR>-Steve Gregory-</FONT></HTML>
--part1_ca.a0d27a9.29ed958d_boundary--
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Date: Tue, 16 Apr 2002 09:53:52 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: IPC SMT FOOTPRINT DESIGN GUIDLINES VS SUPPLIERS
X-To: "Jack C. Olson" <[log in to unmask]>
Jack,
Now you've done it. I'm using your post for all my, 2, designers and make it
a strict requirement until maturity, based on quality and reliability
analysis says otherwise.
Thank you very much
Earl Moon
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Date: Tue, 16 Apr 2002 09:58:16 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Cracking Chip Resistors
X-To: Dave Hillman <[log in to unmask]>
Dave,
With all due respect to a 40 year old, masters degreed, coke junkie, how can
you perrom adequately. I know, you probably just oversee the hand soldering
process performed extremely well by a TRAINED hand soldering management expert.
As for the rest, BeO presents its unique set of problems but should solder
without cracking. As for traditional cap constructions, the same can be
said. So what's different but for your extreme coke ingestion this AM?
MoonMan
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Date: Tue, 16 Apr 2002 10:01:15 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Munie, Gregory" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Munie, Gregory" <[log in to unmask]>
Subject: Re: Nickel Test
X-To: Geoff Layhe <[log in to unmask]>
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Another late entry:
There's an old Bell System test for coatings. The outline is below.
1. Saturate a filter paper with an aqueous soln of 0.4M Na2CO3 and 0.1M
NaCl.
2. Sandwich the filter paper and a blotter sheet
between the test sample and a metal plate so the filter paper is in =
contact
with the test sample. Good contact with the test sample is essential!
3. Connect a dc power supply between the test sample (positive) and =
the
metal plate (negative) and set the current to 5ma/cm2 and maintain =
for
30s.
4. Remove the filter paper and develop in a 1% solution of =
Dimethylglyoxime
in a solvent made of 95%v/v EtOH and 5%conc NH4OH.
5. Count the developed red spots using 10X mag.
6. Typical pore counts for hard Au over Ni are:
>50 =B5inch: <20 pores/cm2
30=B5inch: <30pores/cm2
25=B5inch: <50pores/cm2
-----Original Message-----
From: Geoff Layhe [mailto:[log in to unmask]]
Sent: Tuesday, April 16, 2002 8:05 AM
To: [log in to unmask]
Subject: Re: [TN] Nickel Test
A late reply on this but I knew I had some information on porosity =
testing
hidden away somewhere.
Dimethylglyoxime is a spot test reagent for nickel in the presence of
ammonia. As far as I can remember the dmg was dissolved in iso-propyl
alcohol (approx 2%)and ammonia added. This solution turns red in the
presence of nickel, and was used as a porosity test for gold on nickel.
I don't have this method for porosity but I do have one using nioxime. =
This
test was used for porosity of electroplated gold on electroplated =
nickel on
copper. The minimum coating thicknesses were 2.5 microns (0.0001")gold =
on 5
microns (0.0002") nickel.
The test uses pressure and current so I doubt if it will be OK for the =
thin
enig coatings.
If you want the text of the test let me know your fax No.
Geoff Layhe
www.lamar-uk.co.uk
-----Original Message-----
From: Rudy Sedlak [mailto:[log in to unmask]]
Sent: 11 April 2002 02:25
To: [log in to unmask]
Subject: [TN] Nickel Test
I recall seeing a spot test for Nickel that involved using a solution =
of
Dimethylglyoxime in dilute Ammonia, + ???? as a spot test for gold =
porosity
to show presence of Nickel.
Does anyone have the exact details of this test? Does anyone know if =
it
works on Electroless Nickel? (Suspect it may not because EN is so much =
more
passive.)
Rudy Sedlak
RD Chemical Company
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847-509-9700
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Date: Tue, 16 Apr 2002 10:10:20 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Depanelization - Cracked Chip Caps
X-To: [log in to unmask]
Steve,
You submit a very important issue as definition and as a requirement.
Another reason I/we have problems with pizza scoring and
cutting/depanelizing/defect/etc. is the V groove tolerances as incapable of
being met most of the time especially with high density MLB's. If it's a two
sided board or 4 layer type, I couldn't care less as long as no damage is done.
Earl
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Date: Tue, 16 Apr 2002 18:30:56 +0300
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Brian Ellis <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Brian Ellis <[log in to unmask]>
Subject: Re: Cracking Chip Resistors
X-To: [log in to unmask]
MIME-Version: 1.0
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Dave
Are you sure Doug didn't lace your Coke with Mountain Dew?
Brian
Dave Hillman wrote:
>
> Hi folks! I have ran into a problem which has me baffled and the extra 20
> ounces of Coke I consumed this morning didn't bring about any better
> thought clarity so I would like to bounce the problem off the minds of
> TechNet. I have been attempting to hand solder a chip resistor (50 x 100)
> but have immediate cracking of the resistor across the width of the
> component. The resistor is either Aluminum Nitride or BeO (I'm still trying
> to find out which material). And yes, we are using proper soldering
> technique(s) and the resistor pad geometries are our standard dimensions. I
> know that the typical resistor body material is Alumina. Has anyone had
> good or bad experiences in hand soldering AlN or BeO resistors? Have I run
> into a material flexural strength issue?
>
> Dave Hillman
> Rockwell Collins
> [log in to unmask]
>
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Date: Tue, 16 Apr 2002 08:35:23 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Dan R. Johnson" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Dan R. Johnson" <[log in to unmask]>
Subject: Re: Depanelization - Cracked Chip Caps
X-To: Earl Moon <[log in to unmask]>
MIME-version: 1.0
Content-type: text/plain; charset=iso-8859-1
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Hi Earl & Steve,
I build assemblies which start at .5 X .5 and go down in size to .175 X .175
with smaller stuff in development. There are two simple solutions to the
quandary of depanelizing these little $&%'ers. Most of our low volume stuff
is tab routed with tiny tabs holding them into the array, flush cutters
remove them. Higher cost but higher margin on low volume so that's OK.
High volume stuff goes out to the dicing service. I also have a dicing saw
in house for medium volume stuff. You can pick up a used dicing saw cheap,
it doesn't need to be accurate enough for die, even a really badly aligned
saw can hold +/- .0005 over 5" of travel. The facilities requirements can
get pricy but you probably already have air and vacuum available, so all you
need is a re-circ/ chiller for the water. I kluged ours together out of a
stock tank and a sump pump (welcome to cow country).
My panels have standard tooling holes and sizes regardless of the unit size
so one size tooling fits all. Panels set up for dicing really maximize your
PCB yield since there is almost no waste, the saw kerf is .008 - .010", and
the cost of a service is less than labor to cut the things out of a tab
routed array.
If you want to contact me offline I can but you in touch with a reliable
dicing service and a good used equipment vendor. Be careful of the guys in
silicon gulch, they have a lean and hungry look right now.
Dan
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Date: Tue, 16 Apr 2002 11:34:59 EDT
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Dennis Fritz <[log in to unmask]>
Subject: Re: aging test with metal plating
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MIME-Version: 1.0
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Mary, I suggest you contact the
American Society of Electroplated Plastics (ASEP)
1767 Business Center Drive
Reston, VA 22090
Executive Director: David W. Barrack
Association Director: Brian Meltzer
Phone: 703-438-3101
Their association deals with plating of plastics
Dennis Fritz
MacDermid, Inc.
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Date: Tue, 16 Apr 2002 10:54:17 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Kathy Kuhlow <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Kathy Kuhlow <[log in to unmask]>
Subject: Re: IPC SMT FOOTPRINT DESIGN GUIDLINES VS SUPPLIERS
Mime-Version: 1.0
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Of all that do not necessarily use the IPC guidelines how do you comply =
with section 1.2 of the IPC-610? It seems pretty clear in 1.2 that unless =
a design complies with the IPC or equivalent requirements then the =
acceptance criteria needs to be defined between the customer and supplier. =
How many of you sit down and have this discussion? =20
Kathy=20
--=_F7AA7A56.C8A9C471
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<META content="MSHTML 6.00.2713.1100" name=GENERATOR></HEAD>
<BODY style="MARGIN-TOP: 2px; FONT: 10pt MS Sans Serif; MARGIN-LEFT: 2px">
<DIV>Of all that do not necessarily use the IPC guidelines how do you comply
with section 1.2 of the IPC-610? It seems pretty clear in 1.2 that
unless a design complies with the IPC or equivalent requirements then the
acceptance criteria needs to be defined between the customer and supplier.
How many of you sit down and have this discussion? </DIV>
<DIV> </DIV>
<DIV>Kathy </DIV>
<DIV> </DIV></BODY></HTML>
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Date: Tue, 16 Apr 2002 10:59:14 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Ken Carlile <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Ken Carlile <[log in to unmask]>
Subject: Re: IPC SMT FOOTPRINT DESIGN GUIDLINES VS SUPPLIERS
I have read many responses to this very question, but have yet to read a
manufacturer defending why he/she has deviated from IPC specifications. If
there are any representatives out there I would be eager to hear your
PROs/CONs (arguments).
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Date: Tue, 16 Apr 2002 12:20:37 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"WEEKES, MICHAEL HS-SNS" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "WEEKES, MICHAEL HS-SNS" <[log in to unmask]>
Subject: question - 2 parts
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
1. Can I build a 20 layer PWB that does not exceed 0.125 overall thickness
and still have 2 oz Cu that still meets IPC class 3? I have some concern
about controlled impedance and the need for inner layers being thick enough
to meet product objective.
2. Have any of you pursued the DoD "Single Process Initiative" (SPI)
process, often referred to as a "Block Change", which lets military
contractors file a single document with DoD stating that they will use one
standard (usually J-STD-001) for all their soldering requirements. I'd like
to discuss how it went and whether there were any special hoops you had to
jump through.
TechNet participants from Boeing, DoD, Raytheon, Lockheed-Martin,
Northrop-Grumman, Bechtel Plant Machinery, BAE, L-3 Communications, AAI or
others are especially invited to respond.
Mike Weekes
[log in to unmask]
Boeing and DoD have contracts with many companies that work to IPC
standards. Boeing themselves, also Raytheon, Lockheed-Martin,
Northrop-Grumman, Bechtel Plant Machinery, BAE, L-3 Communications, AAI to
name just a few.
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Date: Tue, 16 Apr 2002 11:28:22 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Depanelization - Cracked Chip Caps
X-To: [log in to unmask]
Dan,
I agree dicing saws are the best thing ever. You have stated the
disadvantages not withstanding the face they are very kind to both die and
boards. We use them all the time to extract test coupons from detached
quality conformance test circuitry once punched out with whatever crude method.
Says work well but provide the same problems, as room to manuver, as do
pizza cutters and routers.
Thank you,
Earl
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Date: Tue, 16 Apr 2002 11:35:58 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: IPC SMT FOOTPRINT DESIGN GUIDLINES VS SUPPLIERS
X-To: Kathy Kuhlow <[log in to unmask]>
Kathy,
Right on as well. I communicate first with a contract supported by the
master drawing and the assembly drawing. These are the requirements any
customer must provide for acceptable product. To further concurrence,
clearly defined acceptance requirements must be observed, stated, and
correlated with to enaure customer contract requirements are met.
Concurrence, either face to face or performed in other WRITTEN
communications, must establish whether a supplier can meet customer
requirements. If not, the design or process must be changed for the
"parthership" to work. If negative discussions, and there results, are
forthcoming, look for another suppleri, designer, engineer, or design.
It's a good story not always positively told. As you are a dedicated DFM/CE
authority, you know how to make the equation work, or not.
Earl
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Date: Tue, 16 Apr 2002 11:37:33 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: IPC SMT FOOTPRINT DESIGN GUIDLINES VS SUPPLIERS
X-To: Ken Carlile <[log in to unmask]>
I most fervently concur.
MoonMan
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Date: Tue, 16 Apr 2002 12:44:09 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Creswick, Steven" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Creswick, Steven" <[log in to unmask]>
Subject: Re: Cracking Chip Resistors
X-To: "[log in to unmask]" <[log in to unmask]>
MIME-Version: 1.0
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Dave,
As I recall AlN (4-4.5 ppm) has a lower TCE than either Alumina (7 ppm) or
Beo (7.2-8ppm) at soldering temperatures. One would expect that as the
PWB contracted during cooling (having a still greater TCE), that the
resistor would be in compression - not a problem here! Is the contraction
of the individual solder joints sufficient to crack the body??
I looked in my records but wouldn't you know it, I am missing tensile
strength info for AlN. But, yes it is weaker than Alumina.
Al2O3 - 0.193 GPa, BeO - 0.062-0.069GPa, AlN - ?
Flexural Strength -
Al2O3 - 0.274-0.4 GPa, BeO - 0.110 GPa, AlN - 0.25-0.32 GPa
Got me baffled as well. Never soldered BeO or AlN chip resistors - sorry.
Guess I need to down another Vernors Ginger Ale!
Steven Creswick - Gentex Corp
-----Original Message-----
From: Dave Hillman [mailto:[log in to unmask]]
Sent: Tuesday, April 16, 2002 10:28 AM
To: [log in to unmask]
Subject: [TN] Cracking Chip Resistors
Hi folks! I have ran into a problem which has me baffled and the extra 20
ounces of Coke I consumed this morning didn't bring about any better
thought clarity so I would like to bounce the problem off the minds of
TechNet. I have been attempting to hand solder a chip resistor (50 x 100)
but have immediate cracking of the resistor across the width of the
component. The resistor is either Aluminum Nitride or BeO (I'm still trying
to find out which material). And yes, we are using proper soldering
technique(s) and the resistor pad geometries are our standard dimensions. I
know that the typical resistor body material is Alumina. Has anyone had
good or bad experiences in hand soldering AlN or BeO resistors? Have I run
into a material flexural strength issue?
Dave Hillman
Rockwell Collins
[log in to unmask]
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Date: Tue, 16 Apr 2002 11:41:21 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Donald Kyle <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Donald Kyle <[log in to unmask]>
Subject: Re: Cracking Chip Resistors
X-To: [log in to unmask]
In-Reply-To: <[log in to unmask] m>
MIME-version: 1.0
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Dave,
Sounds like thermal shock. What you need to do is raise the temperature of
the component slowly before soldering, the higher the better. Also, check
your soldering iron temperature if you are using an iron.
If you have a re-flow air stream, use it to heat the chip and
board. Slowly heat the component and board to a temperature of 125 to 175
C. Then re-flow or hand solder the part to the board.
Donald Kyle
At 09:27 AM 4/16/2002, you wrote:
>Hi folks! I have ran into a problem which has me baffled and the extra 20
>ounces of Coke I consumed this morning didn't bring about any better
>thought clarity so I would like to bounce the problem off the minds of
>TechNet. I have been attempting to hand solder a chip resistor (50 x 100)
>but have immediate cracking of the resistor across the width of the
>component. The resistor is either Aluminum Nitride or BeO (I'm still trying
>to find out which material). And yes, we are using proper soldering
>technique(s) and the resistor pad geometries are our standard dimensions. I
>know that the typical resistor body material is Alumina. Has anyone had
>good or bad experiences in hand soldering AlN or BeO resistors? Have I run
>into a material flexural strength issue?
>
>Dave Hillman
>Rockwell Collins
>[log in to unmask]
>
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>
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Date: Tue, 16 Apr 2002 12:54:16 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Randy Bock Sr." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Randy Bock Sr." <[log in to unmask]>
Subject: Re: Depanelization - Cracked Chip Caps
X-To: "Dan R. Johnson" <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
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As my Grandfather used to always tell me "Necessity is the Mother of
Invention."
MOOOOO
----- Original Message -----
From: Dan R. Johnson <[log in to unmask]>
To: <[log in to unmask]>
Sent: Tuesday, April 16, 2002 11:35 AM
Subject: Re: [TN] Depanelization - Cracked Chip Caps
> Hi Earl & Steve,
> I build assemblies which start at .5 X .5 and go down in size to .175 X
.175
> with smaller stuff in development. There are two simple solutions to the
> quandary of depanelizing these little $&%'ers. Most of our low volume
stuff
> is tab routed with tiny tabs holding them into the array, flush cutters
> remove them. Higher cost but higher margin on low volume so that's OK.
> High volume stuff goes out to the dicing service. I also have a dicing
saw
> in house for medium volume stuff. You can pick up a used dicing saw cheap,
> it doesn't need to be accurate enough for die, even a really badly aligned
> saw can hold +/- .0005 over 5" of travel. The facilities requirements can
> get pricy but you probably already have air and vacuum available, so all
you
> need is a re-circ/ chiller for the water. I kluged ours together out of a
> stock tank and a sump pump (welcome to cow country).
> My panels have standard tooling holes and sizes regardless of the unit
size
> so one size tooling fits all. Panels set up for dicing really maximize
your
> PCB yield since there is almost no waste, the saw kerf is .008 - .010",
and
> the cost of a service is less than labor to cut the things out of a tab
> routed array.
> If you want to contact me offline I can but you in touch with a reliable
> dicing service and a good used equipment vendor. Be careful of the guys in
> silicon gulch, they have a lean and hungry look right now.
> Dan
>
> --------------------------------------------------------------------------
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Date: Tue, 16 Apr 2002 09:55:24 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Frank Langlois <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Frank Langlois <[log in to unmask]>
Subject: Re: IPC SMT FOOTPRINT DESIGN GUIDLINES/ Philips Guidelines
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 8bit
Does anyone have any feedback specifically on the use of the smaller
sized Philips surface mount component guidelines? It would be nice if only
IPC recommended sizes could be used but sometimes space requirements will
not allow it.
Frank Langlois
Project Development
P.O. Box 5582
Bend, OR 97708
----- Original Message -----
From: "Matthias Mansfeld" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Sunday, April 14, 2002 1:15 PM
Subject: Re: [TN] IPC SMT FOOTPRINT DESIGN GUIDLINES VS SUPPLIERS
On 14 Apr 2002 at 13:02, Earl Moon wrote:
> Folks,
>
> Just a simple question really. How many folks use IPC SMT footprint
> guidelines compared with supplier recommendations? There often is
> quite a difference. As everyone on this planet uses IPC acceptance
> criteria, why shouln't everyone use IPC design guidelines but for
> component supplier liability issues?
I use (where place is no issue) the IPC footprints, because my CAD
system has a quite good and complete IPC library. If place IS an
issue, I build my own or use manufacturer's or assembly house's
recommendations. For small passive and semiconductor stuff, I like
the former Philips Components Guidelines (not available any more) and
für ICs the Philips Databook IC26 (don't know whether still
available). They need much less place but also smaller tolerances.
Regards Matthias Mansfeld --
Matthias Mansfeld Elektronik
* Leiterplattenlayout, Bestueckung
Am Langhoelzl 11, 85540 Haar; Tel.: 089/4620 093-7, Fax: -8
Internet: http://www.mansfeld-elektronik.de
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Date: Tue, 16 Apr 2002 12:26:01 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: IPC SMT FOOTPRINT DESIGN GUIDLINES/ Philips Guidelines
X-To: [log in to unmask]
For what it's worth, usually smaller works better. As someone said, "I need
toe and heel fillets" meaning, to me, side fillets are not required. I
concur and stand behind my 0603 on 0402 footprints, as but one example. As
for the rest, many large companies, with large resources, prove this and
similar requirements. Still, as a rookie operation, I must start with IPC
MoonMan
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Date: Tue, 16 Apr 2002 12:28:29 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Cracking Chip Resistors
X-To: [log in to unmask]
Steve,
You really are an old timer. TCE instead of CTE? I still use the former.
When did it all change?
Earl
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Date: Tue, 16 Apr 2002 15:58:01 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
[log in to unmask]
Sender: TechNet <[log in to unmask]>
From: "Mark E. Schumacher" <[log in to unmask]>
Subject: Re: Depanelization - Cracked Chip Caps
X-To: "Dan R. Johnson" <[log in to unmask]>
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
Dan,
Please fill me in.
Mark
"Dan R.
Johnson" To: [log in to unmask]
<[log in to unmask] cc:
COM> Subject: Re: [TN] Depanelization - Cracked Chip Caps
Sent by:
TechNet
<[log in to unmask]
RG>
04/16/02 11:35
AM
Please respond
to "TechNet
E-Mail
Forum.";
Please respond
to "Dan R.
Johnson"
Hi Earl & Steve,
I build assemblies which start at .5 X .5 and go down in size to .175 X
.175
with smaller stuff in development. There are two simple solutions to the
quandary of depanelizing these little $&%'ers. Most of our low volume stuff
is tab routed with tiny tabs holding them into the array, flush cutters
remove them. Higher cost but higher margin on low volume so that's OK.
High volume stuff goes out to the dicing service. I also have a dicing saw
in house for medium volume stuff. You can pick up a used dicing saw cheap,
it doesn't need to be accurate enough for die, even a really badly aligned
saw can hold +/- .0005 over 5" of travel. The facilities requirements can
get pricy but you probably already have air and vacuum available, so all
you
need is a re-circ/ chiller for the water. I kluged ours together out of a
stock tank and a sump pump (welcome to cow country).
My panels have standard tooling holes and sizes regardless of the unit size
so one size tooling fits all. Panels set up for dicing really maximize your
PCB yield since there is almost no waste, the saw kerf is .008 - .010", and
the cost of a service is less than labor to cut the things out of a tab
routed array.
If you want to contact me offline I can but you in touch with a reliable
dicing service and a good used equipment vendor. Be careful of the guys in
silicon gulch, they have a lean and hungry look right now.
Dan
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Date: Tue, 16 Apr 2002 16:39:23 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Rob Legg <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Rob Legg <[log in to unmask]>
Subject: Re: IPC SMT FOOTPRINT DESIGN GUIDLINES VS SUPPLIERS
X-To: Ken Carlile <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit
Is there any reason for a manufacturer to do so, unless its a specific
client enquiry? Here's one or two on the same web page. You should also be
able to find similar reasons in this forum's correspondence, but few posters
will claim to be "a manufacturer"; they are simply the individuals
responsible for getting things done.
http://www.giscafe.com/DACafe/USERSGROUPS/cctug/specctra_email_bin/1999/msg0
0735.html
As an example, a recent link in forum correspondence pointed to this Kemet
article, which deals specifically with the juggling of IPC782 deficiencies
and errors.
http://www.kemet.com/kemet/web/homepage/kechome.nsf/vapubfiles/f2100e/$file/
f2100e.pdf
RL
----- Original Message -----
From: "Ken Carlile" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Tuesday, April 16, 2002 11:59 AM
Subject: Re: [TN] IPC SMT FOOTPRINT DESIGN GUIDLINES VS SUPPLIERS
> I have read many responses to this very question, but have yet to read a
> manufacturer defending why he/she has deviated from IPC specifications.
If
> there are any representatives out there I would be eager to hear your
> PROs/CONs (arguments).
>
> --------------------------------------------------------------------------
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Date: Wed, 17 Apr 2002 09:30:15 +1200
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Michael Bell <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Michael Bell <[log in to unmask]>
Subject: End Cap/Resistor problems
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Hey all,
I have just had a few questions raised regarding a customers product and
it's reliability. Presently, they are potting a control circuitry into a
siliconne rubber mould. This is sealed and then installed in oven control
systems. What appears to be happening is, over it's lifetime, for some
unknown reason, the ends of the SMT caps is corroding and giving
intermittant faults. If you pearce the siliconne rubber mould and press on
the end cap with a probe, it then forms a contact and the fault goes away.
The PCB itself is an FR4 PCB with HASL finish, and has an operating current
of around 6mA. The product is washed once inside the oven control, but
shouldn't the siliconne rubber protect this sufficently enough??? Since the
rubber is a permeable compound, is it possible for water to make it's way
into the mould and onto the surface of the PCB and then not escape????
Would this lead to the corrosion of the end caps???
Cheers
Mike
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Date: Tue, 16 Apr 2002 17:53:31 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
[log in to unmask]
Sender: TechNet <[log in to unmask]>
From: "Mark E. Schumacher" <[log in to unmask]>
Subject: Re: End Cap/Resistor problems
X-To: Michael Bell <[log in to unmask]>
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
Michael,
Join the club............... Conformal coating of silicone is porous to
sulfur, the sulfur attacks the exposed silver end terminations were the
epoxy meets the termination. Usually see black clouds in silicone conformal
coating around termination.
You need to find the source of sulfur in your system. For us it was an EPDM
rubber grommet. We also went from Dale parts (which have no Pd content) to
KOA parts with have 4% minimum Pd. We also went to a acrylic/polyeurathane
conformal coating. Our problems have been gone for 3 years.
Please contact me off line for additional details.
Mark
Michael Bell
<Michael.Bell@ To: [log in to unmask]
GPC.CO.NZ> cc:
Sent by: Subject: [TN] End Cap/Resistor problems
TechNet
<[log in to unmask]
RG>
04/16/02 05:30
PM
Please respond
to "TechNet
E-Mail
Forum.";
Please respond
to Michael
Bell
Hey all,
I have just had a few questions raised regarding a customers product and
it's reliability. Presently, they are potting a control circuitry into a
siliconne rubber mould. This is sealed and then installed in oven control
systems. What appears to be happening is, over it's lifetime, for some
unknown reason, the ends of the SMT caps is corroding and giving
intermittant faults. If you pearce the siliconne rubber mould and press on
the end cap with a probe, it then forms a contact and the fault goes away.
The PCB itself is an FR4 PCB with HASL finish, and has an operating current
of around 6mA. The product is washed once inside the oven control, but
shouldn't the siliconne rubber protect this sufficently enough??? Since
the
rubber is a permeable compound, is it possible for water to make it's way
into the mould and onto the surface of the PCB and then not escape????
Would this lead to the corrosion of the end caps???
Cheers
Mike
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Date: Wed, 17 Apr 2002 07:53:33 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: IPC SMT FOOTPRINT DESIGN GUIDLINES VS SUPPLIERS
X-To: Earl Moon <[log in to unmask]>
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
Hi, Earl,
We went through some pain with this a while back and decided to adopt the
following heirarchy:
1. Where supplier reccomendations exist, use them.
2. Where no supplier recommendation exists, but where there are fottprints
given in IPA-SM-782, use those.
3. Where neither of the above are specific, calculate your own. There is a
formula given in IPC-SM-782 near the beginning, but it's also on-line from
the IPC website. There are, however a number of other on-line calculators
available that give slightly differing results, so the pattern you wind up
with can often be based on best guess and experience, given the surrounding
board features and the assembly processes to be used.
Determining land patterns/footprints is still something of a black art
rather than a science, and as with all recommendations, they aren't always
applicable to specific cases - they have to be decided by the man on the
spot.
Not a lot of help perhaps, but then there isn't much to be had in this
area, I found - too many permutations that affect a given pattern for a
given component on a given class, layout, construction, operation, etc.,
etc., etc. of PCB.
Best of Luck
Peter
Earl Moon
<[log in to unmask] To: [log in to unmask]
M.COM> cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
Sent by: Aero/ST Group)
TechNet Subject: [TN] IPC SMT FOOTPRINT DESIGN
<[log in to unmask] GUIDLINES VS SUPPLIERS
ORG>
04/15/02
02:02 AM
Please
respond to
"TechNet
E-Mail
Forum.";
Please
respond to
Earl Moon
Folks,
Just a simple question really. How many folks use IPC SMT footprint
guidelines compared with supplier recommendations? There often is quite a
difference. As everyone on this planet uses IPC acceptance criteria, why
shouln't everyone use IPC design guidelines but for component supplier
liability issues?
MoonMan
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Date: Tue, 16 Apr 2002 17:13:43 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
David Douthit <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: David Douthit <[log in to unmask]>
Subject: Re: End Cap/Resistor problems
X-To: Michael Bell <[log in to unmask]>
MIME-Version: 1.0
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boundary="------------421D163E24778FA28164A68C"
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Michael,
The product is washed once inside the oven control, but
shouldn't the siliconne rubber protect this sufficiently enough???
NO!
Since therubber is a permeable compound, is it possible for water to make it's way
into the mould and onto the surface of the PCB and then not escape????
The moisture level on the surface of the PCB will achieve and maintain equilibrium with the surrounding
area
Would this lead to the corrosion of the end caps??? YES!!
How long of a life time are you talking about?
David A. Douthit
Manager
LoCan LLC
Michael Bell wrote:
> Hey all,
>
> I have just had a few questions raised regarding a customers product and
> it's reliability. Presently, they are potting a control circuitry into a
> siliconne rubber mould. This is sealed and then installed in oven control
> systems. What appears to be happening is, over it's lifetime, for some
> unknown reason, the ends of the SMT caps is corroding and giving
> intermittant faults. If you pearce the siliconne rubber mould and press on
> the end cap with a probe, it then forms a contact and the fault goes away.
> The PCB itself is an FR4 PCB with HASL finish, and has an operating current
> of around 6mA. The product is washed once inside the oven control, but
> shouldn't the siliconne rubber protect this sufficently enough??? Since the
> rubber is a permeable compound, is it possible for water to make it's way
> into the mould and onto the surface of the PCB and then not escape????
> Would this lead to the corrosion of the end caps???
>
> Cheers
>
> Mike
>
> ---------------------------------------------------------------------------------
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<html>
Michael,<i></i>
<p><i>The product is washed once inside the oven control, but</i>
<br><i>shouldn't the siliconne rubber protect this sufficiently enough???</i>
<br>NO!<i></i>
<p><i>Since therubber is a permeable compound, is it possible for water
to make it's way</i>
<br><i>into the mould and onto the surface of the PCB and then not escape????</i>
<br>The moisture level on the surface of the PCB will achieve and maintain
equilibrium with the surrounding area<i></i>
<p><i>Would this lead to the corrosion of the end caps??? </i>YES!!
<p>How long of a life time are you talking about?
<p>David A. Douthit
<br>Manager
<br>LoCan LLC<i></i>
<p>Michael Bell wrote:
<blockquote TYPE=CITE>Hey all,
<p>I have just had a few questions raised regarding a customers product
and
<br>it's reliability. Presently, they are potting a control circuitry
into a
<br>siliconne rubber mould. This is sealed and then installed in
oven control
<br>systems. What appears to be happening is, over it's lifetime,
for some
<br>unknown reason, the ends of the SMT caps is corroding and giving
<br>intermittant faults. If you pearce the siliconne rubber mould
and press on
<br>the end cap with a probe, it then forms a contact and the fault goes
away.
<br>The PCB itself is an FR4 PCB with HASL finish, and has an operating
current
<br>of around 6mA. The product is washed once inside the oven control,
but
<br>shouldn't the siliconne rubber protect this sufficently enough???
Since the
<br>rubber is a permeable compound, is it possible for water to make it's
way
<br>into the mould and onto the surface of the PCB and then not escape????
<br>Would this lead to the corrosion of the end caps???
<p>Cheers
<p>Mike
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Date: Wed, 17 Apr 2002 09:02:51 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: IPC SMT FOOTPRINT DESIGN GUIDLINES VS SUPPLIERS
X-To: "Jack C. Olson" <[log in to unmask]>
MIME-Version: 1.0
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Jack,
I had great difficulty in getting land patterns to "conform to IPC". If you
have a registered land pattern and it's in IPC-SM-782, but you then
check/compare it using the calculator/formula in the same spec, you get two
different results. Where is the conformity, I ask? Also, there are more
instances of no-land-pattern-information-availability than there are
guidelines or recommendations. As was said, component manufacturers do
their own thing, maybe loosely centred around "standard" package types, but
they often differ enough from the standard to make one suspicious about
using the "standard" land patterns for them.
As I said (provocatively) in my last reply posting, there are too many
permutations in board design, materials, assembly processes, component
package styles, materials and contents, operating conditions and so on, to
have a concise "standard" for all occasions - unless each parameter in the
overall CCA universe becomes standard/fixed. What we have are workable
compromises that suit most groups of parameters. It's towards the more
extreme CCA applications and environments that these compromises start to
break down.
I believe there's still a ways to go before 'art' changes to 'science'.
Peter
"Jack C.
Olson" To: [log in to unmask]
<OLSON_JACK_C cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
@CAT.COM> Aero/ST Group)
Sent by: Subject: Re: [TN] IPC SMT FOOTPRINT DESIGN
TechNet GUIDLINES VS SUPPLIERS
<[log in to unmask]
ORG>
04/16/02
10:53 PM
Please
respond to
"TechNet
E-Mail
Forum.";
Please
respond to
"Jack C.
Olson"
Great question!
We have wasted SO much time designing custom libraries
for specific vendors, its to the point of being ridiculous.
Here is what I would do if I was starting over:
- Design to IPC unless I had a GOOD reason not to.
- NEVER use a component data sheet. can't trust 'em.
- If a vendor had a reason supported by SCIENTIFIC
DATA to suggest a change, DOCUMENT IT!
The ideal (in my opinion) would be to say "All footprints
conform to IPC with the exception of..." and for those
exceptions explain WHY YOU CHANGED IT. (including
high density versions, wave solder alternates, whatever)
best wishes,
Jack
-----Original Message-----
From: Earl Moon [mailto:[log in to unmask]]
Sent: Sunday, April 14, 2002 2:03 PM
To: [log in to unmask]
Subject: [TN] IPC SMT FOOTPRINT DESIGN GUIDLINES VS SUPPLIERS
Folks,
Just a simple question really. How many folks use IPC SMT footprint
guidelines compared with supplier recommendations? There often is quite a
difference. As everyone on this planet uses IPC acceptance criteria, why
shouln't everyone use IPC design guidelines but for component supplier
liability issues?
MoonMan
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Date: Tue, 16 Apr 2002 23:27:23 EDT
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Werner Engelmaier <[log in to unmask]>
Subject: Re: IPC SMT FOOTPRINT DESIGN GUIDLINES VS SUPPLIERS
X-To: [log in to unmask]
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Ahh Earl,
You can lead the horse [or is it ass] to the water, but you cannot make it
drink.
Werner
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Date: Wed, 17 Apr 2002 11:29:09 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Cracking Chip Resistors
X-To: Earl Moon <[log in to unmask]>
MIME-Version: 1.0
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It changed when the pedants took over and demanded greater perceived
precision through change of emphasis. CTE is deemed to be more
scientifically correct than TCE (so my teach told me many moons ago (NPI)).
TCE = Thermal Co-efficient of Expansion as opposed to any other
co-efficient of expansion, while
CTE = Co-efficient of Thermal Expansion as opposed to a co-efficient of
expansion caused by anything else.
The idea is to place the emphasis on the 'Co-efficient' bit, not on the
'Thermal' bit ... or something.
I'm just bored and just wanted to say something, OK?
Peter
Earl Moon
<[log in to unmask] To: [log in to unmask]
M.COM> cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
Sent by: Aero/ST Group)
TechNet Subject: Re: [TN] Cracking Chip Resistors
<[log in to unmask]
ORG>
04/17/02
01:28 AM
Please
respond to
"TechNet
E-Mail
Forum.";
Please
respond to
Earl Moon
Steve,
You really are an old timer. TCE instead of CTE? I still use the former.
When did it all change?
Earl
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Date: Wed, 17 Apr 2002 00:08:25 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
YH Koh <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: YH Koh <[log in to unmask]>
Subject: Ionic Contamination for No Clean Flux
To TechNet,
Wondering if there is a specifcation to indicate the limit of ionic
contamination for an after reflow boards. Understand that the amount of the
flux activator remain on the boards is depending on the amount of solder
joints on the boards. So, is there a criteria to address the amount of
ionic versus the pads area or other related criterias?
We are currently having corrosion on the board (after 1 year of application
in the field). The flux we are using are no clean RMA flux. After
extracted the flux remnant from the boards and subjected for Capillary
Electrophoresis (CE-MS) test, we found high amount of bromide, chloride,
nitrite and nitrate. I am not sure if thease are the elements that caused
the corrosion.
From here, I am not sure if it is practical to specify the ionic limit on
the after reflow boards? Or should continue to work on the driven factor of
the corrosion like water, voltage, electromigration etc?
Appreciate any inputs.
Best Regards,
YH Koh
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Date: Wed, 17 Apr 2002 00:34:38 -0500
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Seth Goodman <[log in to unmask]>
Subject: Re: connecting aluminum to copper
X-To: [log in to unmask]
In-Reply-To: <003b01c1e1f6$e208b370$f502a8c0@ukomfenner>
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Hi Mike,
While I agree with you in general about the reactivity of aluminum, in
specific cases it can be used successfully. One obvious example is aluminum
sheet metal cases housing circuit boards. It is necessary to maintain
electrical continuity from panel-to-panel and from panel to earth ground
(third wire) if you need to comply with IEC60950 and many other standards.
I have commonly used anodized or anodized and painted aluminum parts on
cases, and the anodizing is a nearly ideal insulator. To solve this
problem, we use star washers under the screw heads and the nuts are
self-broaching fasteners pressed in from behind. The ground wire terminal
is fastened with a nut onto a self-broaching stud pressed into the aluminum
chassis. I've seen some very old equipment come in from the field (chemical
laboratory environment) very grungy but without corrosion and still having
continuity.
My impression is that when you compress the star washer with enough force,
the projections on the washer that pierce the thin anodized layer form a
gas-tight connection to the aluminum substrate and therefore do not oxidize
or corrode. Yes, the fasteners and their finishes have to be compatible for
the environment, but this approach has been successful for many years.
Similarly, it is possible to fasten a PCB to an aluminum standoff with a
stainless steel screw, with or without a star washer. The screw threads
break through the anodized coating inside the threaded aluminum fastener and
the screw head makes good contact with the top side of the PCB. UL does not
accept this as a primary ground connection, though this has nothing to do
with corrosion. Since the aluminum spacer contacts the tin/lead (or tin)
coated pad on the bottom side of the board, I would be very careful to not
let anything get at that joint. Personally, I prefer to use steel standoffs
when possible. My first choice is a self-broaching threaded standoff
pressed directly into the aluminum chassis. These are available with closed
bottoms (blind threaded) to avoid liquid ingress. Obviously, these must be
pressed in after anodizing and before painting.
Hope this has been of some help.
Regards,
Seth Goodman
Goodman Associates, LLC
tel 608.833.9933
fax 608.833.9966
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Mike Fenner
> Sent: Friday, April 12, 2002 2:52 AM
> To: [log in to unmask]
> Subject: Re: [TN] connecting aluminum to copper
>
>
> Aluminium to anything will fairly quickly go electrically open circuit,
> although you will retain thermal conductivity. Depending on the conditions
> of use and the contact metal you will next slowly or quickly achieve all
> sorts of corrosion issues. Immunise the aluminium from the outside world
> with something more stable like nickel
>
> Kind Regards
>
> Mike Fenner
>
> Applications Engineer, European Operations
> Indium Corporation
> T: + 44 1908 580 400
> M: + 44 7810 526 317
> F: + 44 1908 580 411
> E: [log in to unmask]
> W: www.indium.com
> Leadfree: www.Pb-Free.com
>
>
>
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Phil Nutting
> Sent: Wednesday, April 10, 2002 9:12 PM
> To: [log in to unmask]
> Subject: [TN] connecting aluminum to copper
>
>
> Good afternoon TechNet,
>
> Would anyone like to share their knowledge about using an
> aluminum standoff
> as a conductor when connecting two circuit boards together. I
> suspect that
> if it were aluminum to copper there would be an issue, but what about
> aluminum to HASL surface of circuit boards?
>
> Thanks in advance for your wisdom,
>
> Phil Nutting
>
> ------------------------------------------------------------------
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Date: Wed, 17 Apr 2002 00:57:58 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: IPC SMT FOOTPRINT DESIGN GUIDLINES VS SUPPLIERS
X-To: Werner Engelmaier <[log in to unmask]>
Damn Werner, my horse usually can't even be lead. Often it's so broken it
can't walk. I ought to shoot it out of kindness but it pays the bills so I
don't protest to loudly.
Earl
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Date: Wed, 17 Apr 2002 09:04:21 +0300
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Brian Ellis <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Brian Ellis <[log in to unmask]>
Subject: Re: Cracking Chip Resistors
X-To: [log in to unmask]
MIME-Version: 1.0
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Peter
If you wish to be really pedantic, how about LCTE, as opposed to VCTE (I
learnt both of these at school, about 60 years ago)? You may think the
volume coefficient is the cube of the linear, but 'tis not, necessarily.
In amorphous molecular structures, it usually is, but it is rarely the
case in morphous ones, as X, Y and Z LCTEs are rarely the same (take
FR-4 as one example).
Brian
Dave Hillman wrote:
>
> Hi folks! I have ran into a problem which has me baffled and the extra 20
> ounces of Coke I consumed this morning didn't bring about any better
> thought clarity so I would like to bounce the problem off the minds of
> TechNet. I have been attempting to hand solder a chip resistor (50 x 100)
> but have immediate cracking of the resistor across the width of the
> component. The resistor is either Aluminum Nitride or BeO (I'm still trying
> to find out which material). And yes, we are using proper soldering
> technique(s) and the resistor pad geometries are our standard dimensions. I
> know that the typical resistor body material is Alumina. Has anyone had
> good or bad experiences in hand soldering AlN or BeO resistors? Have I run
> into a material flexural strength issue?
>
> Dave Hillman
> Rockwell Collins
> [log in to unmask]
>
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Date: Wed, 17 Apr 2002 01:03:54 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: IPC SMT FOOTPRINT DESIGN GUIDLINES VS SUPPLIERS
X-To: [log in to unmask]
As always, thanks Peter. I've been down the same road with the same results.
This time is different.
I have too "young gun" designers wanting to do it their way. No problem as
long as their way is my way. Every PCB designer with whom I've ever worked
has a tremendous need to be creative. Not being an "artist" myself or
artistic in any way, I want the facts man, just the facts and applied rather
scientifically.
Hell, I have one designer wanting to change MY master drawing notes. Not in
my lifetime on this contract. These notes correlate almost exactly to IPC
600 acceptance SPECIFICATIONS. You don't mess with something that works and
I wouldn't have said that a few years ago about IPC before it's resurrection.
Earl
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Date: Wed, 17 Apr 2002 01:13:11 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Cracking Chip Resistors
X-To: [log in to unmask]
Actually, as told me by a very serious and dedicated mechanical enginnering
type, like me, it changed in 1972, or thereabouts. Academia started the
"new" stuff to reflect what you say. I agree with it but it's just real hard
for old hard heads to make the change. 1972, are you joshing me?
Another thing I have difficulty with is pounds/foot instead of foot/pounds.
I came from the 409 Chevy and 429 Boss and super Cobra Jet era. Anyone else
that old having bought, built, or otherwise used "real" muscle in their cars
or boats. ft./lbs. of torque got you off the line as acceleration is a
function of torque unlike all these little high revin' torqueless high horse
power motors of today claiming high speed is a function of RPM without
benefit of fast acceleration.
I do love the smell of burned nitro in the morning,
MoonMan
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Date: Wed, 17 Apr 2002 01:39:54 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Cracking Chip Resistors
X-To: [log in to unmask]
Now that's saying something profound. Forget my rantings about 409's ect.
Earl
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Date: Wed, 17 Apr 2002 09:55:56 +0300
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Brian Ellis <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Brian Ellis <[log in to unmask]>
Subject: Re: Ionic Contamination for No Clean Flux
X-To: YH Koh <[log in to unmask]>
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There is no specification, nor can there be. There are far too many
variables. Ionic contamination testing cannot correlate the reliability
of assemblies with flux residues thereon. However, your ionic mix sounds
very suspicious, although you do not mention the quantities of each
anion. I suggest that your problem MAY be due, at least partially, to
your bare boards coming from the PCB fab guys complete with a hefty dose
of contamination. Most RMA fluxes contain small quantities of EITHER
bromides OR chlorides, but I don't know of any with BOTH. This would
suggest, e.g., the board is HASLed with a Br- flux (common) and soldered
with a Cl- one (also common) and insufficiently washed in between. Of
course, the bromine could also come from the board itself (flame
retardant), if your measurement process would allow it to be leached
out. As for nitrates, and more especially, nitrites, I cannot imagine
where they came from. Neither are anions commonly used in electronics,
to the best of my knowledge. Is there any possibility that the boards
could become contaminated after they were put in service.
Nitrates/nitrites are commonly used in agriculture and meat processing,
as well as various chemical processes, and are also common in the gases
released after the combustion of explosives and rocket fuels.
It could also be helpful to know what cations were found on the boards,
as well.
OK: the practicalities. If you seek a reasonable reliability with
"no-clean" soldering, firstly, you must routinely check incoming bare
boards for ionic contamination. Here, it is possible to set up an
in-house standard, and I would suggest that 0.5 µg/cm2 eq. NaCl would
not be exceptionally severe. Then, make sure there is no process within
your own factory which would introduce further ionic contamination,
other than the flux itself. Then the flux itself should come under
suspicion. RMA fluxes are perhaps not the best for "no-clean" processes:
they were not designed for this and some of them do leave residues which
contain fairly high halide levels. Personally, I would plump for a
low-residue non-rosin flux. In all cases, I would qualify the
post-solder flux residues with ECMR testing and, for critical circuits,
SIR testing, before adopting ANY flux.
Of course, if the contaminants reach the circuits in service, then you
need additional protection and, possibly, even cleaning and conformal
coating.
Now for your basic question. Post-solder (with "no-clean" chemistry)
ionic contamination testing CAN be useful, but only as a means of
process control. The MO is simple. When your process is working at its
optimum, with clean incoming boards and components, measure, say, 50
identical boards and calculate the mean and standard deviation of the
results (the SD should be quite narrow, say, < 10% of the mean). These
will be your baseline. Repeat for all your different circuits. In
subsequent production, take hourly samples, measure them, and check that
they fall well within the statistical probability of your baseline
measurements. If they consistently fall outside, IN EITHER DIRECTION,
for that type of circuit, then your fluxing/soldering process has gone
off kilter and corrective action may be required. Note that the absolute
values of the means are meaningless (no pun intended) and bear no
correlation to the reliability.
Hope this helps.
Brian
YH Koh wrote:
>
> To TechNet,
>
> Wondering if there is a specifcation to indicate the limit of ionic
> contamination for an after reflow boards. Understand that the amount of the
> flux activator remain on the boards is depending on the amount of solder
> joints on the boards. So, is there a criteria to address the amount of
> ionic versus the pads area or other related criterias?
>
> We are currently having corrosion on the board (after 1 year of application
> in the field). The flux we are using are no clean RMA flux. After
> extracted the flux remnant from the boards and subjected for Capillary
> Electrophoresis (CE-MS) test, we found high amount of bromide, chloride,
> nitrite and nitrate. I am not sure if thease are the elements that caused
> the corrosion.
>
> >From here, I am not sure if it is practical to specify the ionic limit on
> the after reflow boards? Or should continue to work on the driven factor of
> the corrosion like water, voltage, electromigration etc?
>
> Appreciate any inputs.
>
> Best Regards,
> YH Koh
>
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Date: Wed, 17 Apr 2002 17:43:21 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: pedantry
X-To: Brian Ellis <[log in to unmask]>
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
Brian,
You make a good point, I think. Many people seem talk about CTE almost as
if it's a constant in all directions. Yet it is important to know that, and
when, something expands more in one direction than in others, and by how
much. Is this lack of precision laziness, lack of awareness or complacency,
I wonder. Pedants rule, I say!
Peter
Brian Ellis
<b_ellis@PROTO To: [log in to unmask]
NIQUE.COM> cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
Sent by: Aero/ST Group)
TechNet Subject: Re: [TN] Cracking Chip Resistors
<[log in to unmask]
RG>
04/17/02 02:04
PM
Please respond
to "TechNet
E-Mail
Forum.";
Please respond
to Brian Ellis
Peter
If you wish to be really pedantic, how about LCTE, as opposed to VCTE (I
learnt both of these at school, about 60 years ago)? You may think the
volume coefficient is the cube of the linear, but 'tis not, necessarily.
In amorphous molecular structures, it usually is, but it is rarely the
case in morphous ones, as X, Y and Z LCTEs are rarely the same (take
FR-4 as one example).
Brian
Dave Hillman wrote:
>
> Hi folks! I have ran into a problem which has me baffled and the extra 20
> ounces of Coke I consumed this morning didn't bring about any better
> thought clarity so I would like to bounce the problem off the minds of
> TechNet. I have been attempting to hand solder a chip resistor (50 x 100)
> but have immediate cracking of the resistor across the width of the
> component. The resistor is either Aluminum Nitride or BeO (I'm still
trying
> to find out which material). And yes, we are using proper soldering
> technique(s) and the resistor pad geometries are our standard dimensions.
I
> know that the typical resistor body material is Alumina. Has anyone had
> good or bad experiences in hand soldering AlN or BeO resistors? Have I
run
> into a material flexural strength issue?
>
> Dave Hillman
> Rockwell Collins
> [log in to unmask]
>
>
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Date: Wed, 17 Apr 2002 12:06:01 +0200
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Busko, Wolfgang" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Busko, Wolfgang" <[log in to unmask]>
Subject: =?iso-8859-1?Q?-_Off_Topic-_=2E=2E=2E_you=B4ve_been_a_wonderfu?=
=?iso-8859-1?Q?l_audience_=2E=2E=2E_?=
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Hi All,
=B4T is my last one before the computer is shut down and my account =
will be
deleted here.
Just don=B4t wonna leave without saying " by folks", seeya maybe.
... you=B4ve been a wonderful audience ...=20
.... and a bunch of great guys, really !!!!
Wolfgang
=20
=09
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Date: Wed, 17 Apr 2002 06:49:50 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Creswick, Steven" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Creswick, Steven" <[log in to unmask]>
Subject: Re: Cracking Chip Resistors
X-To: "[log in to unmask]" <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Wow! Thanks!
I feel enlightened!
So who says you can't teach an old dog (fart) new tricks? .... well, at
least try...
Steve
-----Original Message-----
From: [log in to unmask] [mailto:[log in to unmask]]
Sent: Tuesday, April 16, 2002 11:29 PM
To: [log in to unmask]
Subject: Re: [TN] Cracking Chip Resistors
It changed when the pedants took over and demanded greater perceived
precision through change of emphasis. CTE is deemed to be more
scientifically correct than TCE (so my teach told me many moons ago (NPI)).
TCE = Thermal Co-efficient of Expansion as opposed to any other
co-efficient of expansion, while
CTE = Co-efficient of Thermal Expansion as opposed to a co-efficient of
expansion caused by anything else.
The idea is to place the emphasis on the 'Co-efficient' bit, not on the
'Thermal' bit ... or something.
I'm just bored and just wanted to say something, OK?
Peter
Earl Moon
<[log in to unmask] To: [log in to unmask]
M.COM> cc: (bcc: DUNCAN Peter/Asst
Prin Engr/ST
Sent by: Aero/ST Group)
TechNet Subject: Re: [TN] Cracking Chip
Resistors
<[log in to unmask]
ORG>
04/17/02
01:28 AM
Please
respond to
"TechNet
E-Mail
Forum.";
Please
respond to
Earl Moon
Steve,
You really are an old timer. TCE instead of CTE? I still use the former.
When did it all change?
Earl
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Date: Wed, 17 Apr 2002 06:03:42 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re:
=?iso-8859-1?Q?-_Off_Topic-_=2E=2E=2E_you=B4ve_been_a_wonderfu?=
=?iso-8859-1?Q?l_audience_=2E=2E=2E_?=
X-To: [log in to unmask]
Wolfgang, my friend, of what do you speak?
Earl
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Date: Wed, 17 Apr 2002 06:07:53 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Cracking Chip Resistors
X-To: [log in to unmask]
and with Brian's help, I'm even starting to see light, or absence of it,
again. CTE? Has a good ring to it after rejecting it over 30 years. Ah, 1972
- what/who was I doing then, or they me? Could have been Sally Perkinson or
was it Vicky Prince, or was it both. Certainly not paying as much attention
to work as them.
MoonMan
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Date: Wed, 17 Apr 2002 07:56:08 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Rob Legg <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Rob Legg <[log in to unmask]>
Subject: Re: IPC SMT FOOTPRINT DESIGN GUIDLINES VS SUPPLIERS
X-To: [log in to unmask]
MIME-Version: 1.0
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The well is always happy to hear from a satisfied customer.
RL
----- Original Message -----
From: "Werner Engelmaier" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Tuesday, April 16, 2002 11:27 PM
Subject: Re: [TN] IPC SMT FOOTPRINT DESIGN GUIDLINES VS SUPPLIERS
> Ahh Earl,
> You can lead the horse [or is it ass] to the water, but you cannot make it
> drink.
>
> Werner
>
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Date: Wed, 17 Apr 2002 07:27:23 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Jack C. Olson" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Jack C. Olson" <[log in to unmask]>
Subject: Re: IPC SMT FOOTPRINT DESIGN GUIDLINES VS SUPPLIERS
X-To: [log in to unmask]
MIME-Version: 1.0
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Yes, I agree, and I have a confession to make as well...
I asked an IPC dude (Gary) about the difference between the
registered pattern dimensions and the calculated results,
and he said the calculator was in the process of a significant
re-design, but then I never heard anything about it since then.
(Does anyone know if there is a newer version on the way?
or is that what we are using now?)
The confession is, sometimes I am lazy and just look it up
in my SMTplus library, since they have every SMT part under
the sun. (my original post said "If I was starting OVER again")
After being frustrated by seeing 4-5 "suggested" patterns
for the same darn part from every vendor and data sheet,
I still maintain it is preferable to START with a standard.
As for your statement about "permutations in board design,
materials, assembly processes, component package styles,
materials and contents, operating conditions..."
well, this getting into the area where your knowledge and
experience is leading you towards a modification, which is
GREAT!, All I say is DOCUMENT THE REASON so the next bozo
to come along won't change it and lose all the benefit of
your work.
And I still stick by my statement that if you DON'T know
what you are doing, USE A STANDARD, don't use a component
data sheet.
Jack
[log in to unmask]
16Apr2002 08:02 PM
To: "TechNet E-Mail Forum." <[log in to unmask]>
"Jack C. Olson" <[log in to unmask]>
cc:
Subject: Re: [TN] IPC SMT FOOTPRINT DESIGN GUIDLINES VS SUPPLIERS
Retain Until: 05/16/2002 Retention Category: G90 - Information and Reports
Caterpillar Confidential: Green
Jack,
I had great difficulty in getting land patterns to "conform to IPC". If you
have a registered land pattern and it's in IPC-SM-782, but you then
check/compare it using the calculator/formula in the same spec, you get two
different results. Where is the conformity, I ask? Also, there are more
instances of no-land-pattern-information-availability than there are
guidelines or recommendations. As was said, component manufacturers do
their own thing, maybe loosely centred around "standard" package types, but
they often differ enough from the standard to make one suspicious about
using the "standard" land patterns for them.
As I said (provocatively) in my last reply posting, there are too many
permutations in board design, materials, assembly processes, component
package styles, materials and contents, operating conditions and so on, to
have a concise "standard" for all occasions - unless each parameter in the
overall CCA universe becomes standard/fixed. What we have are workable
compromises that suit most groups of parameters. It's towards the more
extreme CCA applications and environments that these compromises start to
break down.
I believe there's still a ways to go before 'art' changes to 'science'.
Peter
"Jack C.
Olson" To: [log in to unmask]
<OLSON_JACK_C cc: (bcc: DUNCAN Peter/Asst
Prin Engr/ST
@CAT.COM> Aero/ST Group)
Sent by: Subject: Re: [TN] IPC SMT
FOOTPRINT DESIGN
TechNet GUIDLINES VS SUPPLIERS
<[log in to unmask]
ORG>
04/16/02
10:53 PM
Please
respond to
"TechNet
E-Mail
Forum.";
Please
respond to
"Jack C.
Olson"
Great question!
We have wasted SO much time designing custom libraries
for specific vendors, its to the point of being ridiculous.
Here is what I would do if I was starting over:
- Design to IPC unless I had a GOOD reason not to.
- NEVER use a component data sheet. can't trust 'em.
- If a vendor had a reason supported by SCIENTIFIC
DATA to suggest a change, DOCUMENT IT!
The ideal (in my opinion) would be to say "All footprints
conform to IPC with the exception of..." and for those
exceptions explain WHY YOU CHANGED IT. (including
high density versions, wave solder alternates, whatever)
best wishes,
Jack
-----Original Message-----
From: Earl Moon [mailto:[log in to unmask]]
Sent: Sunday, April 14, 2002 2:03 PM
To: [log in to unmask]
Subject: [TN] IPC SMT FOOTPRINT DESIGN GUIDLINES VS SUPPLIERS
Folks,
Just a simple question really. How many folks use IPC SMT footprint
guidelines compared with supplier recommendations? There often is quite a
difference. As everyone on this planet uses IPC acceptance criteria, why
shouln't everyone use IPC design guidelines but for component supplier
liability issues?
MoonMan
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Date: Wed, 17 Apr 2002 07:38:43 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Jack C. Olson" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Jack C. Olson" <[log in to unmask]>
Subject: Re: Immersion Silver
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
The PCD magazine list went down before I could get an
answer to this question, does anyone have experience
with silver and contact switches?
==============================================
Most sources say a silver surface will not be solderable
after a month or so unprotected. (Even in a baggie it will
be okay a year later?)
Anyway, you say it is good for switches, which would solve
some of our hard gold plating problems.
But I would think the "unsolderability" of the aged silver
surface (unprotected in the unit and tarnished?) would
affect the reliability of the switches, wouldn't it?
Jack
Rob Mongey <[log in to unmask]>@freelists.org
4Apr2002 06:08 AM
Please respond to [log in to unmask]
Sent by: [log in to unmask]
To: [log in to unmask]
cc:
Subject: [pcdlist] Re: Immersion Silver
Retain Until: 05/04/2002 Retention Category: G90 - Information and Reports
Caterpillar Confidential: Green
Hi all,
Good to see Immersion Silver is starting to take off. We've been using
it
in here for about two years, and it is now our prefered board finish (We
get silver finish unless we specify differently.) More common useage will
mean that maybe more Far Eastern shops will start supplying it.
We started to use Silver because it is so adaptable to what we need
our
PCB surface finish to do, namely:
1. Good solderability. (Silver excels at this, ask any vendor).
2. Flatness for fine pitch SMT. (Silver is as flat, if not flatter than
Gold)
3. Mechanical strength for carbon pill switch contacts / Elastomer
contacts. ( Flash Gold is weak, and hard Gold gives SMT solderability
problems)
4. Stability for compression power contacts. (We have power contacts on our
PCBs that mate to battery contacts via a spring compression. We found that
the nickel under gold can cause problems with electrochemical migration
toward our battery contact.)
Immersion silver is the most suitable choice that can do all four. I'd use
gold as an alternative, but we'd have to compromise our designs somewhat.
We specify our Silver finish as 0.1 Microns Min to 0.2 Microns Max, over
bare copper. Anyone else do it differently? Or do we trust our board shops?
:)
Regards,
Rob Mongey.
CAD Technician.
Robert Mongey <[log in to unmask]> Tel : +353 (0)91 774300
Bio Medical Research Direct : +353 (0)91 774338
BMR House, Fax : +353 (0)91 774302
Parkmore Business Park West, Mobile : +353 (0)87 2485262
Galway
Rep of Ireland.
---------------------------------------------------------------------------------
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Date: Wed, 17 Apr 2002 08:02:58 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
[log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Cracking Chip Resistors
X-To: [log in to unmask]
MIME-Version: 1.0
Content-type: text/plain; charset="us-ascii"
Brian Ellis quips:
Are you sure Doug didn't lace your Coke with Mountain Dew?
**Brian,
Some things just are NOT done. Dave and I are goofy enough by ourselves
without chemically enhancement...................
---------------------------------------------------------------------------------
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Date: Wed, 17 Apr 2002 10:16:49 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"WEEKES, MICHAEL HS-SNS" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "WEEKES, MICHAEL HS-SNS" <[log in to unmask]>
Subject: Re: Immersion Silver
X-To: "Jack C. Olson" <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain
There must be some reason why less than 3% of the world has moved toward
immersion silver. Why doesn't HASL or NiGold work for your application?
Mike
-----Original Message-----
From: Jack C. Olson [mailto:[log in to unmask]]
Sent: Wednesday, April 17, 2002 7:39 AM
To: [log in to unmask]
Subject: Re: [TN] Immersion Silver
The PCD magazine list went down before I could get an
answer to this question, does anyone have experience
with silver and contact switches?
==============================================
Most sources say a silver surface will not be solderable
after a month or so unprotected. (Even in a baggie it will
be okay a year later?)
Anyway, you say it is good for switches, which would solve
some of our hard gold plating problems.
But I would think the "unsolderability" of the aged silver
surface (unprotected in the unit and tarnished?) would
affect the reliability of the switches, wouldn't it?
Jack
Rob Mongey <[log in to unmask]>@freelists.org
4Apr2002 06:08 AM
Please respond to [log in to unmask]
Sent by: [log in to unmask]
To: [log in to unmask]
cc:
Subject: [pcdlist] Re: Immersion Silver
Retain Until: 05/04/2002 Retention Category: G90 - Information and Reports
Caterpillar Confidential: Green
Hi all,
Good to see Immersion Silver is starting to take off. We've been using
it
in here for about two years, and it is now our prefered board finish (We
get silver finish unless we specify differently.) More common useage will
mean that maybe more Far Eastern shops will start supplying it.
We started to use Silver because it is so adaptable to what we need
our
PCB surface finish to do, namely:
1. Good solderability. (Silver excels at this, ask any vendor).
2. Flatness for fine pitch SMT. (Silver is as flat, if not flatter than
Gold)
3. Mechanical strength for carbon pill switch contacts / Elastomer
contacts. ( Flash Gold is weak, and hard Gold gives SMT solderability
problems)
4. Stability for compression power contacts. (We have power contacts on our
PCBs that mate to battery contacts via a spring compression. We found that
the nickel under gold can cause problems with electrochemical migration
toward our battery contact.)
Immersion silver is the most suitable choice that can do all four. I'd use
gold as an alternative, but we'd have to compromise our designs somewhat.
We specify our Silver finish as 0.1 Microns Min to 0.2 Microns Max, over
bare copper. Anyone else do it differently? Or do we trust our board shops?
:)
Regards,
Rob Mongey.
CAD Technician.
Robert Mongey <[log in to unmask]> Tel : +353 (0)91 774300
Bio Medical Research Direct : +353 (0)91 774338
BMR House, Fax : +353 (0)91 774302
Parkmore Business Park West, Mobile : +353 (0)87 2485262
Galway
Rep of Ireland.
----------------------------------------------------------------------------
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Date: Wed, 17 Apr 2002 10:24:06 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Cracking Chip Resistors
X-To: "Creswick, Steven" <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit
Yes
----- Original Message -----
From: "Creswick, Steven" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Wednesday, April 17, 2002 6:49 AM
Subject: Re: [TN] Cracking Chip Resistors
> Wow! Thanks!
>
> I feel enlightened!
>
> So who says you can't teach an old dog (fart) new tricks? .... well, at
> least try...
>
> Steve
>
> -----Original Message-----
> From: [log in to unmask] [mailto:[log in to unmask]]
> Sent: Tuesday, April 16, 2002 11:29 PM
> To: [log in to unmask]
> Subject: Re: [TN] Cracking Chip Resistors
>
>
> It changed when the pedants took over and demanded greater perceived
> precision through change of emphasis. CTE is deemed to be more
> scientifically correct than TCE (so my teach told me many moons ago
(NPI)).
>
> TCE = Thermal Co-efficient of Expansion as opposed to any other
> co-efficient of expansion, while
> CTE = Co-efficient of Thermal Expansion as opposed to a co-efficient of
> expansion caused by anything else.
>
> The idea is to place the emphasis on the 'Co-efficient' bit, not on the
> 'Thermal' bit ... or something.
>
> I'm just bored and just wanted to say something, OK?
>
> Peter
>
>
>
>
> Earl Moon
> <[log in to unmask] To: [log in to unmask]
> M.COM> cc: (bcc: DUNCAN Peter/Asst
> Prin Engr/ST
> Sent by: Aero/ST Group)
> TechNet Subject: Re: [TN] Cracking
Chip
> Resistors
> <[log in to unmask]
> ORG>
>
>
> 04/17/02
> 01:28 AM
> Please
> respond to
> "TechNet
> E-Mail
> Forum.";
> Please
> respond to
> Earl Moon
>
>
>
>
>
>
> Steve,
>
> You really are an old timer. TCE instead of CTE? I still use the former.
> When did it all change?
>
> Earl
>
> --------------------------------------------------------------------------
--
> -----
>
> Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
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> information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700
> ext.5315
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> -----
>
>
>
>
>
> [This e-mail is confidential and may also be privileged. If you are not
the
> intended recipient, please delete it and notify us immediately; you should
> not copy or use it for any purpose, nor disclose its contents to any other
> person. Thank you.]
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SET
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Date: Wed, 17 Apr 2002 09:32:05 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Cracking Chip Resistors
X-To: [log in to unmask]
Doug,
You and Dave have, as some of us others, as sacred thing going and I agree.
What I don't believe is that last comment you made. You don't get that goofy
without benefit of some "unatural" substance. I, myself, am pure.
MoonMan
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Date: Wed, 17 Apr 2002 07:48:51 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Frank Kimmey <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Frank Kimmey <[log in to unmask]>
Subject: Re: IPC SMT FOOTPRINT DESIGN GUIDLINES VS SUPPLIERS
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
I've watched , I've waited and now I have to add my two cents.
IPC-782 is a great place to start. These land patterns work (though not
always perfectly) and are simple to understand as a good starting place for
well documented library creation. The difference between the standard and
the calculator is, I think that the standard is made up of process proven
design where the calculator is just that, a calculation of acceptable (key
wording - acceptable not preferred) extension from termination size to allow
an usable solder joint. My experience has been that the calculator usually
creates a slightly smaller footprint than the standard recommends.
Back to the original subject:
I have always recommended that for library creation the following inputs in
order of importance:
1. Process proven footprints
modifications of existing footprints that best fit the process being
used (determined by trial and error/DOE)
2. IPC-782
this is an industry standard
3. SMT+
the folks at SMT Plus have done a good job but don't always fit all
processes
4. Purchased library sets
some are good , some are good starting places, some are bad
5. Creations
using the IPC calculator or calculating from scratch using IPC-782
recommendations and DOE.
6. Software libraries
a starting place to create better symbols from
7. Manufacturers data sheets
I don't trust these well enough to use except as a verification of
my calculations. Unfortunately data sheets are all to often WRONG.
Almost done here. I adamantly agree the most important step while finding a
good land pattern is to document what was done. All to often a change in
personnel, vendors or suppliers can cause an existing footprint to become
non-optimal and only good documentation will keep mistakes from having to be
repeated.
Lastly, though I personally think good PCB design is an art more than a
science I also agree that great PCB design requires that that art be a blend
of good science, communication, common sense and documentation.
Hope this makes sense and helps.
Thanks,
FNK
Frank N Kimmey, C.I.D.+
Senior PCB Designer
Powerwave Technologies
PH. 916-941-3159
Fax 916-941-3195
-----Original Message-----
From: Jack C. Olson [mailto:[log in to unmask]]
Sent: Wednesday, April 17, 2002 5:27 AM
To: [log in to unmask]
Subject: Re: [TN] IPC SMT FOOTPRINT DESIGN GUIDLINES VS SUPPLIERS
Yes, I agree, and I have a confession to make as well...
I asked an IPC dude (Gary) about the difference between the
registered pattern dimensions and the calculated results,
and he said the calculator was in the process of a significant
re-design, but then I never heard anything about it since then.
(Does anyone know if there is a newer version on the way?
or is that what we are using now?)
The confession is, sometimes I am lazy and just look it up
in my SMTplus library, since they have every SMT part under
the sun. (my original post said "If I was starting OVER again")
After being frustrated by seeing 4-5 "suggested" patterns
for the same darn part from every vendor and data sheet,
I still maintain it is preferable to START with a standard.
As for your statement about "permutations in board design,
materials, assembly processes, component package styles,
materials and contents, operating conditions..."
well, this getting into the area where your knowledge and
experience is leading you towards a modification, which is
GREAT!, All I say is DOCUMENT THE REASON so the next bozo
to come along won't change it and lose all the benefit of
your work.
And I still stick by my statement that if you DON'T know
what you are doing, USE A STANDARD, don't use a component
data sheet.
Jack
[log in to unmask]
16Apr2002 08:02 PM
To: "TechNet E-Mail Forum." <[log in to unmask]>
"Jack C. Olson" <[log in to unmask]>
cc:
Subject: Re: [TN] IPC SMT FOOTPRINT DESIGN GUIDLINES VS SUPPLIERS
Retain Until: 05/16/2002 Retention Category: G90 - Information and Reports
Caterpillar Confidential: Green
Jack,
I had great difficulty in getting land patterns to "conform to IPC". If you
have a registered land pattern and it's in IPC-SM-782, but you then
check/compare it using the calculator/formula in the same spec, you get two
different results. Where is the conformity, I ask? Also, there are more
instances of no-land-pattern-information-availability than there are
guidelines or recommendations. As was said, component manufacturers do
their own thing, maybe loosely centred around "standard" package types, but
they often differ enough from the standard to make one suspicious about
using the "standard" land patterns for them.
As I said (provocatively) in my last reply posting, there are too many
permutations in board design, materials, assembly processes, component
package styles, materials and contents, operating conditions and so on, to
have a concise "standard" for all occasions - unless each parameter in the
overall CCA universe becomes standard/fixed. What we have are workable
compromises that suit most groups of parameters. It's towards the more
extreme CCA applications and environments that these compromises start to
break down.
I believe there's still a ways to go before 'art' changes to 'science'.
Peter
"Jack C.
Olson" To: [log in to unmask]
<OLSON_JACK_C cc: (bcc: DUNCAN Peter/Asst
Prin Engr/ST
@CAT.COM> Aero/ST Group)
Sent by: Subject: Re: [TN] IPC SMT
FOOTPRINT DESIGN
TechNet GUIDLINES VS SUPPLIERS
<[log in to unmask]
ORG>
04/16/02
10:53 PM
Please
respond to
"TechNet
E-Mail
Forum.";
Please
respond to
"Jack C.
Olson"
Great question!
We have wasted SO much time designing custom libraries
for specific vendors, its to the point of being ridiculous.
Here is what I would do if I was starting over:
- Design to IPC unless I had a GOOD reason not to.
- NEVER use a component data sheet. can't trust 'em.
- If a vendor had a reason supported by SCIENTIFIC
DATA to suggest a change, DOCUMENT IT!
The ideal (in my opinion) would be to say "All footprints
conform to IPC with the exception of..." and for those
exceptions explain WHY YOU CHANGED IT. (including
high density versions, wave solder alternates, whatever)
best wishes,
Jack
-----Original Message-----
From: Earl Moon [mailto:[log in to unmask]]
Sent: Sunday, April 14, 2002 2:03 PM
To: [log in to unmask]
Subject: [TN] IPC SMT FOOTPRINT DESIGN GUIDLINES VS SUPPLIERS
Folks,
Just a simple question really. How many folks use IPC SMT footprint
guidelines compared with supplier recommendations? There often is quite a
difference. As everyone on this planet uses IPC acceptance criteria, why
shouln't everyone use IPC design guidelines but for component supplier
liability issues?
MoonMan
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Date: Wed, 17 Apr 2002 08:22:27 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Dan R. Johnson" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Dan R. Johnson" <[log in to unmask]>
Subject: Re: IPC SMT FOOTPRINT DESIGN GUIDLINES VS SUPPLIERS
MIME-version: 1.0
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Ok, I've been lurking on this one. Since idle hands wind up filling out
forms at the unemployment office I have volunteered to take on some projects
outside my normal scope of responsibility. (Darn that ol' mortgage payment.)
Aside from maintaining our website, helping with trade show logistics, and
LAN support, I have a project to publish suppliers recommended layouts for
all our parts. From what I'm hearing most of you would throw away my
recommendation and start over again. I had great plans to milk this with
test PCB's, sample runs, and a stunning excel report to illustrate the
results to management.
Here are my questions,
Assume that IPC doesn't have and never will have a standards for my product.
(We don't account for a rounding error in the percentage of active
components supplied to the electronics industry).
What supporting evidence would convince you to use my recommendations?
If I supplied the patterns in electronic format would you be more likely to
use them? Hopefully you like this one 'cause then I get to figure out how to
set up and FTP site to down-load files.
Dan
P.S.: I heard rumors there are seasons other than winter, any truth to that?
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Date: Wed, 17 Apr 2002 10:22:24 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Jack C. Olson" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Jack C. Olson" <[log in to unmask]>
Subject: Re: Immersion Silver
X-To: "WEEKES, MICHAEL HS-SNS" <[log in to unmask]>
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
Hmmm,
Well, at some point in EVERY new technology it was used by less
than 3% of the world, eh? Guess I'm just a trailblazer....
naw, just kiddin ya.
I subscribed to a magazine called Circuitree, and the last issue
came bundled with another publication called "The Board Authority"
which has some very well written (and well researched!) articles
on alternate finishes. I can't see any downside to using silver
in our applications, and I've looked all through the archives for
Technet, DesignerCouncil and PCDlist forums, still no show-stoppers,
so we tried it for the first time on our last design. Yes, HASL and
NiGold do work fine, but maybe we can get the same functionality
for cheaper, and do our fab vendor a favor in the process, since
they seem to prefer it (less steps? more reliable? not sure) maybe
the fab guys can answer that one....
Jack
"WEEKES, MICHAEL HS-SNS" <[log in to unmask]>
17Apr2002 09:16 AM
To: "'TechNet E-Mail Forum.'" <[log in to unmask]>
"'Jack C. Olson'" <[log in to unmask]>
cc:
Subject: RE: [TN] Immersion Silver
Retain Until: 05/17/2002 Retention Category: G90 - Information and Reports
Caterpillar Confidential: Green
There must be some reason why less than 3% of the world has moved toward
immersion silver. Why doesn't HASL or NiGold work for your application?
Mike
-----Original Message-----
From: Jack C. Olson [mailto:[log in to unmask]]
Sent: Wednesday, April 17, 2002 7:39 AM
To: [log in to unmask]
Subject: Re: [TN] Immersion Silver
The PCD magazine list went down before I could get an
answer to this question, does anyone have experience
with silver and contact switches?
==============================================
Most sources say a silver surface will not be solderable
after a month or so unprotected. (Even in a baggie it will
be okay a year later?)
Anyway, you say it is good for switches, which would solve
some of our hard gold plating problems.
But I would think the "unsolderability" of the aged silver
surface (unprotected in the unit and tarnished?) would
affect the reliability of the switches, wouldn't it?
Jack
Rob Mongey <[log in to unmask]>@freelists.org
4Apr2002 06:08 AM
Please respond to [log in to unmask]
Sent by: [log in to unmask]
To: [log in to unmask]
cc:
Subject: [pcdlist] Re: Immersion Silver
Retain Until: 05/04/2002 Retention Category: G90 - Information and Reports
Caterpillar Confidential: Green
Hi all,
Good to see Immersion Silver is starting to take off. We've been using
it
in here for about two years, and it is now our prefered board finish (We
get silver finish unless we specify differently.) More common useage will
mean that maybe more Far Eastern shops will start supplying it.
We started to use Silver because it is so adaptable to what we need
our
PCB surface finish to do, namely:
1. Good solderability. (Silver excels at this, ask any vendor).
2. Flatness for fine pitch SMT. (Silver is as flat, if not flatter than
Gold)
3. Mechanical strength for carbon pill switch contacts / Elastomer
contacts. ( Flash Gold is weak, and hard Gold gives SMT solderability
problems)
4. Stability for compression power contacts. (We have power contacts on our
PCBs that mate to battery contacts via a spring compression. We found that
the nickel under gold can cause problems with electrochemical migration
toward our battery contact.)
Immersion silver is the most suitable choice that can do all four. I'd use
gold as an alternative, but we'd have to compromise our designs somewhat.
We specify our Silver finish as 0.1 Microns Min to 0.2 Microns Max, over
bare copper. Anyone else do it differently? Or do we trust our board shops?
:)
Regards,
Rob Mongey.
CAD Technician.
Robert Mongey <[log in to unmask]> Tel : +353 (0)91 774300
Bio Medical Research Direct : +353 (0)91 774338
BMR House, Fax : +353 (0)91 774302
Parkmore Business Park West, Mobile : +353 (0)87 2485262
Galway
Rep of Ireland.
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Date: Wed, 17 Apr 2002 10:25:44 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: IPC SMT FOOTPRINT DESIGN GUIDLINES VS SUPPLIERS
X-To: [log in to unmask]
Damn good input.
I have chosen a path starting with IPC. Then my strategy, as always, is to
seek concurrent input from my qualified assembler. If disagreement is
forthcoming, we will work that out, concurrently, on whatever basis possibly
using supplier recommended footprints, etc.
As initial quality is to be verified using IPC 610 requirements, I demand
correlation between selected design rules and process management effects. As
I cannot lead my broken horse to water to make it drink, I will not have the
reliability confirmation I need. Unfortunately, that will come from the
field and the customer we supply.
Thanks for good stuff,
MoonMan
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Date: Wed, 17 Apr 2002 10:32:11 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: IPC SMT FOOTPRINT DESIGN GUIDLINES VS SUPPLIERS
X-To: [log in to unmask]
Man Dan,
You got a good one going. I just replied to Frank about my plan. So many
ways to go and dealing with designers practicing their "art" is tough.
Dealing with designers having only an objective approach is much better. Are
there any out there and is it possible to be totally objective? Of course
not, but I always try to hedge my bet in favor of the odds.
Concerning the seasons, it was a bloody hot 85 degrees here after not having
been over 55 the days before. Hell, it must be IPC 782 causing all this
stuff, but a good place to start as has been said so often,
Earl
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Date: Wed, 17 Apr 2002 08:59:29 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Dan R. Johnson" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Dan R. Johnson" <[log in to unmask]>
Subject: naive questions
MIME-version: 1.0
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I have a couple of naive questions,
How do you determine the overall increase in copper thickness for a given thickness of through hole plating?
What are the relationships between overall plate thickness, hole plate thickness, voltage, current, and time?
I assume these all change in the specifics
I am not now nor ever have been a member of the PCB manufacturing community, this is purely a matter of academic interest. Perhaps some of the gurus of FR-4 out there can help me.
Thanks for helping satisfy my thirst for knowledge,
Dan
--Boundary_(ID_EUHJphs/UFyZTaFJX5ttDQ)
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<META content="MSHTML 6.00.2715.400" name=GENERATOR>
<STYLE></STYLE>
</HEAD>
<BODY bgColor=#ffffff>
<DIV><FONT face=Arial size=2>I have a couple of naive questions, </FONT></DIV>
<DIV><FONT face=Arial size=2>How do you determine the overall increase in copper
thickness for a given thickness of through hole plating?</FONT></DIV>
<DIV><FONT face=Arial size=2>What are the relationships between overall plate
thickness, hole plate thickness, voltage, current, and time?</FONT></DIV>
<DIV><FONT face=Arial size=2>I assume these all change in the
specifics</FONT></DIV>
<DIV><FONT face=Arial size=2>I am not now nor ever have been a member of the PCB
manufacturing community, this is purely a matter of academic interest. Perhaps
some of the gurus of FR-4 out there can help me.</FONT></DIV>
<DIV><FONT face=Arial size=2></FONT> </DIV>
<DIV><FONT face=Arial size=2>Thanks for helping satisfy my thirst for
knowledge,</FONT></DIV>
<DIV><FONT face=Arial size=2>Dan</FONT></DIV></BODY></HTML>
--Boundary_(ID_EUHJphs/UFyZTaFJX5ttDQ)--
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Date: Wed, 17 Apr 2002 11:03:09 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: naive questions
X-To: [log in to unmask]
Very ggod question for naive Dan
I use a ratio thst has some validity though results vary with process
management and requirements as well as the process itself. If I specify one
mil of copper plating in a typical hole wall, whatever that is now, I expect
to verify about 1.2 mils on the board surface. So, if I start with .5 oz. Cu
folil on the board outer layers, I will see about 1.9 mils total for traces,
as an example, on the surface. There's some math in there somewhere and Rudy
probably will provide the real answer.
Earl
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Date: Wed, 17 Apr 2002 11:17:01 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Immersion Silver
X-To: "Jack C. Olson" <[log in to unmask]>
Used it and specified it. Works great. Still have some bare boards from 1995
and solder them once in awhile to see and so far they still solder.
Dave Hillman is the guru on this subject. Where is he when you need him.
Must be coking out with Doug Dewhurst.
MoonMan
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Date: Wed, 17 Apr 2002 11:55:35 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Don Vischulis <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Don Vischulis <[log in to unmask]>
Subject: Re: naive questions
X-To: "Dan R. Johnson" <[log in to unmask]>
In-Reply-To: <00d501c1e628$db8b3be0$6401a8c0@dan>
MIME-Version: 1.0
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Dan
To add to Earl's reply, in less well managed processes, the surface to hole
ratio can approach 1.4. The ratio depends on almost every variable in the
plating process: current density, acid to copper ratio, brightener system,
hole aspect ratio and rectifier type (DC vs. pulse) to name some of the more
important ones. Voltage is usually not controlled and time is used to
control the average plating thickness. In general, higher current (for a
given design) results in increased thickness variations across the panel,
within the holes, and affects the surface to hole thickness ratio. Other
factors like plating tank design, anode length/placement, and tank agitation
also factor into the discussion.
I've probably told you more than necessary, but optimizing and maintaining
the electroplating process is a complex task that creates a need for many
process engineers.
Don Vischulis
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Dan R. Johnson
Sent: Wednesday, April 17, 2002 10:59 AM
To: [log in to unmask]
Subject: [TN] naive questions
I have a couple of naive questions,
How do you determine the overall increase in copper thickness for a given
thickness of through hole plating?
What are the relationships between overall plate thickness, hole plate
thickness, voltage, current, and time?
I assume these all change in the specifics
I am not now nor ever have been a member of the PCB manufacturing community,
this is purely a matter of academic interest. Perhaps some of the gurus of
FR-4 out there can help me.
Thanks for helping satisfy my thirst for knowledge,
Dan
------=_NextPart_000_0002_01C1E606.C88DE820
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charset="iso-8859-1"
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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META http-equiv=3DContent-Type content=3D"text/html; =
charset=3Diso-8859-1">
<META content=3D"MSHTML 6.00.2715.400" name=3DGENERATOR>
<STYLE></STYLE>
</HEAD>
<BODY bgColor=3D#ffffff>
<DIV><SPAN class=3D065344316-17042002><FONT face=3DArial color=3D#0000ff =
size=3D2>Dan</FONT></SPAN></DIV>
<DIV><SPAN class=3D065344316-17042002><FONT face=3DArial color=3D#0000ff =
size=3D2></FONT></SPAN> </DIV>
<DIV><SPAN class=3D065344316-17042002><FONT face=3DArial color=3D#0000ff =
size=3D2>To add=20
to Earl's reply, in less well managed processes, the surface to hole =
ratio can=20
approach 1.4. The ratio depends on almost every variable in the =
plating=20
process: current density, acid to copper ratio, brightener system, hole =
aspect=20
ratio and rectifier type (DC vs. pulse) to name some of the more =
important=20
ones. Voltage is usually not controlled and time is used to =
control the=20
average plating thickness. In general, higher current (for a given =
design)=20
results in increased thickness variations across the panel, within the =
holes,=20
and affects the surface to hole thickness ratio. Other factors =
like=20
plating tank design, anode length/placement, and tank agitation also =
factor into=20
the discussion.</FONT></SPAN></DIV>
<DIV><SPAN class=3D065344316-17042002><FONT face=3DArial color=3D#0000ff =
size=3D2></FONT></SPAN> </DIV>
<DIV><SPAN class=3D065344316-17042002><FONT face=3DArial color=3D#0000ff =
size=3D2>I've=20
probably told you more than necessary, but optimizing and maintaining =
the=20
electroplating process is a complex task that creates a need for many =
process=20
engineers.</FONT></SPAN></DIV>
<DIV><SPAN class=3D065344316-17042002><FONT face=3DArial color=3D#0000ff =
size=3D2></FONT></SPAN> </DIV>
<DIV><SPAN class=3D065344316-17042002><FONT face=3DArial color=3D#0000ff =
size=3D2>Don=20
Vischulis</FONT></SPAN></DIV>
<DIV><SPAN class=3D065344316-17042002></SPAN> </DIV>
<DIV class=3DOutlookMessageHeader dir=3Dltr align=3Dleft><FONT =
face=3DTahoma=20
size=3D2>-----Original Message-----<BR><B>From:</B> TechNet=20
[mailto:[log in to unmask]]<B>On Behalf Of </B>Dan R. =
Johnson<BR><B>Sent:</B>=20
Wednesday, April 17, 2002 10:59 AM<BR><B>To:</B>=20
[log in to unmask]<BR><B>Subject:</B> [TN] naive =
questions<BR><BR></FONT></DIV>
<DIV><FONT face=3DArial size=3D2>I have a couple of naive questions, =
</FONT></DIV>
<DIV><FONT face=3DArial size=3D2>How do you determine the overall =
increase in copper=20
thickness for a given thickness of through hole plating?</FONT></DIV>
<DIV><FONT face=3DArial size=3D2>What are the relationships between =
overall plate=20
thickness, hole plate thickness, voltage, current, and =
time?</FONT></DIV>
<DIV><FONT face=3DArial size=3D2>I assume these all change in the=20
specifics</FONT></DIV>
<DIV><FONT face=3DArial size=3D2>I am not now nor ever have been a =
member of the PCB=20
manufacturing community, this is purely a matter of academic interest. =
Perhaps=20
some of the gurus of FR-4 out there can help me.</FONT></DIV>
<DIV><FONT face=3DArial size=3D2></FONT> </DIV>
<DIV><FONT face=3DArial size=3D2>Thanks for helping satisfy my thirst =
for=20
knowledge,</FONT></DIV>
<DIV><FONT face=3DArial size=3D2>Dan</FONT></DIV></BODY></HTML>
------=_NextPart_000_0002_01C1E606.C88DE820--
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Date: Wed, 17 Apr 2002 13:00:53 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Wenger, George M." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Wenger, George M." <[log in to unmask]>
Subject: Re: Immersion Silver
MIME-Version: 1.0
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I think the obvious answer is that the other 97% of the rest of the =
world are waiting for someone to sign on the dotted line that there is =
nothing wrong with immersion silver, its reliable and and we'll never =
have trouble with it. The 3% who are using it have done their homework =
and aren't relying on someone else telling them it is okay. They have =
found out that immersion silver works at lest as well as other surface =
finished, is much flatter than HASL, isn't susceptable to "Black Pad", =
is as reliable as solder joints made to HASL or OSP boards, and the =
problems one can have with imemrsion silver can be handled.
Regards,
George
George M. Wenger (908)-546-4531 [log in to unmask]
Distinguished Member Technical Staff
Celiant Corporation, FMA Lab, 40 Technology Drive, NJ 07059
-----Original Message-----
From: Jack C. Olson [mailto:[log in to unmask]]
Sent: Wednesday, April 17, 2002 11:22 AM
To: [log in to unmask]
Subject: Re: [TN] Immersion Silver
Hmmm,
Well, at some point in EVERY new technology it was used by less
than 3% of the world, eh? Guess I'm just a trailblazer....
naw, just kiddin ya.
I subscribed to a magazine called Circuitree, and the last issue
came bundled with another publication called "The Board Authority"
which has some very well written (and well researched!) articles
on alternate finishes. I can't see any downside to using silver
in our applications, and I've looked all through the archives for
Technet, DesignerCouncil and PCDlist forums, still no show-stoppers,
so we tried it for the first time on our last design. Yes, HASL and
NiGold do work fine, but maybe we can get the same functionality
for cheaper, and do our fab vendor a favor in the process, since
they seem to prefer it (less steps? more reliable? not sure) maybe
the fab guys can answer that one....
Jack
"WEEKES, MICHAEL HS-SNS" <[log in to unmask]>
17Apr2002 09:16 AM
To: "'TechNet E-Mail Forum.'" <[log in to unmask]>
"'Jack C. Olson'" <[log in to unmask]>
cc:
Subject: RE: [TN] Immersion Silver
Retain Until: 05/17/2002 Retention Category: G90 - Information and =
Reports
Caterpillar Confidential: Green
There must be some reason why less than 3% of the world has moved toward
immersion silver. Why doesn't HASL or NiGold work for your application?
Mike
-----Original Message-----
From: Jack C. Olson [mailto:[log in to unmask]]
Sent: Wednesday, April 17, 2002 7:39 AM
To: [log in to unmask]
Subject: Re: [TN] Immersion Silver
The PCD magazine list went down before I could get an
answer to this question, does anyone have experience
with silver and contact switches?
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
Most sources say a silver surface will not be solderable
after a month or so unprotected. (Even in a baggie it will
be okay a year later?)
Anyway, you say it is good for switches, which would solve
some of our hard gold plating problems.
But I would think the "unsolderability" of the aged silver
surface (unprotected in the unit and tarnished?) would
affect the reliability of the switches, wouldn't it?
Jack
Rob Mongey <[log in to unmask]>@freelists.org
4Apr2002 06:08 AM
Please respond to [log in to unmask]
Sent by: [log in to unmask]
To: [log in to unmask]
cc:
Subject: [pcdlist] Re: Immersion Silver
Retain Until: 05/04/2002 Retention Category: G90 - Information and =
Reports
Caterpillar Confidential: Green
Hi all,
Good to see Immersion Silver is starting to take off. We've been =
using
it
in here for about two years, and it is now our prefered board finish (We
get silver finish unless we specify differently.) More common useage =
will
mean that maybe more Far Eastern shops will start supplying it.
We started to use Silver because it is so adaptable to what we need
our
PCB surface finish to do, namely:
1. Good solderability. (Silver excels at this, ask any vendor).
2. Flatness for fine pitch SMT. (Silver is as flat, if not flatter than
Gold)
3. Mechanical strength for carbon pill switch contacts / Elastomer
contacts. ( Flash Gold is weak, and hard Gold gives SMT solderability
problems)
4. Stability for compression power contacts. (We have power contacts on =
our
PCBs that mate to battery contacts via a spring compression. We found =
that
the nickel under gold can cause problems with electrochemical migration
toward our battery contact.)
Immersion silver is the most suitable choice that can do all four. I'd =
use
gold as an alternative, but we'd have to compromise our designs =
somewhat.
We specify our Silver finish as 0.1 Microns Min to 0.2 Microns Max, over
bare copper. Anyone else do it differently? Or do we trust our board =
shops?
:)
Regards,
Rob Mongey.
CAD Technician.
Robert Mongey <[log in to unmask]> Tel : +353 (0)91 774300
Bio Medical Research Direct : +353 (0)91 774338
BMR House, Fax : +353 (0)91 774302
Parkmore Business Park West, Mobile : +353 (0)87 2485262
Galway
Rep of Ireland.
-------------------------------------------------------------------------=
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ext.5315
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=========================================================================
Date: Wed, 17 Apr 2002 13:05:32 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Guy Ramsey <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Guy Ramsey <[log in to unmask]>
Subject: Re: Immersion Silver
X-To: "WEEKES, MICHAEL HS-SNS" <[log in to unmask]>
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit
Yes, a reason . . .
Ignorance?
Knowledge?
Marketing?
Science?
Yin
Yang
If we only understood the laws of balance.
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of WEEKES, MICHAEL
> HS-SNS
> Sent: Wednesday, April 17, 2002 10:17 AM
> To: [log in to unmask]
> Subject: Re: [TN] Immersion Silver
>
>
> There must be some reason why less than 3% of the world has moved toward
> immersion silver. Why doesn't HASL or NiGold work for your application?
>
> Mike
>
> -----Original Message-----
> From: Jack C. Olson [mailto:[log in to unmask]]
> Sent: Wednesday, April 17, 2002 7:39 AM
> To: [log in to unmask]
> Subject: Re: [TN] Immersion Silver
>
>
> The PCD magazine list went down before I could get an
> answer to this question, does anyone have experience
> with silver and contact switches?
>
> ==============================================
>
> Most sources say a silver surface will not be solderable
> after a month or so unprotected. (Even in a baggie it will
> be okay a year later?)
> Anyway, you say it is good for switches, which would solve
> some of our hard gold plating problems.
>
> But I would think the "unsolderability" of the aged silver
> surface (unprotected in the unit and tarnished?) would
> affect the reliability of the switches, wouldn't it?
>
> Jack
>
>
>
>
>
>
> Rob Mongey <[log in to unmask]>@freelists.org
> 4Apr2002 06:08 AM
>
> Please respond to [log in to unmask]
>
> Sent by: [log in to unmask]
>
>
>
> To: [log in to unmask]
> cc:
>
> Subject: [pcdlist] Re: Immersion Silver
> Retain Until: 05/04/2002 Retention Category: G90 - Information and Reports
> Caterpillar Confidential: Green
>
>
>
> Hi all,
> Good to see Immersion Silver is starting to take off. We've
> been using
> it
> in here for about two years, and it is now our prefered board finish (We
> get silver finish unless we specify differently.) More common useage will
> mean that maybe more Far Eastern shops will start supplying it.
>
> We started to use Silver because it is so adaptable to what we need
> our
> PCB surface finish to do, namely:
>
> 1. Good solderability. (Silver excels at this, ask any vendor).
> 2. Flatness for fine pitch SMT. (Silver is as flat, if not flatter than
> Gold)
> 3. Mechanical strength for carbon pill switch contacts / Elastomer
> contacts. ( Flash Gold is weak, and hard Gold gives SMT solderability
> problems)
> 4. Stability for compression power contacts. (We have power
> contacts on our
> PCBs that mate to battery contacts via a spring compression. We found that
> the nickel under gold can cause problems with electrochemical migration
> toward our battery contact.)
>
> Immersion silver is the most suitable choice that can do all four. I'd use
> gold as an alternative, but we'd have to compromise our designs somewhat.
>
> We specify our Silver finish as 0.1 Microns Min to 0.2 Microns Max, over
> bare copper. Anyone else do it differently? Or do we trust our
> board shops?
> :)
>
> Regards,
> Rob Mongey.
> CAD Technician.
>
> Robert Mongey <[log in to unmask]> Tel : +353 (0)91 774300
> Bio Medical Research Direct : +353 (0)91 774338
> BMR House, Fax : +353 (0)91 774302
> Parkmore Business Park West, Mobile : +353 (0)87 2485262
> Galway
> Rep of Ireland.
>
> ------------------------------------------------------------------
> ----------
> -----
> Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
> To unsubscribe, send a message to [log in to unmask] with following text in
> the BODY (NOT the subject field): SIGNOFF Technet
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> [log in to unmask]: SET
> Technet NOMAIL
> To receive ONE mailing per day of all the posts: send e-mail to
> [log in to unmask]: SET Technet Digest
> Search the archives of previous posts at: http://listserv.ipc.org/archives
> Please visit IPC web site http://www.ipc.org/html/forum.htm for additional
> information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700
> ext.5315
> ------------------------------------------------------------------
> ----------
> -----
>
> ------------------------------------------------------------------
> ---------------
> Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
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> Please visit IPC web site http://www.ipc.org/html/forum.htm for additional
> information, or contact Keach Sasamori at [log in to unmask] or
> 847-509-9700 ext.5315
> ------------------------------------------------------------------
> ---------------
>
---------------------------------------------------------------------------------
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=========================================================================
Date: Wed, 17 Apr 2002 13:11:43 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Stephannie Caliendo <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Stephannie Caliendo <[log in to unmask]>
Subject: IPC DESIGNERS LEARNING SYMPOSIUMS - TEXAS & CANADA
Mime-Version: 1.0
Content-Type: text/plain; charset=US-ASCII
Content-Transfer-Encoding: quoted-printable
Hello Everyone,
For the upcoming Texas Symposium - May 20-25, 2002
VISIT...
Brochure: http://dc.ipc.org/DLS/DLS.HTM=20
Tabletop Exhibit Application: http://dc.ipc.org/DLS/2002tableapp.pdf
Registration Form: http://dc.ipc.org/DLS/2002DLSreg.pdf
DC Membership: http://dc.ipc.org/DCmembership/DC%20Application.pdf
(Canada's Symposium information will be posted soon.)
This year's symposiums will maintain the high level of educational quality =
while lowering cost, both in the price of attendance and reducing travel =
by making the conference available in two locations.
For 2002, the IPC Designers Council is bringing together first-class =
technical events that include full-day workshops on the hottest topics in =
design, hands-on training courses, panel discussions, facility tours, a =
self-development forum, tabletop exhibits, highly informative technical =
papers, that are designed specifically to prepare the designer survive as =
the economy strengthens.
We are finding many of our colleagues facing company cutbacks and =
unemployment. As we are here to serve you and the industry, we realize the =
increasing need to alleviate the costs of networking and professional =
development.
Both of the IPC Designers Learning Symposiums, May 20-25, Dallas, Texas, =
and Sept. 30-Oct. 5, Toronto, Canada, will offer technical workshops, an =
unparallel technical conference and both PCB Designer Certification =
Programs: the Designer Certification Preparation Workshop & Exam and the =
new PCB Advanced Designer Certification Preparation Workshop & Exam . The =
shows will be similar in layout with differences in the content.
If you have any questions please feel free to call or email me one on one. =
Please do not respond to all.=20
Kindest regards,
Stephannie Caliendo
IPC Designers Council
Program Manager
[log in to unmask]
847-790-5302
---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
=========================================================================
Date: Wed, 17 Apr 2002 14:54:50 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Rob Legg <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Rob Legg <[log in to unmask]>
Subject: Re: Immersion Silver
X-To: "Jack C. Olson" <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit
Silver finds it's way into high energy switchgear contacts (not solder
terminations) due to it's ability to maintain a functional contact surface
in the presence of arcing. Normal contamination of surfaces is defeated
through the wiping action forced on these contacts, when in transition.
Arcing and static surfaces of the contact are partitioned, where possible.
High rel components (mtbf still sucks) are hermetically sealed.
The mfring process is generally hostile to all switchgear; uncovered or
unsealed parts require special handling to reduce fallout.
Silver has no greater suitability for forming reliable solder joints, on or
in switchgear, than it has anywhere else.
A month is a very short time to guarantee solderability. Have you looked at
the date-codes on some of your electromechanical parts?
RL
[log in to unmask]
----- Original Message -----
From: "Jack C. Olson" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Wednesday, April 17, 2002 8:38 AM
Subject: Re: [TN] Immersion Silver
> The PCD magazine list went down before I could get an
> answer to this question, does anyone have experience
> with silver and contact switches?
>
> ==============================================
>
> Most sources say a silver surface will not be solderable
> after a month or so unprotected. (Even in a baggie it will
> be okay a year later?)
> Anyway, you say it is good for switches, which would solve
> some of our hard gold plating problems.
>
> But I would think the "unsolderability" of the aged silver
> surface (unprotected in the unit and tarnished?) would
> affect the reliability of the switches, wouldn't it?
>
> Jack
>
>
>
>
>
>
> Rob Mongey <[log in to unmask]>@freelists.org
> 4Apr2002 06:08 AM
>
> Please respond to [log in to unmask]
>
> Sent by: [log in to unmask]
>
>
>
> To: [log in to unmask]
> cc:
>
> Subject: [pcdlist] Re: Immersion Silver
> Retain Until: 05/04/2002 Retention Category: G90 - Information and Reports
> Caterpillar Confidential: Green
>
>
>
> Hi all,
> Good to see Immersion Silver is starting to take off. We've been
using
> it
> in here for about two years, and it is now our prefered board finish (We
> get silver finish unless we specify differently.) More common useage will
> mean that maybe more Far Eastern shops will start supplying it.
>
> We started to use Silver because it is so adaptable to what we need
> our
> PCB surface finish to do, namely:
>
> 1. Good solderability. (Silver excels at this, ask any vendor).
> 2. Flatness for fine pitch SMT. (Silver is as flat, if not flatter than
> Gold)
> 3. Mechanical strength for carbon pill switch contacts / Elastomer
> contacts. ( Flash Gold is weak, and hard Gold gives SMT solderability
> problems)
> 4. Stability for compression power contacts. (We have power contacts on
our
> PCBs that mate to battery contacts via a spring compression. We found that
> the nickel under gold can cause problems with electrochemical migration
> toward our battery contact.)
>
> Immersion silver is the most suitable choice that can do all four. I'd use
> gold as an alternative, but we'd have to compromise our designs somewhat.
>
> We specify our Silver finish as 0.1 Microns Min to 0.2 Microns Max, over
> bare copper. Anyone else do it differently? Or do we trust our board
shops?
> :)
>
> Regards,
> Rob Mongey.
> CAD Technician.
>
> Robert Mongey <[log in to unmask]> Tel : +353 (0)91 774300
> Bio Medical Research Direct : +353 (0)91 774338
> BMR House, Fax : +353 (0)91 774302
> Parkmore Business Park West, Mobile : +353 (0)87 2485262
> Galway
> Rep of Ireland.
>
> --------------------------------------------------------------------------
-------
> Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
> To unsubscribe, send a message to [log in to unmask] with following text in
> the BODY (NOT the subject field): SIGNOFF Technet
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SET Technet NOMAIL
> To receive ONE mailing per day of all the posts: send e-mail to
[log in to unmask]: SET Technet Digest
> Search the archives of previous posts at: http://listserv.ipc.org/archives
> Please visit IPC web site http://www.ipc.org/html/forum.htm for additional
> information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700
ext.5315
> --------------------------------------------------------------------------
-------
>
---------------------------------------------------------------------------------
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---------------------------------------------------------------------------------
=========================================================================
Date: Wed, 17 Apr 2002 14:08:55 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
[log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Immersion Silver
MIME-Version: 1.0
Content-type: text/plain; charset="us-ascii"
I think that you will find that many are put off from immersion silver
because:
1) they don't have the background to differentiate between the modern
immersion silver and the old electroplated silver that electromigrated at
the drop of a hat.
2) both Underwriter Labs and Bellcore had long time positions of "thou
shalt not silver". Most are not willing to spend the money to pursuade
Bellcore and UL that their position is antiquated.
Doug Pauls
Rockwell Collins
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Date: Wed, 17 Apr 2002 15:23:18 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Bev Christian <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Bev Christian <[log in to unmask]>
Subject: Re: Immersion Silver
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Ditto to what George said. And outside of suppliers with vested interests,
you aren't going to find anyone with more knowledge on this than George.
regards,
Bev Christian
Research in Motion
-----Original Message-----
From: Wenger, George M. [mailto:[log in to unmask]]
Sent: April 17, 2002 1:01 PM
To: [log in to unmask]
Subject: Re: [TN] Immersion Silver
I think the obvious answer is that the other 97% of the rest of the world
are waiting for someone to sign on the dotted line that there is nothing
wrong with immersion silver, its reliable and and we'll never have trouble
with it. The 3% who are using it have done their homework and aren't
relying on someone else telling them it is okay. They have found out that
immersion silver works at lest as well as other surface finished, is much
flatter than HASL, isn't susceptable to "Black Pad", is as reliable as
solder joints made to HASL or OSP boards, and the problems one can have with
imemrsion silver can be handled.
Regards,
George
George M. Wenger (908)-546-4531 [log in to unmask]
Distinguished Member Technical Staff
Celiant Corporation, FMA Lab, 40 Technology Drive, NJ 07059
-----Original Message-----
From: Jack C. Olson [mailto:[log in to unmask]]
Sent: Wednesday, April 17, 2002 11:22 AM
To: [log in to unmask]
Subject: Re: [TN] Immersion Silver
Hmmm,
Well, at some point in EVERY new technology it was used by less
than 3% of the world, eh? Guess I'm just a trailblazer....
naw, just kiddin ya.
I subscribed to a magazine called Circuitree, and the last issue
came bundled with another publication called "The Board Authority"
which has some very well written (and well researched!) articles
on alternate finishes. I can't see any downside to using silver
in our applications, and I've looked all through the archives for
Technet, DesignerCouncil and PCDlist forums, still no show-stoppers,
so we tried it for the first time on our last design. Yes, HASL and
NiGold do work fine, but maybe we can get the same functionality
for cheaper, and do our fab vendor a favor in the process, since
they seem to prefer it (less steps? more reliable? not sure) maybe
the fab guys can answer that one....
Jack
"WEEKES, MICHAEL HS-SNS" <[log in to unmask]>
17Apr2002 09:16 AM
To: "'TechNet E-Mail Forum.'" <[log in to unmask]>
"'Jack C. Olson'" <[log in to unmask]>
cc:
Subject: RE: [TN] Immersion Silver
Retain Until: 05/17/2002 Retention Category: G90 - Information and Reports
Caterpillar Confidential: Green
There must be some reason why less than 3% of the world has moved toward
immersion silver. Why doesn't HASL or NiGold work for your application?
Mike
-----Original Message-----
From: Jack C. Olson [mailto:[log in to unmask]]
Sent: Wednesday, April 17, 2002 7:39 AM
To: [log in to unmask]
Subject: Re: [TN] Immersion Silver
The PCD magazine list went down before I could get an
answer to this question, does anyone have experience
with silver and contact switches?
==============================================
Most sources say a silver surface will not be solderable
after a month or so unprotected. (Even in a baggie it will
be okay a year later?)
Anyway, you say it is good for switches, which would solve
some of our hard gold plating problems.
But I would think the "unsolderability" of the aged silver
surface (unprotected in the unit and tarnished?) would
affect the reliability of the switches, wouldn't it?
Jack
Rob Mongey <[log in to unmask]>@freelists.org
4Apr2002 06:08 AM
Please respond to [log in to unmask]
Sent by: [log in to unmask]
To: [log in to unmask]
cc:
Subject: [pcdlist] Re: Immersion Silver
Retain Until: 05/04/2002 Retention Category: G90 - Information and Reports
Caterpillar Confidential: Green
Hi all,
Good to see Immersion Silver is starting to take off. We've been using
it
in here for about two years, and it is now our prefered board finish (We
get silver finish unless we specify differently.) More common useage will
mean that maybe more Far Eastern shops will start supplying it.
We started to use Silver because it is so adaptable to what we need
our
PCB surface finish to do, namely:
1. Good solderability. (Silver excels at this, ask any vendor).
2. Flatness for fine pitch SMT. (Silver is as flat, if not flatter than
Gold)
3. Mechanical strength for carbon pill switch contacts / Elastomer
contacts. ( Flash Gold is weak, and hard Gold gives SMT solderability
problems)
4. Stability for compression power contacts. (We have power contacts on our
PCBs that mate to battery contacts via a spring compression. We found that
the nickel under gold can cause problems with electrochemical migration
toward our battery contact.)
Immersion silver is the most suitable choice that can do all four. I'd use
gold as an alternative, but we'd have to compromise our designs somewhat.
We specify our Silver finish as 0.1 Microns Min to 0.2 Microns Max, over
bare copper. Anyone else do it differently? Or do we trust our board shops?
:)
Regards,
Rob Mongey.
CAD Technician.
Robert Mongey <[log in to unmask]> Tel : +353 (0)91 774300
Bio Medical Research Direct : +353 (0)91 774338
BMR House, Fax : +353 (0)91 774302
Parkmore Business Park West, Mobile : +353 (0)87 2485262
Galway
Rep of Ireland.
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Date: Wed, 17 Apr 2002 12:27:44 -0700
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: David Ricketts <[log in to unmask]>
Subject: Re: IPC SMT FOOTPRINT DESIGN GUIDLINES VS SUPPLIERS
In-Reply-To: <[log in to unmask]>
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Or as I heard it:
Teacher, to her class: "Can someone use the word "horticulture" in a
sentence?"
Little Johnny: "You can lead a horticulture, but you can't make her think."
David
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Werner Engelmaier
Ahh Earl,
You can lead the horse [or is it ass] to the water, but you cannot make it
drink.
Werner
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Date: Wed, 17 Apr 2002 16:27:07 -0400
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Gerard O'Brien <[log in to unmask]>
Subject: Re: Immersion Silver
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Doug - to your second point, there is currently an industry committee
attempting to persuade UL to change their antiquated views on immersion
silver.
Regards
Gerard O'Brien
Photocircuits Corporation
-----Original Message-----
From: [log in to unmask] [mailto:[log in to unmask]]
Sent: Wednesday, April 17, 2002 3:09 PM
To: [log in to unmask]
Subject: Re: [TN] Immersion Silver
I think that you will find that many are put off from immersion silver
because:
1) they don't have the background to differentiate between the modern
immersion silver and the old electroplated silver that electromigrated at
the drop of a hat.
2) both Underwriter Labs and Bellcore had long time positions of "thou
shalt not silver". Most are not willing to spend the money to pursuade
Bellcore and UL that their position is antiquated.
Doug Pauls
Rockwell Collins
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Date: Wed, 17 Apr 2002 13:24:15 -0700
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: David Ricketts <[log in to unmask]>
Subject: Re: Cracking Chip Resistors
X-To: Earl Moon <[log in to unmask]>
In-Reply-To: <[log in to unmask]>
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Earl,
I hope you find it reassuring the today's Corvette still uses the push rod
V8, and the LS6 engine develops 405 HP @ 6000 RPM and 400 lbs-ft of torque
at 4800 RPM. That's 0-60 in 4.0 seconds and 1/4 mile in 12.85 at 118 mph on
the Z06 model. Who needs nitrous :-)
David
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Earl Moon
Sent: Tuesday, April 16, 2002 11:13 PM
To: [log in to unmask]
Subject: Re: [TN] Cracking Chip Resistors
Actually, as told me by a very serious and dedicated mechanical enginnering
type, like me, it changed in 1972, or thereabouts. Academia started the
"new" stuff to reflect what you say. I agree with it but it's just real hard
for old hard heads to make the change. 1972, are you joshing me?
Another thing I have difficulty with is pounds/foot instead of foot/pounds.
I came from the 409 Chevy and 429 Boss and super Cobra Jet era. Anyone else
that old having bought, built, or otherwise used "real" muscle in their cars
or boats. ft./lbs. of torque got you off the line as acceleration is a
function of torque unlike all these little high revin' torqueless high horse
power motors of today claiming high speed is a function of RPM without
benefit of fast acceleration.
I do love the smell of burned nitro in the morning,
MoonMan
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Date: Wed, 17 Apr 2002 15:42:42 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Immersion Silver
X-To: [log in to unmask]
Right on and count me as an additional 1% and more if more customers asked
more suppliers to use silver.
Earl
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Date: Wed, 17 Apr 2002 15:46:20 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: IPC SMT FOOTPRINT DESIGN GUIDLINES VS SUPPLIERS
X-To: [log in to unmask]
Another Johnnie joke is unsuitable for this forum but we all remember it, eh?
MoonMan
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Date: Wed, 17 Apr 2002 15:54:20 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Cracking Chip Resistors
X-To: [log in to unmask]
David,
Truly, I am reassured. Ain't it great and I even go along with the lbs/ft
thing. Pushrods forever maybe with a little help from four valve head
designs just to give a little more RPM at top end and higher speeds with the
faster elapsed times. Still love my Boss 429, no matter how crude, in my
"love boat."
Hell, I only use nitrous to outdo the Dew. He's always said I was on
something. Now you all know. EEEEEha and whoopeeeeee!
MoonMan
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Date: Wed, 17 Apr 2002 22:53:44 +0100
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Alan Groves <[log in to unmask]>
Subject: Spell checks
In-Reply-To: <[log in to unmask]>
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Hi technetters,
I am much more of a 'reader' than contributor to the forum, and am often
amazed at, or embarrassed by, the knowledge that is transferred to or shared
within the forum. I could quite possibly be within Moonman's description of
young designer/artist;- but I am confident!
It is only during my 'free' time that I allow myself the luxury of fully
reading the postings, much of which remind me of why I hated chemistry in
school, but many more, especially Sir Moon's, remind me of how I
(unfortunately) fell in to the PCB/PWB business.
However, although I would wish to ask many questions (and I have fantasised
about real show stoppers) :
Why don't Y'all use spell checkers?
Alan Groves,
Senior PCB Designer CID
Spectel Head Office, 21 Stillorgan Ind. Park, Stillorgan,
Co. Dublin. Ireland.
Phone: 353 907 62803
Fax: 353 1 2953740
Email: [log in to unmask]
Internet: www.spectel.com
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Date: Wed, 17 Apr 2002 22:55:47 +0100
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Alan Groves <[log in to unmask]>
Subject: Re: Cracking Chip Resistors
X-To: Earl Moon <[log in to unmask]>
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
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You ever been on >750cc think tank?
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Earl Moon
Sent: Wednesday, April 17, 2002 9:54 PM
To: [log in to unmask]
Subject: Re: [TN] Cracking Chip Resistors
David,
Truly, I am reassured. Ain't it great and I even go along with the lbs/ft
thing. Pushrods forever maybe with a little help from four valve head
designs just to give a little more RPM at top end and higher speeds with the
faster elapsed times. Still love my Boss 429, no matter how crude, in my
"love boat."
Hell, I only use nitrous to outdo the Dew. He's always said I was on
something. Now you all know. EEEEEha and whoopeeeeee!
MoonMan
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Date: Wed, 17 Apr 2002 18:31:22 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Ken Carlile <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Ken Carlile <[log in to unmask]>
Subject: Re: Spell checks
X-To: [log in to unmask]
In-Reply-To: <[log in to unmask]>
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fantasised?????
Try fantasized.
Why don't you all use spell checkers and proper grammar?
Don't pick on Moonman! He is definitely not part of this world!
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Alan Groves
Sent: Wednesday, April 17, 2002 5:54 PM
To: [log in to unmask]
Subject: [TN] Spell checks
Hi technetters,
I am much more of a 'reader' than contributor to the forum, and am often
amazed at, or embarrassed by, the knowledge that is transferred to or shared
within the forum. I could quite possibly be within Moonman's description of
young designer/artist;- but I am confident!
It is only during my 'free' time that I allow myself the luxury of fully
reading the postings, much of which remind me of why I hated chemistry in
school, but many more, especially Sir Moon's, remind me of how I
(unfortunately) fell in to the PCB/PWB business.
However, although I would wish to ask many questions (and I have fantasised
about real show stoppers) :
Why don't Y'all use spell checkers?
Alan Groves,
Senior PCB Designer CID
Spectel Head Office, 21 Stillorgan Ind. Park, Stillorgan,
Co. Dublin. Ireland.
Phone: 353 907 62803
Fax: 353 1 2953740
Email: [log in to unmask]
Internet: www.spectel.com
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Date: Wed, 17 Apr 2002 17:27:59 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Spell checks
X-To: Alan Groves <[log in to unmask]>
You are absolutttteeeeoly right Alan. We shoullld assllll do that. It the
most important part of the forum. Hell, how else could we comminiucate better?
MoonMan
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Date: Wed, 17 Apr 2002 17:30:39 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Cracking Chip Resistors
X-To: Alan Groves <[log in to unmask]>
Alan,
Is that like a pocket rocket Steve Z rides? If not, I need more than
spelling checkers. I need P----r checkrs. Oooops!
Enjoy,
MoonMan or?
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Date: Wed, 17 Apr 2002 17:33:11 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Spell checks
X-To: Ken Carlile <[log in to unmask]>
You're right Carlile and you are?
MoonMan where the language is right on but hard to translate into SIMPLE
english.
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=========================================================================
Date: Wed, 17 Apr 2002 17:14:52 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Vanderhoof, Brad" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Vanderhoof, Brad" <[log in to unmask]>
Subject: Re: Off Topic - The Married Spud & other burning questions
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
A quick question.
Different trace widths to the pads of small passives are a root cause of
tombstoning.
Any opinions about the same situation under a bga?
Thanks,
Brad Vanderhoof
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Date: Thu, 18 Apr 2002 09:52:31 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Spell checks
X-To: Ken Carlile <[log in to unmask]>
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
Ken,
You try 'fantasised'. That's the English way of spelling. 'Fantasized' is
American (or the volume of a fizzy orange drink). Ah, me! I'm about to
start a war between "the-two-countries-separated-by-a-common-language" over
whose spelling is right.
Peter
Ken Carlile
<kcarlile@ECCI To: [log in to unmask]
NCORP.COM> cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
Sent by: Aero/ST Group)
TechNet Subject: Re: [TN] Spell checks
<[log in to unmask]
RG>
04/18/02 06:31
AM
Please respond
to "TechNet
E-Mail
Forum.";
Please respond
to Ken Carlile
fantasised?????
Try fantasized.
Why don't you all use spell checkers and proper grammar?
Don't pick on Moonman! He is definitely not part of this world!
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Alan Groves
Sent: Wednesday, April 17, 2002 5:54 PM
To: [log in to unmask]
Subject: [TN] Spell checks
Hi technetters,
I am much more of a 'reader' than contributor to the forum, and am often
amazed at, or embarrassed by, the knowledge that is transferred to or
shared
within the forum. I could quite possibly be within Moonman's description of
young designer/artist;- but I am confident!
It is only during my 'free' time that I allow myself the luxury of fully
reading the postings, much of which remind me of why I hated chemistry in
school, but many more, especially Sir Moon's, remind me of how I
(unfortunately) fell in to the PCB/PWB business.
However, although I would wish to ask many questions (and I have fantasised
about real show stoppers) :
Why don't Y'all use spell checkers?
Alan Groves,
Senior PCB Designer CID
Spectel Head Office, 21 Stillorgan Ind. Park, Stillorgan,
Co. Dublin. Ireland.
Phone: 353 907 62803
Fax: 353 1 2953740
Email: [log in to unmask]
Internet: www.spectel.com
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Date: Thu, 18 Apr 2002 02:02:51 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Mickey Weiner <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Mickey Weiner <[log in to unmask]>
Subject: Re: Redesign Via in Pad
X-To: [log in to unmask]
Mime-Version: 1.0
Content-Type: text/plain; charset=US-ASCII
Content-Transfer-Encoding: 7bit
Sigi,
Before redesigning the whole board, which is really the proper cure to
this problem
you can try the following.
Vias on the bottom( opposite) side should have the solder mask almost
closing the hole:
: Drill + 4 mils - provided they are not used for Ict. This will
eliminate some of the paste loss.
Then add extra solder past to the troublesome locations either by
enlarging the
stencil opening (opening may be larger then the pad size) or by
injecting paste in rework
station or even in line if your line is so configured.
Mickey
>>> [log in to unmask] 15-Apr-02 6:08:35 PM >>>
Hello to all
We have to redesign different board's because of Via in Pad:
Situation now:
FR4, thickness 1,5 mm, OCC finish
Through Hole Vias in Pads (middle, diameter 0,15..0,3 mm)
The problem is the sucking of solder form to the top to the bottom
side
(causing low solder on top and bumps on test points on the bottom
side)
Because of place limitations dog bones can't probably not be used.
What is your recommendation?
Using Blind Vias (problem of Voids in the solder joint?) ?
Epoxy (with Ag or what else) filled Vias?
Vias on the edge of the pad?
More ideas?
All input is welcome
Best regards
Siggi
----------------------------------------------------------------------------
-
Kind regards / Mit freundlichen Gr??en
Dr. Siegmund Zweigart
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Date: Thu, 18 Apr 2002 11:53:17 +0300
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Brian Ellis <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Brian Ellis <[log in to unmask]>
Subject: Re: Spell checks
X-To: [log in to unmask]
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit
Well, if we are going to have an Atlantic war, I received just today a
doc called "If you are a Brit in the USA, you might be going native if
...." This is 11 pages long, so I won't post it here, but I'll e-mail it
off list to anyone who requests it. The headings are Language; Politics;
Media; Going Home; Assimilating the Culture and Customs; Work and
Shopping and Eating Out. A few samples:
...You call shops "stores"
...You stop asking for rubbers when you want an eraser
...Trunk and hood come to mind rather than boot and bonnet
...You embrace racial politics as the national pastime
...The first section in the Sunday newspapers is the funnies
...You order a Martini in the UK and then have to ask them to add gin
...You flinch when you hear American buzzwords mispronounced on British
radio shows
...You buy a handgun
...You have bought a Websters Dictionary and the OED is gathering dust
...You have given up using irony on anyone without a college education
...You actually try and sing the Star Spangled Banner
...You now regard the UK as being part of Europe
...You get annoyed when a store closes before 9 pm
...You ask for Diet 7UP
...You don't wait for the sun to shine to eat ice cream
...You buy HUGE bottles of gin
Brian
Alan Groves wrote:
>
> Hi technetters,
> I am much more of a 'reader' than contributor to the forum, and am often
> amazed at, or embarrassed by, the knowledge that is transferred to or shared
> within the forum. I could quite possibly be within Moonman's description of
> young designer/artist;- but I am confident!
> It is only during my 'free' time that I allow myself the luxury of fully
> reading the postings, much of which remind me of why I hated chemistry in
> school, but many more, especially Sir Moon's, remind me of how I
> (unfortunately) fell in to the PCB/PWB business.
> However, although I would wish to ask many questions (and I have fantasised
> about real show stoppers) :
>
> Why don't Y'all use spell checkers?
>
> Alan Groves,
> Senior PCB Designer CID
> Spectel Head Office, 21 Stillorgan Ind. Park, Stillorgan,
> Co. Dublin. Ireland.
> Phone: 353 907 62803
> Fax: 353 1 2953740
> Email: [log in to unmask]
> Internet: www.spectel.com
>
> ---------------------------------------------------------------------------------
> Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
> To unsubscribe, send a message to [log in to unmask] with following text in
> the BODY (NOT the subject field): SIGNOFF Technet
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> Please visit IPC web site http://www.ipc.org/html/forum.htm for additional
> information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700 ext.5315
> ---------------------------------------------------------------------------------
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Date: Thu, 18 Apr 2002 14:09:18 +0530
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
MA Ranganath/SMPLB/SEC/SANMAR <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: MA Ranganath/SMPLB/SEC/SANMAR <[log in to unmask]>
Subject: Re: core fill
X-To: [log in to unmask]
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
Dear Sir,
We would like to know some details (technical and commercial) including
Source with contact persons' email,
phone fax etc., for our further action. Expecting your favourable
response. We are one of the Bare PCB mfrs
in India making special products of small volumes of various types.
Regards,
M A Ranganath
GM - Technical & Quality
Sanmar Micropack Limited
Plot No.16, Jigani Industrial Area,
Bangalore - 562 106. INDIA
Phone: 91 - 80 - 7825223/224/226/389
Fax : 91 - 80 - 7825225
Email : [log in to unmask]
[log in to unmask]
OM< > To: [log in to unmask]
Sent by: cc:
TechNet Subject: Re: [TN] core fill
<[log in to unmask]
ORG>
04/11/02
12:41 AM
Please
respond to
"TechNet
E-Mail
Forum.";
Please
respond to
ACCUENG
Tony,
I don't know if Howfill is even available any more. WE have used Fiberite
to fill 0.060 thick copper core w/o any problems. 0.040 thick copper core
regularly.
Arlon has a prepreg that replaces Howfill, but I am not sure it will work
for 0.060 thick core.
Rush
Accurate Engg Inc
www.accueng.com
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* * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
The information contained in this message is legally privileged and
confidential information intended only for the use of the addressed
individual or entity indicated in this message (or responsible for
delivery of the message to such person). It must not be read, copied,
disclosed, distributed or used by any person other than the addressee.
Unauthorised use, disclosure or copying is strictly prohibited and may be
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Opinions, conclusions and other information on this message that do not
relate to the official business of any of the constituent companies of
the SANMAR GROUP shall be understood as neither given nor endorsed by
the Group.
If you have received this message in error, you should destroy this
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Date: Thu, 18 Apr 2002 10:56:52 +0100
Reply-To: Dougal Stewart <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Dougal Stewart <[log in to unmask]>
Subject: Re: Immersion Silver
X-To: "Jack C. Olson" <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit
I would like to know why people don't use OSP - from a board shop's
viewpoint, it is the best finish to put on a board - why ? because it is
very simple chemistry, puts no thermal shock on the product, is applied on a
SHORT conveyor line, and can be easily reworked unlike ANY of the other
finishes. The assembly guys don't like it if they start assembling a product
and then stop because they don't have the parts to finish the job, but
anyone that puts a board into assembly without the ability to finish it
within 6 hours obviously knows nothing about world class manufacturing
practise. As for shelf life, if your stock is even 2 years old, send the
boards back to the board shop and for a small fee they just put them back
down the line again and you have a finish that is good as new, without
having undergone a vicious chemical attack to remove the finish.
Just my thoughts !
Dougal Stewart
email: [log in to unmask]
phone: +44 1896 822204
mob: +44 7984 629667
----- Original Message -----
From: "Jack C. Olson" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Wednesday, April 17, 2002 4:22 PM
Subject: Re: [TN] Immersion Silver
> Hmmm,
>
> Well, at some point in EVERY new technology it was used by less
> than 3% of the world, eh? Guess I'm just a trailblazer....
>
> naw, just kiddin ya.
> I subscribed to a magazine called Circuitree, and the last issue
> came bundled with another publication called "The Board Authority"
> which has some very well written (and well researched!) articles
> on alternate finishes. I can't see any downside to using silver
> in our applications, and I've looked all through the archives for
> Technet, DesignerCouncil and PCDlist forums, still no show-stoppers,
> so we tried it for the first time on our last design. Yes, HASL and
> NiGold do work fine, but maybe we can get the same functionality
> for cheaper, and do our fab vendor a favor in the process, since
> they seem to prefer it (less steps? more reliable? not sure) maybe
> the fab guys can answer that one....
>
> Jack
>
>
>
>
>
> "WEEKES, MICHAEL HS-SNS" <[log in to unmask]>
> 17Apr2002 09:16 AM
>
>
> To: "'TechNet E-Mail Forum.'" <[log in to unmask]>
> "'Jack C. Olson'" <[log in to unmask]>
> cc:
>
> Subject: RE: [TN] Immersion Silver
> Retain Until: 05/17/2002 Retention Category: G90 - Information and Reports
> Caterpillar Confidential: Green
>
>
> There must be some reason why less than 3% of the world has moved toward
> immersion silver. Why doesn't HASL or NiGold work for your application?
>
> Mike
>
> -----Original Message-----
> From: Jack C. Olson [mailto:[log in to unmask]]
> Sent: Wednesday, April 17, 2002 7:39 AM
> To: [log in to unmask]
> Subject: Re: [TN] Immersion Silver
>
>
> The PCD magazine list went down before I could get an
> answer to this question, does anyone have experience
> with silver and contact switches?
>
> ==============================================
>
> Most sources say a silver surface will not be solderable
> after a month or so unprotected. (Even in a baggie it will
> be okay a year later?)
> Anyway, you say it is good for switches, which would solve
> some of our hard gold plating problems.
>
> But I would think the "unsolderability" of the aged silver
> surface (unprotected in the unit and tarnished?) would
> affect the reliability of the switches, wouldn't it?
>
> Jack
>
>
>
>
>
>
> Rob Mongey <[log in to unmask]>@freelists.org
> 4Apr2002 06:08 AM
>
> Please respond to [log in to unmask]
>
> Sent by: [log in to unmask]
>
>
>
> To: [log in to unmask]
> cc:
>
> Subject: [pcdlist] Re: Immersion Silver
> Retain Until: 05/04/2002 Retention Category: G90 - Information and Reports
> Caterpillar Confidential: Green
>
>
>
> Hi all,
> Good to see Immersion Silver is starting to take off. We've been
using
> it
> in here for about two years, and it is now our prefered board finish (We
> get silver finish unless we specify differently.) More common useage will
> mean that maybe more Far Eastern shops will start supplying it.
>
> We started to use Silver because it is so adaptable to what we need
> our
> PCB surface finish to do, namely:
>
> 1. Good solderability. (Silver excels at this, ask any vendor).
> 2. Flatness for fine pitch SMT. (Silver is as flat, if not flatter than
> Gold)
> 3. Mechanical strength for carbon pill switch contacts / Elastomer
> contacts. ( Flash Gold is weak, and hard Gold gives SMT solderability
> problems)
> 4. Stability for compression power contacts. (We have power contacts on
our
> PCBs that mate to battery contacts via a spring compression. We found that
> the nickel under gold can cause problems with electrochemical migration
> toward our battery contact.)
>
> Immersion silver is the most suitable choice that can do all four. I'd use
> gold as an alternative, but we'd have to compromise our designs somewhat.
>
> We specify our Silver finish as 0.1 Microns Min to 0.2 Microns Max, over
> bare copper. Anyone else do it differently? Or do we trust our board
shops?
> :)
>
> Regards,
> Rob Mongey.
> CAD Technician.
>
> Robert Mongey <[log in to unmask]> Tel : +353 (0)91 774300
> Bio Medical Research Direct : +353 (0)91 774338
> BMR House, Fax : +353 (0)91 774302
> Parkmore Business Park West, Mobile : +353 (0)87 2485262
> Galway
> Rep of Ireland.
>
> --------------------------------------------------------------------------
--
>
> -----
> Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
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> --------------------------------------------------------------------------
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>
> -----
>
> --------------------------------------------------------------------------
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> --------------------------------------------------------------------------
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Date: Thu, 18 Apr 2002 03:00:47 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Shirley Xiao <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Shirley Xiao <[log in to unmask]>
Subject: Hole cracking of Teflon PCB after screwing
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
One batch of double sided PCB using teflon materials
have hole cracking problems after screwing by electric
driver.The borad is easy to break if I bent it. Is it
do to laminate quality problem?
What kind of test shall I have?
Thanks in advance!
__________________________________________________
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Yahoo! Tax Center - online filing with TurboTax
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Date: Thu, 18 Apr 2002 07:00:48 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Immersion Silver
X-To: [log in to unmask]
Doug,
Though have answered your question, it is a good one. I like the finish and
find it as easy to work with as you say.
Way back when, we used similar finishes as "Sealbrite" and it served some
well but did not find wide use either. IBM really used a lot of OSP starting
in the mid 80's.
Like all finishes, it's difficult to sell one over another. In recent times,
trends tend to metal coatings instead of organic but the silvers and tins
are a combination.
Give me OPP/OCC's any time. I just can't sell it to clients and few board
shops deal with it much because so few use it.
Earl
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Date: Thu, 18 Apr 2002 08:29:08 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Furrow, Robert Gordon (Bob)" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Furrow, Robert Gordon (Bob)" <[log in to unmask]>
Subject: Re: Immersion Silver
X-To: Dougal Stewart <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Doug,
There are a couple of drawbacks to OSP from an assembly standpoint. One is
that we would get occasional "busts" where the solderability of the pads was
poor on a few pads on the board. You can not determine this prior to
assembly and since it is a low level occurrence, when it did occur, you
could have a lot of money worth of components on the board prior to catching
the problem. You can repair the defects that are obvious by scraping the pad
, but because you could not be sure of the integrity of the rest of the
solder joints, we chose to scrap the boards rather than assume the
reliability risk. This gets expensive very quickly. On most occasions it was
determine to not be the OSP process at fault, but rather things like unseen
soldermask residues or incomplete removal of the tin etch resist. However,
on at least one occasion boards were shipped without the OSP coating
applied.
The other area where OSP can fail is with via in pad (VIP) product. If there
is any residue remaining in the holes it will cause a degradation of the OSP
coating. Again, it results in scrapping expensive product.
OSP in general worked very well for us for over a decade, but the problems,
although infrequent, were costly and hence we have shied away from OSP in
recent years. It is still considered an acceptable finish, but it is not
preferred.
Thanks,
Robert Furrow
Printed Wiring Board Engineer
Supply Chain Networks
Lucent Technologies
978-960-3224 [log in to unmask]
-----Original Message-----
From: Dougal Stewart [mailto:[log in to unmask]]
Sent: Thursday, April 18, 2002 5:57 AM
To: [log in to unmask]
Subject: Re: [TN] Immersion Silver
I would like to know why people don't use OSP - from a board shop's
viewpoint, it is the best finish to put on a board - why ? because it is
very simple chemistry, puts no thermal shock on the product, is applied on a
SHORT conveyor line, and can be easily reworked unlike ANY of the other
finishes. The assembly guys don't like it if they start assembling a product
and then stop because they don't have the parts to finish the job, but
anyone that puts a board into assembly without the ability to finish it
within 6 hours obviously knows nothing about world class manufacturing
practise. As for shelf life, if your stock is even 2 years old, send the
boards back to the board shop and for a small fee they just put them back
down the line again and you have a finish that is good as new, without
having undergone a vicious chemical attack to remove the finish.
Just my thoughts !
Dougal Stewart
email: [log in to unmask]
phone: +44 1896 822204
mob: +44 7984 629667
----- Original Message -----
From: "Jack C. Olson" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Wednesday, April 17, 2002 4:22 PM
Subject: Re: [TN] Immersion Silver
> Hmmm,
>
> Well, at some point in EVERY new technology it was used by less
> than 3% of the world, eh? Guess I'm just a trailblazer....
>
> naw, just kiddin ya.
> I subscribed to a magazine called Circuitree, and the last issue
> came bundled with another publication called "The Board Authority"
> which has some very well written (and well researched!) articles
> on alternate finishes. I can't see any downside to using silver
> in our applications, and I've looked all through the archives for
> Technet, DesignerCouncil and PCDlist forums, still no show-stoppers,
> so we tried it for the first time on our last design. Yes, HASL and
> NiGold do work fine, but maybe we can get the same functionality
> for cheaper, and do our fab vendor a favor in the process, since
> they seem to prefer it (less steps? more reliable? not sure) maybe
> the fab guys can answer that one....
>
> Jack
>
>
>
>
>
> "WEEKES, MICHAEL HS-SNS" <[log in to unmask]>
> 17Apr2002 09:16 AM
>
>
> To: "'TechNet E-Mail Forum.'" <[log in to unmask]>
> "'Jack C. Olson'" <[log in to unmask]>
> cc:
>
> Subject: RE: [TN] Immersion Silver
> Retain Until: 05/17/2002 Retention Category: G90 - Information and Reports
> Caterpillar Confidential: Green
>
>
> There must be some reason why less than 3% of the world has moved toward
> immersion silver. Why doesn't HASL or NiGold work for your application?
>
> Mike
>
> -----Original Message-----
> From: Jack C. Olson [mailto:[log in to unmask]]
> Sent: Wednesday, April 17, 2002 7:39 AM
> To: [log in to unmask]
> Subject: Re: [TN] Immersion Silver
>
>
> The PCD magazine list went down before I could get an
> answer to this question, does anyone have experience
> with silver and contact switches?
>
> ==============================================
>
> Most sources say a silver surface will not be solderable
> after a month or so unprotected. (Even in a baggie it will
> be okay a year later?)
> Anyway, you say it is good for switches, which would solve
> some of our hard gold plating problems.
>
> But I would think the "unsolderability" of the aged silver
> surface (unprotected in the unit and tarnished?) would
> affect the reliability of the switches, wouldn't it?
>
> Jack
>
>
>
>
>
>
> Rob Mongey <[log in to unmask]>@freelists.org
> 4Apr2002 06:08 AM
>
> Please respond to [log in to unmask]
>
> Sent by: [log in to unmask]
>
>
>
> To: [log in to unmask]
> cc:
>
> Subject: [pcdlist] Re: Immersion Silver
> Retain Until: 05/04/2002 Retention Category: G90 - Information and Reports
> Caterpillar Confidential: Green
>
>
>
> Hi all,
> Good to see Immersion Silver is starting to take off. We've been
using
> it
> in here for about two years, and it is now our prefered board finish (We
> get silver finish unless we specify differently.) More common useage will
> mean that maybe more Far Eastern shops will start supplying it.
>
> We started to use Silver because it is so adaptable to what we need
> our
> PCB surface finish to do, namely:
>
> 1. Good solderability. (Silver excels at this, ask any vendor).
> 2. Flatness for fine pitch SMT. (Silver is as flat, if not flatter than
> Gold)
> 3. Mechanical strength for carbon pill switch contacts / Elastomer
> contacts. ( Flash Gold is weak, and hard Gold gives SMT solderability
> problems)
> 4. Stability for compression power contacts. (We have power contacts on
our
> PCBs that mate to battery contacts via a spring compression. We found that
> the nickel under gold can cause problems with electrochemical migration
> toward our battery contact.)
>
> Immersion silver is the most suitable choice that can do all four. I'd use
> gold as an alternative, but we'd have to compromise our designs somewhat.
>
> We specify our Silver finish as 0.1 Microns Min to 0.2 Microns Max, over
> bare copper. Anyone else do it differently? Or do we trust our board
shops?
> :)
>
> Regards,
> Rob Mongey.
> CAD Technician.
>
> Robert Mongey <[log in to unmask]> Tel : +353 (0)91 774300
> Bio Medical Research Direct : +353 (0)91 774338
> BMR House, Fax : +353 (0)91 774302
> Parkmore Business Park West, Mobile : +353 (0)87 2485262
> Galway
> Rep of Ireland.
>
> --------------------------------------------------------------------------
--
>
> -----
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--
>
> -----
>
> --------------------------------------------------------------------------
-------
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ext.5315
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Date: Thu, 18 Apr 2002 13:40:20 +0100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Eric Dawson <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Eric Dawson <[log in to unmask]>
Subject: Re: Immersion Silver
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Hi Dougal,
OSP sounds attractive but can I seek your views on a couple of points?
We double side reflow and clean between operations to avoid baking the flux
on. These are complex boards and can take several days to progress through
the line. Will the OSP stay fresh for the second side reflow or would we
have to treat the surface? Will cleaning take it off? (Prozone).
Regards
Eric Dawson
> -----Original Message-----
> From: Dougal Stewart [SMTP:[log in to unmask]]
> Sent: Thursday, April 18, 2002 10:57 AM
> To: [log in to unmask]
> Subject: Re: [TN] Immersion Silver
>
> I would like to know why people don't use OSP - from a board shop's
> viewpoint, it is the best finish to put on a board - why ? because it is
> very simple chemistry, puts no thermal shock on the product, is applied on
> a
> SHORT conveyor line, and can be easily reworked unlike ANY of the other
> finishes. The assembly guys don't like it if they start assembling a
> product
> and then stop because they don't have the parts to finish the job, but
> anyone that puts a board into assembly without the ability to finish it
> within 6 hours obviously knows nothing about world class manufacturing
> practise. As for shelf life, if your stock is even 2 years old, send the
> boards back to the board shop and for a small fee they just put them back
> down the line again and you have a finish that is good as new, without
> having undergone a vicious chemical attack to remove the finish.
> Just my thoughts !
> Dougal Stewart
>
> email: [log in to unmask]
> phone: +44 1896 822204
> mob: +44 7984 629667
> ----- Original Message -----
> From: "Jack C. Olson" <[log in to unmask]>
> To: <[log in to unmask]>
> Sent: Wednesday, April 17, 2002 4:22 PM
> Subject: Re: [TN] Immersion Silver
>
>
> > Hmmm,
> >
> > Well, at some point in EVERY new technology it was used by less
> > than 3% of the world, eh? Guess I'm just a trailblazer....
> >
> > naw, just kiddin ya.
> > I subscribed to a magazine called Circuitree, and the last issue
> > came bundled with another publication called "The Board Authority"
> > which has some very well written (and well researched!) articles
> > on alternate finishes. I can't see any downside to using silver
> > in our applications, and I've looked all through the archives for
> > Technet, DesignerCouncil and PCDlist forums, still no show-stoppers,
> > so we tried it for the first time on our last design. Yes, HASL and
> > NiGold do work fine, but maybe we can get the same functionality
> > for cheaper, and do our fab vendor a favor in the process, since
> > they seem to prefer it (less steps? more reliable? not sure) maybe
> > the fab guys can answer that one....
> >
> > Jack
> >
> >
> >
> >
> >
> > "WEEKES, MICHAEL HS-SNS" <[log in to unmask]>
> > 17Apr2002 09:16 AM
> >
> >
> > To: "'TechNet E-Mail Forum.'" <[log in to unmask]>
> > "'Jack C. Olson'" <[log in to unmask]>
> > cc:
> >
> > Subject: RE: [TN] Immersion Silver
> > Retain Until: 05/17/2002 Retention Category: G90 - Information and
> Reports
> > Caterpillar Confidential: Green
> >
> >
> > There must be some reason why less than 3% of the world has moved toward
> > immersion silver. Why doesn't HASL or NiGold work for your application?
> >
> > Mike
> >
> > -----Original Message-----
> > From: Jack C. Olson [mailto:[log in to unmask]]
> > Sent: Wednesday, April 17, 2002 7:39 AM
> > To: [log in to unmask]
> > Subject: Re: [TN] Immersion Silver
> >
> >
> > The PCD magazine list went down before I could get an
> > answer to this question, does anyone have experience
> > with silver and contact switches?
> >
> > ==============================================
> >
> > Most sources say a silver surface will not be solderable
> > after a month or so unprotected. (Even in a baggie it will
> > be okay a year later?)
> > Anyway, you say it is good for switches, which would solve
> > some of our hard gold plating problems.
> >
> > But I would think the "unsolderability" of the aged silver
> > surface (unprotected in the unit and tarnished?) would
> > affect the reliability of the switches, wouldn't it?
> >
> > Jack
> >
> >
> >
> >
> >
> >
> > Rob Mongey <[log in to unmask]>@freelists.org
> > 4Apr2002 06:08 AM
> >
> > Please respond to [log in to unmask]
> >
> > Sent by: [log in to unmask]
> >
> >
> >
> > To: [log in to unmask]
> > cc:
> >
> > Subject: [pcdlist] Re: Immersion Silver
> > Retain Until: 05/04/2002 Retention Category: G90 - Information and
> Reports
> > Caterpillar Confidential: Green
> >
> >
> >
> > Hi all,
> > Good to see Immersion Silver is starting to take off. We've been
> using
> > it
> > in here for about two years, and it is now our prefered board finish (We
> > get silver finish unless we specify differently.) More common useage
> will
> > mean that maybe more Far Eastern shops will start supplying it.
> >
> > We started to use Silver because it is so adaptable to what we need
> > our
> > PCB surface finish to do, namely:
> >
> > 1. Good solderability. (Silver excels at this, ask any vendor).
> > 2. Flatness for fine pitch SMT. (Silver is as flat, if not flatter than
> > Gold)
> > 3. Mechanical strength for carbon pill switch contacts / Elastomer
> > contacts. ( Flash Gold is weak, and hard Gold gives SMT solderability
> > problems)
> > 4. Stability for compression power contacts. (We have power contacts on
> our
> > PCBs that mate to battery contacts via a spring compression. We found
> that
> > the nickel under gold can cause problems with electrochemical migration
> > toward our battery contact.)
> >
> > Immersion silver is the most suitable choice that can do all four. I'd
> use
> > gold as an alternative, but we'd have to compromise our designs
> somewhat.
> >
> > We specify our Silver finish as 0.1 Microns Min to 0.2 Microns Max, over
> > bare copper. Anyone else do it differently? Or do we trust our board
> shops?
> > :)
> >
> > Regards,
> > Rob Mongey.
> > CAD Technician.
> >
> > Robert Mongey <[log in to unmask]> Tel : +353 (0)91 774300
> > Bio Medical Research Direct : +353 (0)91 774338
> > BMR House, Fax : +353 (0)91 774302
> > Parkmore Business Park West, Mobile : +353 (0)87 2485262
> > Galway
> > Rep of Ireland.
> >
> >
> --------------------------------------------------------------------------
> --
> >
> > -----
> > Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
> > To unsubscribe, send a message to [log in to unmask] with following text
> in
> > the BODY (NOT the subject field): SIGNOFF Technet
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> > SET
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> > To receive ONE mailing per day of all the posts: send e-mail to
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> > Search the archives of previous posts at:
> http://listserv.ipc.org/archives
> > Please visit IPC web site http://www.ipc.org/html/forum.htm for
> additional
> > information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700
> > ext.5315
> >
> --------------------------------------------------------------------------
> --
> >
> > -----
> >
> >
> --------------------------------------------------------------------------
> -------
> > Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
> > To unsubscribe, send a message to [log in to unmask] with following text
> in
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> > Please visit IPC web site http://www.ipc.org/html/forum.htm for
> additional
> > information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700
> ext.5315
> >
> --------------------------------------------------------------------------
> -------
>
> --------------------------------------------------------------------------
> -------
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=========================================================================
Date: Thu, 18 Apr 2002 08:42:17 EDT
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Rick Fudalewski <[log in to unmask]>
Subject: Re: Immersion Silver
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="part1_6c.1ae42a9f.29f01929_boundary"
--part1_6c.1ae42a9f.29f01929_boundary
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
There are a couple of drawbacks to OSP from an assembly standpoint
One is
that we would get occasional "busts" where the solderability of the pads was
poor on a few pads on the board.
The other area where OSP can fail is with via in pad (VIP) product. If there
is any residue remaining in the holes it will cause a degradation of the OSP
coating.
determine to not be the OSP process at fault, but rather things like unseen
soldermask residues or incomplete removal of the tin etch resist.
Doug, this seems to be a problem with your board manufactures control of the
process.
regards
Rich Fudalewski
FCT
--part1_6c.1ae42a9f.29f01929_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>There are a couple of drawbacks to OSP from an assembly standpoint
<BR>
<BR>One is
<BR>that we would get occasional "busts" where the solderability of the pads was
<BR>poor on a few pads on the board.
<BR>
<BR>The other area where OSP can fail is with via in pad (VIP) product. If there
<BR>is any residue remaining in the holes it will cause a degradation of the OSP
<BR>coating.
<BR>
<BR>determine to not be the OSP process at fault, but rather things like unseen
<BR>soldermask residues or incomplete removal of the tin etch resist.
<BR>
<BR>Doug, this seems to be a problem with your board manufactures control of the process.
<BR>
<BR>regards
<BR>
<BR>Rich Fudalewski
<BR>FCT</FONT></HTML>
--part1_6c.1ae42a9f.29f01929_boundary--
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=========================================================================
Date: Thu, 18 Apr 2002 08:41:04 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"McMullen, Kerry" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "McMullen, Kerry" <[log in to unmask]>
Subject: Re: Immersion Silver
X-To: Earl Moon <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Now I am confused.
How can you use Immersion Silver on a Class II product if it is not UL or
Bellcore approved?
-----Original Message-----
From: Earl Moon [mailto:[log in to unmask]]
Sent: Wednesday, April 17, 2002 4:43 PM
To: [log in to unmask]
Subject: Re: [TN] Immersion Silver
Right on and count me as an additional 1% and more if more customers asked
more suppliers to use silver.
Earl
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Date: Thu, 18 Apr 2002 07:54:01 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Immersion Silver
X-To: [log in to unmask]
Some well said points. I'm having the same problems now with ENIG as some
areas and pads solder well, others don't because - I don't know yet but
black pad is not an issue. This too is a very expensive proposition just as
with OSP or any other solder termination area sufrace finish.
Earl Moon
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Date: Thu, 18 Apr 2002 07:59:23 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Immersion Silver
X-To: [log in to unmask]
Kerry,
You're right. I think someone else addressed the approval process as waiting
to catch up with reality or some such thing. Again, I, and many others in
the 3% category, have been using silver since its inception - about 1995, I
think.
Many of us don't use the solder termination area finish for this reason.
Most don't seem to use it because it hasn't "caught on" yet.
Earl
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Date: Thu, 18 Apr 2002 08:12:34 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: "Ted Tontis, C.I.D." <[log in to unmask]>
Subject: Re: IPC SMT FOOTPRINT DESIGN GUIDLINES VS SUPPLIERS
X-To: [log in to unmask]
MIME-Version: 1.0
Content-Type: text/plain
Jack,
I just heard that IPC is working on a new calculator. This new
calculator will give you three footprint dimensions for the same part. One
would be for a HDI design another would be for a design that is not quite as
heavily populated as HDI and the last one would be for a design that would
have a need for normal footprints. I have no idea when this new calculator
will be available, but there working on it.
Regards,
Ted Tontis
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Date: Thu, 18 Apr 2002 08:11:54 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: IPC SMT FOOTPRINT DESIGN GUIDLINES VS SUPPLIERS
X-To: "Ted Tontis, C.I.D." <[log in to unmask]>
Good input so maybe someone at IPC could shed some light on this. It could
save my dumb ass and those of many others. This starting from scratch sucks
so far.
MoonMan
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Date: Thu, 18 Apr 2002 08:37:52 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
[log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Dave Hillman <[log in to unmask]>
Subject: Re: Immersion Silver
X-To: [log in to unmask]
MIME-Version: 1.0
Content-type: text/plain; charset="us-ascii"
Hi Doug! OSP is a wonderful surface finish in many situations but there are
some use applications where the other finish alternatives have an
advantage:
1) Field repair - OSPs don't provide the long term solderability on pwa's
which have been in the field for a number of years which sometimes are
subjected to upgrades/changes. It is typically an uphill struggle to have
good solderability for HASL for servicing an assembly which has been in the
field for 5-10 years anyway and OSPs just give up the ghost way to early in
comparison to metallic surface finishes.
2) Multiple thermal excursion processes - it is not uncommon on some
complicated assemblies to have 2 reflow excursions (top/bottom), an odd
form component attach excursion, an adhesive cure excursion, and possibly a
repair excursion. Add in a couple of cleaning steps and you really push an
OSP to the limit.
OSPs have a definite place in electronics assembly - I just look at them
as one "tool" in our toolbox of surface finishes for the different
soldering processes used in the industry. We use OSPs at Rockwell Collins
but in very specific applications/designs. We are also using Immersion
silver, Immersion tin, and ENIG very successfully as well.
Dave Hillman
Rockwell Collins
[log in to unmask]
Dougal Stewart <[log in to unmask]>@ipc.org> on 04/18/2002
04:56:52 AM
Please respond to Dougal Stewart <[log in to unmask]>
Sent by: TechNet <[log in to unmask]>
To: [log in to unmask]
cc:
Subject: Re: [TN] Immersion Silver
I would like to know why people don't use OSP - from a board shop's
viewpoint, it is the best finish to put on a board - why ? because it is
very simple chemistry, puts no thermal shock on the product, is applied on
a
SHORT conveyor line, and can be easily reworked unlike ANY of the other
finishes. The assembly guys don't like it if they start assembling a
product
and then stop because they don't have the parts to finish the job, but
anyone that puts a board into assembly without the ability to finish it
within 6 hours obviously knows nothing about world class manufacturing
practise. As for shelf life, if your stock is even 2 years old, send the
boards back to the board shop and for a small fee they just put them back
down the line again and you have a finish that is good as new, without
having undergone a vicious chemical attack to remove the finish.
Just my thoughts !
Dougal Stewart
email: [log in to unmask]
phone: +44 1896 822204
mob: +44 7984 629667
----- Original Message -----
From: "Jack C. Olson" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Wednesday, April 17, 2002 4:22 PM
Subject: Re: [TN] Immersion Silver
> Hmmm,
>
> Well, at some point in EVERY new technology it was used by less
> than 3% of the world, eh? Guess I'm just a trailblazer....
>
> naw, just kiddin ya.
> I subscribed to a magazine called Circuitree, and the last issue
> came bundled with another publication called "The Board Authority"
> which has some very well written (and well researched!) articles
> on alternate finishes. I can't see any downside to using silver
> in our applications, and I've looked all through the archives for
> Technet, DesignerCouncil and PCDlist forums, still no show-stoppers,
> so we tried it for the first time on our last design. Yes, HASL and
> NiGold do work fine, but maybe we can get the same functionality
> for cheaper, and do our fab vendor a favor in the process, since
> they seem to prefer it (less steps? more reliable? not sure) maybe
> the fab guys can answer that one....
>
> Jack
>
>
>
>
>
> "WEEKES, MICHAEL HS-SNS" <[log in to unmask]>
> 17Apr2002 09:16 AM
>
>
> To: "'TechNet E-Mail Forum.'" <[log in to unmask]>
> "'Jack C. Olson'" <[log in to unmask]>
> cc:
>
> Subject: RE: [TN] Immersion Silver
> Retain Until: 05/17/2002 Retention Category: G90 - Information and
Reports
> Caterpillar Confidential: Green
>
>
> There must be some reason why less than 3% of the world has moved toward
> immersion silver. Why doesn't HASL or NiGold work for your application?
>
> Mike
>
> -----Original Message-----
> From: Jack C. Olson [mailto:[log in to unmask]]
> Sent: Wednesday, April 17, 2002 7:39 AM
> To: [log in to unmask]
> Subject: Re: [TN] Immersion Silver
>
>
> The PCD magazine list went down before I could get an
> answer to this question, does anyone have experience
> with silver and contact switches?
>
> ==============================================
>
> Most sources say a silver surface will not be solderable
> after a month or so unprotected. (Even in a baggie it will
> be okay a year later?)
> Anyway, you say it is good for switches, which would solve
> some of our hard gold plating problems.
>
> But I would think the "unsolderability" of the aged silver
> surface (unprotected in the unit and tarnished?) would
> affect the reliability of the switches, wouldn't it?
>
> Jack
>
>
>
>
>
>
> Rob Mongey <[log in to unmask]>@freelists.org
> 4Apr2002 06:08 AM
>
> Please respond to [log in to unmask]
>
> Sent by: [log in to unmask]
>
>
>
> To: [log in to unmask]
> cc:
>
> Subject: [pcdlist] Re: Immersion Silver
> Retain Until: 05/04/2002 Retention Category: G90 - Information and
Reports
> Caterpillar Confidential: Green
>
>
>
> Hi all,
> Good to see Immersion Silver is starting to take off. We've been
using
> it
> in here for about two years, and it is now our prefered board finish (We
> get silver finish unless we specify differently.) More common useage will
> mean that maybe more Far Eastern shops will start supplying it.
>
> We started to use Silver because it is so adaptable to what we need
> our
> PCB surface finish to do, namely:
>
> 1. Good solderability. (Silver excels at this, ask any vendor).
> 2. Flatness for fine pitch SMT. (Silver is as flat, if not flatter than
> Gold)
> 3. Mechanical strength for carbon pill switch contacts / Elastomer
> contacts. ( Flash Gold is weak, and hard Gold gives SMT solderability
> problems)
> 4. Stability for compression power contacts. (We have power contacts on
our
> PCBs that mate to battery contacts via a spring compression. We found
that
> the nickel under gold can cause problems with electrochemical migration
> toward our battery contact.)
>
> Immersion silver is the most suitable choice that can do all four. I'd
use
> gold as an alternative, but we'd have to compromise our designs somewhat.
>
> We specify our Silver finish as 0.1 Microns Min to 0.2 Microns Max, over
> bare copper. Anyone else do it differently? Or do we trust our board
shops?
> :)
>
> Regards,
> Rob Mongey.
> CAD Technician.
>
> Robert Mongey <[log in to unmask]> Tel : +353 (0)91 774300
> Bio Medical Research Direct : +353 (0)91 774338
> BMR House, Fax : +353 (0)91 774302
> Parkmore Business Park West, Mobile : +353 (0)87 2485262
> Galway
> Rep of Ireland.
>
>
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>
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>
> -----
>
>
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Date: Thu, 18 Apr 2002 08:38:33 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Barry Gallegos <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Barry Gallegos <[log in to unmask]>
Subject: OSP
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Good morning T-net.
Can some one tell me what the Organic in OSP is.
Barry.
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Date: Thu, 18 Apr 2002 12:11:27 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Wenger, George M." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Wenger, George M." <[log in to unmask]>
Subject: Re: Immersion Silver
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
Kerry,
Telcordia and UL don't "approve" surface finishes they have end point =
and use requirments that products need to meet. Our immersion silver =
boards meet UL Flame Only testing and pass all of the Telcordia =
GR-78CORE requirments
George
George M. Wenger (908)-546-4531 [log in to unmask]
Distinguished Member Technical Staff
Celiant Corporation, FMA Lab, 40 Technology Drive, NJ 07059
-----Original Message-----
From: McMullen, Kerry [mailto:[log in to unmask]]
Sent: Thursday, April 18, 2002 8:41 AM
To: [log in to unmask]
Subject: Re: [TN] Immersion Silver
Now I am confused.
How can you use Immersion Silver on a Class II product if it is not UL =
or
Bellcore approved?
-----Original Message-----
From: Earl Moon [mailto:[log in to unmask]]
Sent: Wednesday, April 17, 2002 4:43 PM
To: [log in to unmask]
Subject: Re: [TN] Immersion Silver
Right on and count me as an additional 1% and more if more customers =
asked
more suppliers to use silver.
Earl
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Date: Thu, 18 Apr 2002 09:31:57 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Jana Carraway <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Jana Carraway <[log in to unmask]>
Subject: Re: OSP
X-To: Barry Gallegos <[log in to unmask]>
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit
Substituted benzimidizole-based, benzotriazoles, and imidazole chemistries.
My info is a bit old, there may be new formulations available.
Jana Carraway
MSEI
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Barry Gallegos
Sent: Thursday, April 18, 2002 7:39 AM
To: [log in to unmask]
Subject: [TN] OSP
Good morning T-net.
Can some one tell me what the Organic in OSP is.
Barry.
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Date: Thu, 18 Apr 2002 11:41:55 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: OSP
X-To: [log in to unmask]
Jana,
I too thank you for the input. Do these chemistries equate in some way to
"fluxes?"
Earl
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Date: Thu, 18 Apr 2002 13:29:13 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"McMullen, Kerry" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "McMullen, Kerry" <[log in to unmask]>
Subject: Re: Immersion Silver
X-To: "Wenger, George M." <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Thanks George,
That was the answer I was looking for.
I too plan to use Immersion Silver pretty soon. ENIG is getting boring :)
Kerry
-----Original Message-----
From: Wenger, George M. [mailto:[log in to unmask]]
Sent: Thursday, April 18, 2002 12:11 PM
To: [log in to unmask]
Subject: Re: [TN] Immersion Silver
Kerry,
Telcordia and UL don't "approve" surface finishes they have end point and
use requirments that products need to meet. Our immersion silver boards
meet UL Flame Only testing and pass all of the Telcordia GR-78CORE
requirments
George
George M. Wenger (908)-546-4531 [log in to unmask]
Distinguished Member Technical Staff
Celiant Corporation, FMA Lab, 40 Technology Drive, NJ 07059
-----Original Message-----
From: McMullen, Kerry [mailto:[log in to unmask]]
Sent: Thursday, April 18, 2002 8:41 AM
To: [log in to unmask]
Subject: Re: [TN] Immersion Silver
Now I am confused.
How can you use Immersion Silver on a Class II product if it is not UL or
Bellcore approved?
-----Original Message-----
From: Earl Moon [mailto:[log in to unmask]]
Sent: Wednesday, April 17, 2002 4:43 PM
To: [log in to unmask]
Subject: Re: [TN] Immersion Silver
Right on and count me as an additional 1% and more if more customers asked
more suppliers to use silver.
Earl
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Date: Thu, 18 Apr 2002 10:58:28 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Jana Carraway <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Jana Carraway <[log in to unmask]>
Subject: Re: OSP
X-To: Earl Moon <[log in to unmask]>
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
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Earl, I don't work with fluxes, I can't answer this question.
Jana
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Earl Moon
Sent: Thursday, April 18, 2002 9:42 AM
To: [log in to unmask]
Subject: Re: [TN] OSP
Jana,
I too thank you for the input. Do these chemistries equate in some way to
"fluxes?"
Earl
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Date: Thu, 18 Apr 2002 14:48:46 EDT
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Rick Fudalewski <[log in to unmask]>
Subject: Re: OSP
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="part1_c1.1f67f657.29f06f0e_boundary"
--part1_c1.1f67f657.29f06f0e_boundary
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
i've been reading postings on the net for the last few days and it appears to
me that the people involved in the FAB process that are on the net are either
not responding or looking for work - perhaps?
all these finishes - silver - tin - osp - eng - they all have their place and
application. in today's market they are all approved processes for surface
finishes - replacing HASL in one way or another. i am sure a company has a
preferred finish over the others for one reason or another.
in reading your postings - at times it appears that many of you just haven't
done your homework - for whatever reason.
without asking millions of questions - i think it was Earl who hit the nail
right on the head - they work - period!!!!
why some have failure with one and not the other - when i read - seems like
either the application was wrong - the boards weren't properly processed by
the fabricator - or as i mentioned - you haven't done your homework before
you started having the surface finish applied.
there has been copious amounts of literature floating around for the last
decade - silver - nor tin - nor OSP - or ENG - is preffered one over the
other. they all work.
someone mentioned ENG is boring - so it'll be replaced by silver - if i were
in their shoes - i'd look at the application first - like i previously stated
- they all have their places as a surface finish. if silver is to replace ENG
as a surface finish - then whomever speced ENG on that board in the first
place - didn't do their homework.
OSP - TIN - SILVER - can all be used as HASL replacements - depending on what
the criteria is - but to date - i haven't seen one of them replace ENG nor
Deep Bodied Ni/AU - unless - one of those two finishes shouldn't have been
speced in to begin with.
regards
Rich Fudalewski
FCT
--part1_c1.1f67f657.29f06f0e_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>i've been reading postings on the net for the last few days and it appears to me that the people involved in the FAB process that are on the net are either not responding or looking for work - perhaps?
<BR>
<BR>all these finishes - silver - tin - osp - eng - they all have their place and application. in today's market they are all approved processes for surface finishes - replacing HASL in one way or another. i am sure a company has a preferred finish over the others for one reason or another.
<BR>
<BR>in reading your postings - at times it appears that many of you just haven't done your homework - for whatever reason.
<BR>
<BR>without asking millions of questions - i think it was Earl who hit the nail right on the head - they work - period!!!!
<BR>
<BR>why some have failure with one and not the other - when i read - seems like either the application was wrong - the boards weren't properly processed by the fabricator - or as i mentioned - you haven't done your homework before you started having the surface finish applied.
<BR>
<BR>there has been copious amounts of literature floating around for the last decade - silver - nor tin - nor OSP - or ENG - is preffered one over the other. they all work.
<BR>
<BR>someone mentioned ENG is boring - so it'll be replaced by silver - if i were in their shoes - i'd look at the application first - like i previously stated - they all have their places as a surface finish. if silver is to replace ENG as a surface finish - then whomever speced ENG on that board in the first place - didn't do their homework.
<BR>
<BR>OSP - TIN - SILVER - can all be used as HASL replacements - depending on what the criteria is - but to date - i haven't seen one of them replace ENG nor Deep Bodied Ni/AU - unless - one of those two finishes shouldn't have been speced in to begin with.
<BR>
<BR>regards
<BR>
<BR>Rich Fudalewski
<BR>
<BR>FCT</FONT></HTML>
--part1_c1.1f67f657.29f06f0e_boundary--
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Date: Thu, 18 Apr 2002 13:58:45 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Immersion Silver
X-To: [log in to unmask]
Kerry,
You helped me greatly with your reflow profile. Help me, and us all, again
with the results of your silver findings.
Earl
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Date: Thu, 18 Apr 2002 14:02:29 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: OSP
X-To: [log in to unmask]
Jana,
I appreciate you are not into fluxes and the answer concerning OSP
composition. I'm sure the OSP chemistry is compatible - no kidding - with
current flux chemistries or how could it work
When we used "SealBrite" it was essentiall a flux. Does someone out there
know the answer to my question concerning flux composition in terms of
Jana's answer?
Earl
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Date: Thu, 18 Apr 2002 14:14:43 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: OSP
X-To: Rick Fudalewski <[log in to unmask]>
Outstanding Rick,
I agree and side with Kerry as well but for his "boring" comment. I know he
meant well as we all try CPI.
Other folks, me included, have commented on the lack of board type people
participating enough on this forum. I certainly have done my best to get
them back but probably have bored them and others to leaving because of my
excessive time on the forum.
Phil Hinton said this forum is becoming an "good old boys club" or some such
thing. I agreed then as now but we have the freedom to participate or not.
I just want the facts man, just the facts. I have way more questions than
answers but one thing is sure - we need more fabricators on this thing.
I just finished a concurrent engineering conference with my assembler, my
company, and my fab supplier. Excellent results concerning solder wetting,
or not.
Turns out our great fab supplier (Proto Engineering)provided highly
solderable ENIG boards that didn't look that great after assembly in some
areas. Also turns out, our fantastic assembler (MPI) uses the latest DEK
stencil printers with ProFlo heads. Because of this, and the large pads
required for a few parts, MPI requested steicils with "window pane"
apertures for these large pads. Hence, non wetting on some pad areas. New
one to me but greatly appreciated for us all.
Where have all the board people gone, long time passing. I'll get of the
fourm if it's me but we need fab folks no matter.
MoonMan
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Date: Thu, 18 Apr 2002 14:34:32 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Don Vischulis <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Don Vischulis <[log in to unmask]>
Subject: Re: OSP
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
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Earl:
These do not equate to fluxes. They are thin (monomolecular in some cases)
protective coatings that prevent the copper from oxidizing. They are
removed by the heat of the soldering process (or alcohol). Fluxes on the
other hand become active at elevated temperatures and actually reduce or
remove oxides on the copper surface.
I'm a rusty on the actual chemistry. I certain there are others who can
fill us in on that aspect if needed.
Don Vischulis
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Jana Carraway
Sent: Thursday, April 18, 2002 12:58 PM
To: [log in to unmask]
Subject: Re: [TN] OSP
Earl, I don't work with fluxes, I can't answer this question.
Jana
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Earl Moon
Sent: Thursday, April 18, 2002 9:42 AM
To: [log in to unmask]
Subject: Re: [TN] OSP
Jana,
I too thank you for the input. Do these chemistries equate in some way to
"fluxes?"
Earl
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Date: Thu, 18 Apr 2002 15:56:35 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"McMullen, Kerry" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "McMullen, Kerry" <[log in to unmask]>
Subject: Re: Immersion Silver
X-To: Earl Moon <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Hi Earl / Rick F.
I am still doing my research. I recently heard you have to make sure that
your soldermask is compatible with the Immersion Silver process. That is
where I am at now in my evaluation.
Rick F. made some good points. NiAu , Ag, Sn, HASL should be selected based
on the design. For example, I would rather press compliant pins into HASL
plated through holes than NiAU holes.
Cheers,
Kerry
-----Original Message-----
From: Earl Moon [mailto:[log in to unmask]]
Sent: Thursday, April 18, 2002 2:59 PM
To: [log in to unmask]; McMullen, Kerry
Subject: Re: Immersion Silver
Kerry,
You helped me greatly with your reflow profile. Help me, and us all, again
with the results of your silver findings.
Earl
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Date: Thu, 18 Apr 2002 15:21:15 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Immersion Silver
X-To: [log in to unmask]
Kerry,
The soldermask issue must be addressed for all board types and solder
termination area finishes. Please remember one important thing, as you know
already, and that is you are not pressing anything into a thin surface
finish. You are pressing into a carefully drilled, prepared, and copper
plated hole. If the drilling, hole wall preparation, and copper plating is
not as CAREFULLY SPECIFIED, you will not get the effects specified.
Earl
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Date: Thu, 18 Apr 2002 16:31:19 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Guy Ramsey <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Guy Ramsey <[log in to unmask]>
Subject: Re: OSP
X-To: [log in to unmask]
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="----=_NextPart_000_0005_01C1E6F6.784C8AB0"
This is a multi-part message in MIME format.
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Content-Type: text/plain;
charset="iso-8859-1"
Content-Transfer-Encoding: 7bit
Am I cranky today; or was that post too preachy.
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Rick Fudalewski
Sent: Thursday, April 18, 2002 2:49 PM
To: [log in to unmask]
Subject: Re: [TN] OSP
i've been reading postings on the net for the last few days and it appears
to me that the people involved in the FAB process that are on the net are
either not responding or looking for work - perhaps?
all these finishes - silver - tin - osp - eng - they all have their place
and application. in today's market they are all approved processes for
surface finishes - replacing HASL in one way or another. i am sure a company
has a preferred finish over the others for one reason or another.
in reading your postings - at times it appears that many of you just
haven't done your homework - for whatever reason.
without asking millions of questions - i think it was Earl who hit the
nail right on the head - they work - period!!!!
why some have failure with one and not the other - when i read - seems
like either the application was wrong - the boards weren't properly
processed by the fabricator - or as i mentioned - you haven't done your
homework before you started having the surface finish applied.
there has been copious amounts of literature floating around for the last
decade - silver - nor tin - nor OSP - or ENG - is preffered one over the
other. they all work.
someone mentioned ENG is boring - so it'll be replaced by silver - if i
were in their shoes - i'd look at the application first - like i previously
stated - they all have their places as a surface finish. if silver is to
replace ENG as a surface finish - then whomever speced ENG on that board in
the first place - didn't do their homework.
OSP - TIN - SILVER - can all be used as HASL replacements - depending on
what the criteria is - but to date - i haven't seen one of them replace ENG
nor Deep Bodied Ni/AU - unless - one of those two finishes shouldn't have
been speced in to begin with.
regards
Rich Fudalewski
FCT
------=_NextPart_000_0005_01C1E6F6.784C8AB0
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charset="iso-8859-1"
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<DIV><FONT color=3D#0000ff face=3DArial size=3D2><SPAN =
class=3D81243020-18042002>Am I=20
cranky today; or was that post too preachy. </SPAN></FONT></DIV>
<BLOCKQUOTE=20
style=3D"BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; PADDING-LEFT: =
5px">
<DIV class=3DOutlookMessageHeader><FONT face=3D"Times New Roman"=20
size=3D2>-----Original Message-----<BR><B>From:</B> TechNet=20
[mailto:[log in to unmask]]<B>On Behalf Of</B> Rick =
Fudalewski<BR><B>Sent:</B>=20
Thursday, April 18, 2002 2:49 PM<BR><B>To:</B>=20
[log in to unmask]<BR><B>Subject:</B> Re: [TN] =
OSP<BR><BR></DIV></FONT><FONT=20
face=3Darial,helvetica><FONT size=3D2>i've been reading postings on =
the net for=20
the last few days and it appears to me that the people involved in the =
FAB=20
process that are on the net are either not responding or looking for =
work -=20
perhaps? <BR><BR>all these finishes - silver - tin - osp - eng - they =
all have=20
their place and application. in today's market they are all approved =
processes=20
for surface finishes - replacing HASL in one way or another. i am sure =
a=20
company has a preferred finish over the others for one reason or =
another.=20
<BR><BR>in reading your postings - at times it appears that many of =
you just=20
haven't done your homework - for whatever reason. <BR><BR>without =
asking=20
millions of questions - i think it was Earl who hit the nail right on =
the head=20
- they work - period!!!! <BR><BR>why some have failure with one and =
not the=20
other - when i read - seems like either the application was wrong - =
the boards=20
weren't properly processed by the fabricator - or as i mentioned - you =
haven't=20
done your homework before you started having the surface finish =
applied.=20
<BR><BR>there has been copious amounts of literature floating around =
for the=20
last decade - silver - nor tin - nor OSP - or ENG - is preffered one =
over the=20
other. they all work. <BR><BR>someone mentioned ENG is boring - so =
it'll be=20
replaced by silver - if i were in their shoes - i'd look at the =
application=20
first - like i previously stated - they all have their places as a =
surface=20
finish. if silver is to replace ENG as a surface finish - then =
whomever speced=20
ENG on that board in the first place - didn't do their homework. =
<BR><BR>OSP -=20
TIN - SILVER - can all be used as HASL replacements - depending on =
what the=20
criteria is - but to date - i haven't seen one of them replace ENG nor =
Deep=20
Bodied Ni/AU - unless - one of those two finishes shouldn't have been =
speced=20
in to begin with. <BR><BR>regards <BR><BR>Rich Fudalewski =
<BR><BR>FCT</FONT>=20
</FONT></BLOCKQUOTE></BODY></HTML>
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Date: Thu, 18 Apr 2002 15:40:19 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: OSP
X-To: [log in to unmask]
cranky my dumbass. too preachy (how do you spell this stuff anyway), never
you. plus, you never see me getting pissed.
good stuff Guy as you see me slipping into a void by not following required,
specified grammatic practices.
MoonMan
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Date: Thu, 18 Apr 2002 13:51:14 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Barmuta, Mike" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Barmuta, Mike" <[log in to unmask]>
Subject: Re: OSP
X-To: Earl Moon <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Earl: The current OSP coatings are not based on any type of flux chemistry
such as the old Sealbrite. That was a rosin based product from London
Chemical Co.
The OSP forms an organo-metallic complex on the surface of the copper to
protect it. It does not aid or contribute to the fluxing operation. The
coating is actually broken down by the flux allowing you to solder to non
oxidized copper.
Regards
Michael Barmuta
Staff Engineer
Fluke Corp.
Everett WA
425-446-6076
-----Original Message-----
From: Earl Moon [mailto:[log in to unmask]]
Sent: Thursday, April 18, 2002 12:02 PM
To: [log in to unmask]
Subject: Re: [TN] OSP
Jana,
I appreciate you are not into fluxes and the answer concerning OSP
composition. I'm sure the OSP chemistry is compatible - no kidding - with
current flux chemistries or how could it work
When we used "SealBrite" it was essentiall a flux. Does someone out there
know the answer to my question concerning flux composition in terms of
Jana's answer?
Earl
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Date: Thu, 18 Apr 2002 14:07:20 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Jana Carraway <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Jana Carraway <[log in to unmask]>
Subject: Re: OSP
X-To: Earl Moon <[log in to unmask]>
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
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Earl, I read your question incorrectly. When you said equate to, I read
that as in having a similar component, not as in being compatible with
fluxes. I think the best answer is that it is something that needs to be
tested on a case by case basis.
Jana
-----Original Message-----
From: Earl Moon [mailto:[log in to unmask]]
Sent: Thursday, April 18, 2002 12:02 PM
To: [log in to unmask]; [log in to unmask]
Subject: Re: OSP
Jana,
I appreciate you are not into fluxes and the answer concerning OSP
composition. I'm sure the OSP chemistry is compatible - no kidding - with
current flux chemistries or how could it work
When we used "SealBrite" it was essentiall a flux. Does someone out there
know the answer to my question concerning flux composition in terms of
Jana's answer?
Earl
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Date: Thu, 18 Apr 2002 15:57:15 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: OSP
X-To: [log in to unmask]
Mike,
I thank you much and am filing your answer away so I needn't ask the
question again.
You seem very bright and probably are young, relatively, how do you know
this stuff?
Earl
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Date: Thu, 18 Apr 2002 16:32:33 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Hole cracking of Teflon PCB after screwing
X-To: Shirley Xiao <[log in to unmask]>
Mime-Version: 1.0
Content-type: text/plain; charset=us-ascii
that even sounds painfull, sorry couldn't resist!
Shirley Xiao <[log in to unmask]> on 04/18/2002 05:00:47 AM
Please respond to "TechNet E-Mail Forum." <[log in to unmask]>; Please respond to
Shirley Xiao <[log in to unmask]>
To: [log in to unmask]
cc: (bcc: Warren Crow/US/I-O INC)
Subject: [TN] Hole cracking of Teflon PCB after screwing
One batch of double sided PCB using teflon materials
have hole cracking problems after screwing by electric
driver.The borad is easy to break if I bent it. Is it
do to laminate quality problem?
What kind of test shall I have?
Thanks in advance!
__________________________________________________
Do You Yahoo!?
Yahoo! Tax Center - online filing with TurboTax
http://taxes.yahoo.com/
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Date: Thu, 18 Apr 2002 17:15:25 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Scott Kauling <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Scott Kauling <[log in to unmask]>
Organization: Tri-onics, Inc.
Subject: Silver
With all of the discussion about the immersion silver, I have a few
questions.
Why can you not use silver jumper wire per IPC-A-610, but it is OK to use
it for a board finish?
I was given a sample of a conductive pen to try as an alternate for jumper
wires and it contains silver. Is anyone using a product such as this on
production boards or is this something that should be kept in the
engineering lab as products are being developed?
I am sure that you folks will clear up my confusion.
SCOTT
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Date: Thu, 18 Apr 2002 15:20:35 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Ken Patel <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Ken Patel <[log in to unmask]>
Organization: interWAVE Communications, Inc.
Subject: Via in Pad: Filling of vias using silver epoxy!?!?
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit
Guys,
I am dealing with high frequency board which is 25 mil thick and made of
Rogers material. The other side is totally exposed copper. How should I
handle as there via in pads (VIP)? I have heard about filling the vias
using silver epoxy and then plating it over. Can someone shed some more
light?
re,
ken patel
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Date: Thu, 18 Apr 2002 19:15:08 EDT
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Gary Ferrari <[log in to unmask]>
Subject: Re: IPC SMT FOOTPRINT DESIGN GUIDLINES VS SUPPLIERS
MIME-Version: 1.0
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boundary="part1_14f.c89f5c6.29f0ad7c_boundary"
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I would like to address a few of the comments that have been made.
First, when the same component parameters and design fillet goals are input
into the current web based calculator they should yield the same land pattern
as listed in the RLP section. We have on occasion found an error in the
component data listed in the hard copy or web calculator and have made
appropriate corrects. Any discrepancies found should be reported to John
Perry at IPC.
Second is that the calculator is based on the same principles as found in the
hard copy of the standard. It is true that land patterns for the newer
components may not have been tested as the earlier ones were. But in many
cases the basic principles remain untouched. However, the land pattern
committee does approve each new pattern based on an assessment culled from
their own experiences with that component as well as input from other
industry sources.
The last issue is that the 782 land pattern committee is currently working on
a complete revision to our land pattern document. I would point out that one
should not perceive the revised document as an indication that there is
something wrong with the current land patterns. This effort is addressing new
component families as well as a new concept going forward.
The new standard will be identified as IPC-7351 and will be of a format that
provides slash sheets for the various component families. This will enable
new component additions to get released in a much more timely fashion. The
standard will contain four columns of data for each component. The first
column will be the existing 782 pattern data. The next three will represent
minimum, median and maximum applications. All component types not currently
in 782 will be released to this new format. AS we move forward, we will NOT
be adding data under the 782 columns for components not currently listed in
the current 782.
As a general point of information, you will find that the current 782 land
patterns will fall someplace between the minimum and median columns. What is
important to recognize is that compromises were taken to reach the smaller
sizes and it will be quite apparent where they were made. It would be wise
for the designer to obtain approval from those affected by the compromises
before using the smaller sizes.
The first release will contain the current 782 listed components with
additional component slash sheets released in rapid succession thereafter.
Regards,
Gary Ferrari
Executive Director
IPC Designers Council
(860) 350-9300
Fax (413) 771-5386
--part1_14f.c89f5c6.29f0ad7c_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
<HTML><FONT FACE=arial,helvetica><FONT COLOR="#8000ff" SIZE=2 FAMILY="SCRIPT" FACE="Comic Sans MS" LANG="0"><B><I>I would like to address a few of the comments that have been made.<BR>
<BR>
First, when the same component parameters and design fillet goals are input into the current web based calculator they should yield the same land pattern as listed in the RLP section. We have on occasion found an error in the component data listed in the hard copy or web calculator and have made appropriate corrects. Any discrepancies found should be reported to John Perry at IPC.<BR>
<BR>
Second is that the calculator is based on the same principles as found in the hard copy of the standard. It is true that land patterns for the newer components may not have been tested as the earlier ones were. But in many cases the basic principles remain untouched. However, the land pattern committee does approve each new pattern based on an assessment culled from their own experiences with that component as well as input from other industry sources.<BR>
<BR>
The last issue is that the 782 land pattern committee is currently working on a complete revision to our land pattern document. I would point out that one should not perceive the revised document as an indication that there is something wrong with the current land patterns. This effort is addressing new component families as well as a new concept going forward.<BR>
<BR>
The new standard will be identified as IPC-7351 and will be of a format that provides slash sheets for the various component families. This will enable new component additions to get released in a much more timely fashion. The standard will contain four columns of data for each component. The first column will be the existing 782 pattern data. The next three will represent minimum, median and maximum applications. All component types not currently in 782 will be released to this new format. AS we move forward, we will NOT be adding data under the 782 columns for components not currently listed in the current 782.<BR>
<BR>
As a general point of information, you will find that the current 782 land patterns will fall someplace between the minimum and median columns. What is important to recognize is that compromises were taken to reach the smaller sizes and it will be quite apparent where they were made. It would be wise for the designer to obtain approval from those affected by the compromises before using the smaller sizes.<BR>
<BR>
The first release will contain the current 782 listed components with additional component slash sheets released in rapid succession thereafter.<BR>
</FONT><FONT COLOR="#000000" style="BACKGROUND-COLOR: #ffffff" SIZE=2 FAMILY="SCRIPT" FACE="Comic Sans MS" LANG="0"></B></I><BR>
</FONT><FONT COLOR="#8000ff" style="BACKGROUND-COLOR: #ffffff" SIZE=2 FAMILY="SCRIPT" FACE="Comic Sans MS" LANG="0"><B><I>Regards,<BR>
<BR>
Gary Ferrari<BR>
Executive Director<BR>
IPC Designers Council<BR>
(860) 350-9300<BR>
Fax (413) 771-5386</B></I></FONT></HTML>
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Date: Thu, 18 Apr 2002 20:04:42 EDT
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Rick Fudalewski <[log in to unmask]>
Subject: Re: Immersion Silver
MIME-Version: 1.0
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Touche Earl!!
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<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>Touche Earl!!</FONT></HTML>
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Date: Fri, 19 Apr 2002 08:22:40 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Via in Pad: Filling of vias using silver epoxy!?!?
X-To: Ken Patel <[log in to unmask]>
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
Ken,
The process used for my boards is:
1. first drill only the holes to be epoxy filled.
2. plate these holes as normal.
3. fill holes with epoxy (Dupont CB101).
4. grind epoxy flush to board surface.
5. drill and plate all the other holes, thus plating over the filled ones.
Problems are :-
filling holes smaller than about 12 mils (consult your fab house).
filling holes much larger than 25 mils if holes are very shallow (7 mils
deep).
getting the epoxy to stay flush after finish plating, especially with HASL
(ENIG is beautiful). It tends to rise and form bumps
not all fab houses are capable of doing this process well.
I tried it to help with thermal management of conduction cooled boards and
it works well. I specifically mention Dupont material, as some other types
just won't fill the holes (particle size in the compound).
Good luck,
Peter
Ken Patel
<[log in to unmask] To: [log in to unmask]
OM> cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST
Sent by: Aero/ST Group)
TechNet Subject: [TN] Via in Pad: Filling of vias
<[log in to unmask] using silver epoxy!?!?
ORG>
04/19/02
06:20 AM
Please
respond to
"TechNet
E-Mail
Forum.";
Please
respond to
Ken Patel
Guys,
I am dealing with high frequency board which is 25 mil thick and made of
Rogers material. The other side is totally exposed copper. How should I
handle as there via in pads (VIP)? I have heard about filling the vias
using silver epoxy and then plating it over. Can someone shed some more
light?
re,
ken patel
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Date: Thu, 18 Apr 2002 21:30:55 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Wenger, George M." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Wenger, George M." <[log in to unmask]>
Subject: Re: Immersion Silver
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Kerry,
What you heard is partially correct. The exception I take in the =
statement is that you need to make sure that your soldermask is =
compatible with any finial finish that is applied to PWBs after the =
solder mask operation. It is my understanding that because of the =
chemicals and low temperature (compared to other finial =
finishes)associated with immersion silver replacement plating the solder =
mask concern is no worst than other finial finishes. In fact there are =
some fabricators that apply NiAu finial finishes prior to solder mask =
because the sodler mask they use is affected by the electroless nickel =
plating chemistry.
The finial finish needs to be selected based on design, fabrication =
issues, solder joint integrity/reliability, availability, and cost. If =
you're doing SMT reflow of fine pitch components and are required to use =
3 to 6 mil thick stencils you probably need to avoid HASL. If you're =
building 2 to 4 GHz RF products on low low subtrates with long =
microstrips you probably need to avoid the use of NiAu or at least make =
the nickel plating real thin (25-50 micro inches) which presents =
problems to fabricators. If your fabricator has problems controlling =
tin-strip and solder mask processes you probably need to avoid OSP. If =
you fabricator privides boards wrapped with rubber bands or in brown =
paper or if you place boards on trays after reflow assembly rather than =
in metal racks you proably want to stay away fro immersion silver. If =
you need to do wire bonding you'll probably windup using thick =
electrolytic or electroless gold or you might even get away with ENIG. =
On the other hand if you're using 1mm or smaller pitch CSP or area array =
packages or high I/O BGAs you probably need to know as much as possible =
about "Black Pad"
Sorry for the long winded answer but my point is you need to assess the =
compatibility, interactions and requirments associated with fabrication, =
assembly, and use in order to decide what finial surface finish works =
for your application.
-----Original Message-----
From: McMullen, Kerry [mailto:[log in to unmask]]
Sent: Thursday, April 18, 2002 3:57 PM
To: [log in to unmask]
Subject: Re: [TN] Immersion Silver
Hi Earl / Rick F.
I am still doing my research. I recently heard you have to make sure =
that
your soldermask is compatible with the Immersion Silver process. That =
is
where I am at now in my evaluation.
Rick F. made some good points. NiAu , Ag, Sn, HASL should be selected =
based
on the design. For example, I would rather press compliant pins into =
HASL
plated through holes than NiAU holes.
Cheers,
Kerry
-----Original Message-----
From: Earl Moon [mailto:[log in to unmask]]
Sent: Thursday, April 18, 2002 2:59 PM
To: [log in to unmask]; McMullen, Kerry
Subject: Re: Immersion Silver
Kerry,
You helped me greatly with your reflow profile. Help me, and us all, =
again
with the results of your silver findings.
Earl
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Date: Thu, 18 Apr 2002 21:53:03 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Wenger, George M." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Wenger, George M." <[log in to unmask]>
Subject: Re: OSP
MIME-Version: 1.0
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Earl,
I'd like to expand and comment on you question "Where have all the board =
people gone, long time passing". Unfortunately the board people whet by =
the wayside just like many other technical people. Companies have down =
sized their technical efforts and increased their supply chain efforts =
with the rational that we don't have to pay for technical information =
because our suppliers will give us what we need for free. Well the one =
thing most people learn during their life time is you get what you pay =
for. In the past 18 months or more the attendance at technical =
conferences and seminars has decreased, the technical content in email =
forms such as TechNet have decreased and when you ask a supplier for =
technical date you get sales information.
I'm not sure how or if there is going to be a reversal but I sure hope =
that young engineers entering the work place keep letting their =
management know that engineering date not sales information is needed to =
make informed decisions and effective risk assesments.
-----Original Message-----
From: Earl Moon [mailto:[log in to unmask]]
Sent: Thursday, April 18, 2002 3:15 PM
To: [log in to unmask]
Subject: Re: [TN] OSP
Outstanding Rick,
I agree and side with Kerry as well but for his "boring" comment. I know =
he
meant well as we all try CPI.
Other folks, me included, have commented on the lack of board type =
people
participating enough on this forum. I certainly have done my best to get
them back but probably have bored them and others to leaving because of =
my
excessive time on the forum.
Phil Hinton said this forum is becoming an "good old boys club" or some =
such
thing. I agreed then as now but we have the freedom to participate or =
not.
I just want the facts man, just the facts. I have way more questions =
than
answers but one thing is sure - we need more fabricators on this thing.
I just finished a concurrent engineering conference with my assembler, =
my
company, and my fab supplier. Excellent results concerning solder =
wetting,
or not.
Turns out our great fab supplier (Proto Engineering)provided highly
solderable ENIG boards that didn't look that great after assembly in =
some
areas. Also turns out, our fantastic assembler (MPI) uses the latest DEK
stencil printers with ProFlo heads. Because of this, and the large pads
required for a few parts, MPI requested steicils with "window pane"
apertures for these large pads. Hence, non wetting on some pad areas. =
New
one to me but greatly appreciated for us all.
Where have all the board people gone, long time passing. I'll get of the
fourm if it's me but we need fab folks no matter.
MoonMan
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Date: Thu, 18 Apr 2002 22:19:56 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Rob Legg <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Rob Legg <[log in to unmask]>
Subject: Re: IPC SMT FOOTPRINT DESIGN GUIDLINES VS SUPPLIERS
MIME-Version: 1.0
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boundary="----=_NextPart_000_001E_01C1E727.2B7DF3A0"
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------=_NextPart_000_001E_01C1E727.2B7DF3A0
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charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
That's what I like about standards. No ambiguity, good resale value and =
low-cost maintenance for the end user.
RL
----- Original Message -----=20
From: Gary Ferrari=20
To: [log in to unmask]
Sent: Thursday, April 18, 2002 7:15 PM
Subject: Re: [TN] IPC SMT FOOTPRINT DESIGN GUIDLINES VS SUPPLIERS
I would like to address a few of the comments that have been made.
First, when the same component parameters and design fillet goals are =
input into the current web based calculator they should yield the same =
land pattern as listed in the RLP section. We have on occasion found an =
error in the component data listed in the hard copy or web calculator =
and have made appropriate corrects. Any discrepancies found should be =
reported to John Perry at IPC.
Second is that the calculator is based on the same principles as found =
in the hard copy of the standard. It is true that land patterns for the =
newer components may not have been tested as the earlier ones were. But =
in many cases the basic principles remain untouched. However, the land =
pattern committee does approve each new pattern based on an assessment =
culled from their own experiences with that component as well as input =
from other industry sources.
The last issue is that the 782 land pattern committee is currently =
working on a complete revision to our land pattern document. I would =
point out that one should not perceive the revised document as an =
indication that there is something wrong with the current land patterns. =
This effort is addressing new component families as well as a new =
concept going forward.
The new standard will be identified as IPC-7351 and will be of a =
format that provides slash sheets for the various component families. =
This will enable new component additions to get released in a much more =
timely fashion. The standard will contain four columns of data for each =
component. The first column will be the existing 782 pattern data. The =
next three will represent minimum, median and maximum applications. All =
component types not currently in 782 will be released to this new =
format. AS we move forward, we will NOT be adding data under the 782 =
columns for components not currently listed in the current 782.
As a general point of information, you will find that the current 782 =
land patterns will fall someplace between the minimum and median =
columns. What is important to recognize is that compromises were taken =
to reach the smaller sizes and it will be quite apparent where they were =
made. It would be wise for the designer to obtain approval from those =
affected by the compromises before using the smaller sizes.
The first release will contain the current 782 listed components with =
additional component slash sheets released in rapid succession =
thereafter.
Regards,
Gary Ferrari
Executive Director
IPC Designers Council
(860) 350-9300
Fax (413) 771-5386=20
------=_NextPart_000_001E_01C1E727.2B7DF3A0
Content-Type: text/html;
charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META http-equiv=3DContent-Type content=3D"text/html; =
charset=3Diso-8859-1">
<META content=3D"MSHTML 5.50.4522.1800" name=3DGENERATOR>
<STYLE></STYLE>
</HEAD>
<BODY bgColor=3D#dee9ef>
<DIV><FONT face=3DArial size=3D2>That's what I like about standards. No =
ambiguity,=20
good resale value and low-cost maintenance for the end =
user.</FONT></DIV>
<DIV><FONT face=3DArial size=3D2></FONT> </DIV>
<DIV><FONT face=3DArial size=3D2>RL</FONT></DIV>
<BLOCKQUOTE=20
style=3D"PADDING-RIGHT: 0px; PADDING-LEFT: 5px; MARGIN-LEFT: 5px; =
BORDER-LEFT: #000000 2px solid; MARGIN-RIGHT: 0px">
<DIV style=3D"FONT: 10pt arial">----- Original Message ----- </DIV>
<DIV=20
style=3D"BACKGROUND: #e4e4e4; FONT: 10pt arial; font-color: =
black"><B>From:</B>=20
<A [log in to unmask] href=3D"mailto:[log in to unmask]">Gary =
Ferrari</A> </DIV>
<DIV style=3D"FONT: 10pt arial"><B>To:</B> <A [log in to unmask]
href=3D"mailto:[log in to unmask]">[log in to unmask]</A> </DIV>
<DIV style=3D"FONT: 10pt arial"><B>Sent:</B> Thursday, April 18, 2002 =
7:15=20
PM</DIV>
<DIV style=3D"FONT: 10pt arial"><B>Subject:</B> Re: [TN] IPC SMT =
FOOTPRINT=20
DESIGN GUIDLINES VS SUPPLIERS</DIV>
<DIV><BR></DIV><FONT face=3Darial,helvetica><FONT lang=3D0 =
face=3D"Comic Sans MS"=20
color=3D#8000ff size=3D2 FAMILY=3D"SCRIPT"><B><I>I would like to =
address a few of=20
the comments that have been made.<BR><BR>First, when the same =
component=20
parameters and design fillet goals are input into the current web =
based=20
calculator they should yield the same land pattern as listed in the =
RLP=20
section. We have on occasion found an error in the component data =
listed in=20
the hard copy or web calculator and have made appropriate corrects. =
Any=20
discrepancies found should be reported to John Perry at =
IPC.<BR><BR>Second is=20
that the calculator is based on the same principles as found in the =
hard copy=20
of the standard. It is true that land patterns for the newer =
components may=20
not have been tested as the earlier ones were. But in many cases the =
basic=20
principles remain untouched. However, the land pattern committee does =
approve=20
each new pattern based on an assessment culled from their own =
experiences with=20
that component as well as input from other industry =
sources.<BR><BR>The last=20
issue is that the 782 land pattern committee is currently working on a =
complete revision to our land pattern document. I would point out that =
one=20
should not perceive the revised document as an indication that there =
is=20
something wrong with the current land patterns. This effort is =
addressing new=20
component families as well as a new concept going forward.<BR><BR>The =
new=20
standard will be identified as IPC-7351 and will be of a format that =
provides=20
slash sheets for the various component families. This will enable new=20
component additions to get released in a much more timely fashion. The =
standard will contain four columns of data for each component. The =
first=20
column will be the existing 782 pattern data. The next three will =
represent=20
minimum, median and maximum applications. All component types not =
currently in=20
782 will be released to this new format. AS we move forward, we will =
NOT be=20
adding data under the 782 columns for components not currently listed =
in the=20
current 782.<BR><BR>As a general point of information, you will find =
that the=20
current 782 land patterns will fall someplace between the minimum and =
median=20
columns. What is important to recognize is that compromises were taken =
to=20
reach the smaller sizes and it will be quite apparent where they were =
made. It=20
would be wise for the designer to obtain approval from those affected =
by the=20
compromises before using the smaller sizes.<BR><BR>The first release =
will=20
contain the current 782 listed components with additional component =
slash=20
sheets released in rapid succession thereafter.<BR></FONT><FONT =
lang=3D0=20
style=3D"BACKGROUND-COLOR: #ffffff" face=3D"Comic Sans MS" =
color=3D#000000 size=3D2=20
FAMILY=3D"SCRIPT"></B></I><BR></FONT><FONT lang=3D0=20
style=3D"BACKGROUND-COLOR: #ffffff" face=3D"Comic Sans MS" =
color=3D#8000ff size=3D2=20
FAMILY=3D"SCRIPT"><B><I>Regards,<BR><BR>Gary Ferrari<BR>Executive=20
Director<BR>IPC Designers Council<BR>(860) 350-9300<BR>Fax (413)=20
771-5386</B></I></FONT> </FONT></BLOCKQUOTE></BODY></HTML>
------=_NextPart_000_001E_01C1E727.2B7DF3A0--
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Date: Fri, 19 Apr 2002 15:51:11 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Daniel Wong <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Daniel Wong <[log in to unmask]>
Subject: Re: Spell checks
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Hi Brian,
I'm not a British or American, but the discussion here is quite funny.=20
I would like to have a copy of doc you mentioned.=20
Would you please send me one?
Thanks!
Daniel=20
>>> [log in to unmask] 04/18/02 04:53pm >>>
Well, if we are going to have an Atlantic war, I received just today a
doc called "If you are a Brit in the USA, you might be going native if
...." This is 11 pages long, so I won't post it here, but I'll e-mail it
off list to anyone who requests it. The headings are Language; Politics;
Media; Going Home; Assimilating the Culture and Customs; Work and
Shopping and Eating Out. A few samples:
...You call shops "stores"
...You stop asking for rubbers when you want an eraser
...Trunk and hood come to mind rather than boot and bonnet
...You embrace racial politics as the national pastime
...The first section in the Sunday newspapers is the funnies
...You order a Martini in the UK and then have to ask them to add gin
...You flinch when you hear American buzzwords mispronounced on British
radio shows
...You buy a handgun
...You have bought a Websters Dictionary and the OED is gathering dust
...You have given up using irony on anyone without a college education
...You actually try and sing the Star Spangled Banner
...You now regard the UK as being part of Europe
...You get annoyed when a store closes before 9 pm
...You ask for Diet 7UP
...You don't wait for the sun to shine to eat ice cream
...You buy HUGE bottles of gin
Brian
Alan Groves wrote:
>
> Hi technetters,
> I am much more of a 'reader' than contributor to the forum, and am often
> amazed at, or embarrassed by, the knowledge that is transferred to or =
shared
> within the forum. I could quite possibly be within Moonman's description =
of
> young designer/artist;- but I am confident!
> It is only during my 'free' time that I allow myself the luxury of fully
> reading the postings, much of which remind me of why I hated chemistry =
in
> school, but many more, especially Sir Moon's, remind me of how I
> (unfortunately) fell in to the PCB/PWB business.
> However, although I would wish to ask many questions (and I have =
fantasised
> about real show stoppers) :
>
> Why don't Y'all use spell checkers?
>
> Alan Groves,
> Senior PCB Designer CID
> Spectel Head Office, 21 Stillorgan Ind. Park, Stillorgan,
> Co. Dublin. Ireland.
> Phone: 353 907 62803
> Fax: 353 1 2953740
> Email: [log in to unmask]
> Internet: www.spectel.com=20
>
> -------------------------------------------------------------------------=
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s=20
> Please visit IPC web site http://www.ipc.org/html/forum.htm for =
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> information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700 =
ext.5315
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=20
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Date: Fri, 19 Apr 2002 10:14:18 +0100
Reply-To: Dougal Stewart <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Dougal Stewart <[log in to unmask]>
Subject: Re: OSP Re: [TN] Immersion Silver
X-To: Eric Dawson <[log in to unmask]>
MIME-Version: 1.0
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Sorry Eric, I'm afraid that I can't answer your specific questions, as I am
not very experienced on the assembly side of the operation (last did
assembly in 1986 when it was still all through hole). What I do know is that
the modern OSPs are capable of withstanding up to 6 heat cycles, ie you can
glue cure, wave solder, paste reflow and handsolder without losing
solderability. I don't know what the cleaning process in between will do -
you would have to ask the OSP supplier like Cookson for compatibility -
Entec 106A is a Cookson product that they support from all angles - OSP
chemistry, paste, flux, cleaners etc.
I was involved with surface finishes a number of years ago, and found the
ignorance in some (assembly) companies astounding, whilst others fully
understood what they were dealing with.
One OEM company wanted to do accelerated ageing by using steam ageing - a
technique developed to artificially age reflowed tin lead, but pounced on as
the 'be all and end all' method for ALL surface finishes. Not surprisingly,
it failed miserably and the company dismissed OSP as an alternative. After
much persuasion they tried again, and 8 weeks after supplying product to
them, they told me that OSP had failed due to its inability to solder after
the first side. What they didn't tell me, at first, was that they tried to
solder side 2 four weeks after side 1, because this simulated what happened
in their production. Sad to say they have now closed that factory, losing
over 1000 jobs, and all their work is now manufactured by CEMs somewhere in
the far east. I think the inability to understand the basics of JIT
contributed to this greatly.
On the positive side, I worked closely with a (very) major telecomms
company, who saw the benefits of OSP and worked on the basis of never put a
board into assembly unless it can be SHIPPED within 24 hours. They are still
a very successful Telecomm company despite the worldwide downturn.
I have read all the other mails responding to my plea, and I think that the
general message is that surface finish should be related to need and data,
not fashion and opinion.
I would also like to answer Dave Hillman's point
-> 'Field repair - OSPs don't provide the long term solderability on pwa's
which have been in the field for a number of years which sometimes are
subjected to upgrades/changes. It is typically an uphill struggle to have
good solderability for HASL for servicing an assembly which has been in the
field for 5-10 years anyway and OSPs just give up the ghost way to early in
comparison to metallic surface finishes.'
I don't understand this issue as all the solder joints on an assembly were
made at the time the board was first soldered, any surface finish on the raw
card has been incorporated into the solder joint or disappeared through
volatisation at the point of soldering. Surely any rework soldering will be
on a solder joint, not on an ancient surface finish? However, I am glad to
hear that Rockwell use OSP as one of their finishes, on the basis of the
right finish for the right reason.
Rich Fudalewski (and Bob Furrow) stated: 'The other area where OSP can fail
is with via in pad (VIP) product. If there is any residue remaining in the
holes it will cause a degradation of the OSP coating. determine to not be
the OSP process at fault, but rather things like unseen soldermask residues
or incomplete removal of the tin etch resist. Doug, this seems to be a
problem with your board manufactures control of the process.'
I couldn't agree more with this, and have seen even worse issues with
immersion tin, where the thiourea emerges from the VIP during the first side
reflow. I have seen issues with immersion silver where the undercut of the
soldermask traps residues that corrode the finish, and problems with ENIG
where nickel foot has almost shorted between pads. I return to my original
point - only OSP is reworkable in these situations. All of the other
finishes will end up with scrapping the raw card rather than rework, and
even though companies go bust if they cannot control their processes, scrap
is always paid for by us the end customers somewhere down the line (even if
its to pay higher national insurance or tax to cover the unemployment
benefit of those who lost their jobs).
I hope not to have preached too much, and that Rich F has his faith restored
that Fab people do respond ! I am glad to have rekindled some interest
anyway!
Dougal Stewart
email: [log in to unmask]
phone: +44 1896 822204
mob: +44 7984 629667
----- Original Message -----
From: "Eric Dawson" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Thursday, April 18, 2002 1:40 PM
Subject: Re: [TN] Immersion Silver
> Hi Dougal,
> OSP sounds attractive but can I seek your views on a couple of points?
> We double side reflow and clean between operations to avoid baking the
flux
> on. These are complex boards and can take several days to progress through
> the line. Will the OSP stay fresh for the second side reflow or would we
> have to treat the surface? Will cleaning take it off? (Prozone).
> Regards
> Eric Dawson
>
>
> > -----Original Message-----
> > From: Dougal Stewart [SMTP:[log in to unmask]]
> > Sent: Thursday, April 18, 2002 10:57 AM
> > To: [log in to unmask]
> > Subject: Re: [TN] Immersion Silver
> >
> > I would like to know why people don't use OSP - from a board shop's
> > viewpoint, it is the best finish to put on a board - why ? because it is
> > very simple chemistry, puts no thermal shock on the product, is applied
on
> > a
> > SHORT conveyor line, and can be easily reworked unlike ANY of the other
> > finishes. The assembly guys don't like it if they start assembling a
> > product
> > and then stop because they don't have the parts to finish the job, but
> > anyone that puts a board into assembly without the ability to finish it
> > within 6 hours obviously knows nothing about world class manufacturing
> > practise. As for shelf life, if your stock is even 2 years old, send the
> > boards back to the board shop and for a small fee they just put them
back
> > down the line again and you have a finish that is good as new, without
> > having undergone a vicious chemical attack to remove the finish.
> > Just my thoughts !
> > Dougal Stewart
> >
> > email: [log in to unmask]
> > phone: +44 1896 822204
> > mob: +44 7984 629667
> > ----- Original Message -----
> > From: "Jack C. Olson" <[log in to unmask]>
> > To: <[log in to unmask]>
> > Sent: Wednesday, April 17, 2002 4:22 PM
> > Subject: Re: [TN] Immersion Silver
> >
> >
> > > Hmmm,
> > >
> > > Well, at some point in EVERY new technology it was used by less
> > > than 3% of the world, eh? Guess I'm just a trailblazer....
> > >
> > > naw, just kiddin ya.
> > > I subscribed to a magazine called Circuitree, and the last issue
> > > came bundled with another publication called "The Board Authority"
> > > which has some very well written (and well researched!) articles
> > > on alternate finishes. I can't see any downside to using silver
> > > in our applications, and I've looked all through the archives for
> > > Technet, DesignerCouncil and PCDlist forums, still no show-stoppers,
> > > so we tried it for the first time on our last design. Yes, HASL and
> > > NiGold do work fine, but maybe we can get the same functionality
> > > for cheaper, and do our fab vendor a favor in the process, since
> > > they seem to prefer it (less steps? more reliable? not sure) maybe
> > > the fab guys can answer that one....
> > >
> > > Jack
> > >
> > >
> > >
> > >
> > >
> > > "WEEKES, MICHAEL HS-SNS" <[log in to unmask]>
> > > 17Apr2002 09:16 AM
> > >
> > >
> > > To: "'TechNet E-Mail Forum.'" <[log in to unmask]>
> > > "'Jack C. Olson'" <[log in to unmask]>
> > > cc:
> > >
> > > Subject: RE: [TN] Immersion Silver
> > > Retain Until: 05/17/2002 Retention Category: G90 - Information and
> > Reports
> > > Caterpillar Confidential: Green
> > >
> > >
> > > There must be some reason why less than 3% of the world has moved
toward
> > > immersion silver. Why doesn't HASL or NiGold work for your
application?
> > >
> > > Mike
> > >
> > > -----Original Message-----
> > > From: Jack C. Olson [mailto:[log in to unmask]]
> > > Sent: Wednesday, April 17, 2002 7:39 AM
> > > To: [log in to unmask]
> > > Subject: Re: [TN] Immersion Silver
> > >
> > >
> > > The PCD magazine list went down before I could get an
> > > answer to this question, does anyone have experience
> > > with silver and contact switches?
> > >
> > > ==============================================
> > >
> > > Most sources say a silver surface will not be solderable
> > > after a month or so unprotected. (Even in a baggie it will
> > > be okay a year later?)
> > > Anyway, you say it is good for switches, which would solve
> > > some of our hard gold plating problems.
> > >
> > > But I would think the "unsolderability" of the aged silver
> > > surface (unprotected in the unit and tarnished?) would
> > > affect the reliability of the switches, wouldn't it?
> > >
> > > Jack
> > >
> > >
> > >
> > >
> > >
> > >
> > > Rob Mongey <[log in to unmask]>@freelists.org
> > > 4Apr2002 06:08 AM
> > >
> > > Please respond to [log in to unmask]
> > >
> > > Sent by: [log in to unmask]
> > >
> > >
> > >
> > > To: [log in to unmask]
> > > cc:
> > >
> > > Subject: [pcdlist] Re: Immersion Silver
> > > Retain Until: 05/04/2002 Retention Category: G90 - Information and
> > Reports
> > > Caterpillar Confidential: Green
> > >
> > >
> > >
> > > Hi all,
> > > Good to see Immersion Silver is starting to take off. We've been
> > using
> > > it
> > > in here for about two years, and it is now our prefered board finish
(We
> > > get silver finish unless we specify differently.) More common useage
> > will
> > > mean that maybe more Far Eastern shops will start supplying it.
> > >
> > > We started to use Silver because it is so adaptable to what we
need
> > > our
> > > PCB surface finish to do, namely:
> > >
> > > 1. Good solderability. (Silver excels at this, ask any vendor).
> > > 2. Flatness for fine pitch SMT. (Silver is as flat, if not flatter
than
> > > Gold)
> > > 3. Mechanical strength for carbon pill switch contacts / Elastomer
> > > contacts. ( Flash Gold is weak, and hard Gold gives SMT solderability
> > > problems)
> > > 4. Stability for compression power contacts. (We have power contacts
on
> > our
> > > PCBs that mate to battery contacts via a spring compression. We found
> > that
> > > the nickel under gold can cause problems with electrochemical
migration
> > > toward our battery contact.)
> > >
> > > Immersion silver is the most suitable choice that can do all four. I'd
> > use
> > > gold as an alternative, but we'd have to compromise our designs
> > somewhat.
> > >
> > > We specify our Silver finish as 0.1 Microns Min to 0.2 Microns Max,
over
> > > bare copper. Anyone else do it differently? Or do we trust our board
> > shops?
> > > :)
> > >
> > > Regards,
> > > Rob Mongey.
> > > CAD
Technician.
> > >
> > > Robert Mongey <[log in to unmask]> Tel : +353 (0)91 774300
> > > Bio Medical Research Direct : +353 (0)91 774338
> > > BMR House, Fax : +353 (0)91 774302
> > > Parkmore Business Park West, Mobile : +353 (0)87 2485262
> > > Galway
> > > Rep of Ireland.
> > >
> > >
>
> --------------------------------------------------------------------------
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> > > ext.5315
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> > >
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Date: Fri, 19 Apr 2002 06:49:36 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Immersion Silver
X-To: [log in to unmask]
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Thanks Rick,
Earl
----- Original Message -----=20
From: Rick Fudalewski=20
To: [log in to unmask]
Sent: Thursday, April 18, 2002 8:04 PM
Subject: Re: [TN] Immersion Silver
Touche Earl!!
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<DIV><FONT face=3DArial size=3D2>Thanks Rick,</FONT></DIV>
<DIV><FONT face=3DArial size=3D2></FONT> </DIV>
<DIV><FONT face=3DArial size=3D2>Earl</FONT></DIV>
<BLOCKQUOTE=20
style=3D"PADDING-RIGHT: 0px; PADDING-LEFT: 5px; MARGIN-LEFT: 5px; =
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<DIV style=3D"FONT: 10pt arial">----- Original Message ----- </DIV>
<DIV=20
style=3D"BACKGROUND: #e4e4e4; FONT: 10pt arial; font-color: =
black"><B>From:</B>=20
<A [log in to unmask] href=3D"mailto:[log in to unmask]">Rick=20
Fudalewski</A> </DIV>
<DIV style=3D"FONT: 10pt arial"><B>To:</B> <A [log in to unmask]
href=3D"mailto:[log in to unmask]">[log in to unmask]</A> </DIV>
<DIV style=3D"FONT: 10pt arial"><B>Sent:</B> Thursday, April 18, 2002 =
8:04=20
PM</DIV>
<DIV style=3D"FONT: 10pt arial"><B>Subject:</B> Re: [TN] Immersion =
Silver</DIV>
<DIV><BR></DIV><FONT face=3Darial,helvetica><FONT size=3D2>Touche =
Earl!!</FONT>=20
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Date: Fri, 19 Apr 2002 06:06:02 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: OSP
X-To: [log in to unmask]
George,
Thank you very much for shedding some light on an important, to us all,
subject. Sure glad, for us all, you stick around though you're obviously
thought of as much more than a board person.
As for my experiences, and some of my friends in the business, I used to get
mostly "up front" consulting jobs. Now, I get mostly "fix it" type work. I'm
not complaining but, as you said, there seems a new way of designing,
fabricating, and assembling product.
The two examples, of my supplier base that's been with me for years, are
good examples of concurrent engineering staffs. Sanmina Hadco, in its
Haverhill tech center, still has this capability and I desparately hope it
continues but, with the closure of its assembly tech center in Austin, I
have to wonder if the pendulum is swinging back to "traditional" sales
techniques (used car type approach).
Though still providing good product, some of the other PCB technical
"giants" don't talk technical anymore. They and many assembly houses talk
the talk of sales folks mostly telling us/me what we/I want to hear. What
they don't understand is I want to hear technical content with their ability
to back it up.
As much as I love my favorite board shop, PE, I have had few in depth
technical discussions with them. As one example, I requested
photomicrographs to accompany slugs before and after thermal stress to
visually confirm their report. I was asked, when questioning why no pics
were avaialable, as very nice sales lady, apparently, asked "what is
photomicrographs?"
I recognize my client's management, as many other companies, have limited
knowledge concerning PCB's. That, in my opinion, is whay they should look
for folks having up front approaches to preventing defect, through DFM/CE,
at the design level.
As you say, we need more good young engineers having the knowledge, talent,
desire, and ability to do this ever more important job as the technical
world gets more complex. I sure look back on a different world, but don't we
all. Was it any better, I think so when it came to PCB's.
Earl
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Date: Fri, 19 Apr 2002 06:10:14 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: OSP Re: [TN] Immersion Silver
X-To: [log in to unmask]
Geez Doug, for someone not having had much assembly experience in a while,
you sure know your way around what it takes to make surface finishes
solderable. I find nothing wrong with anything you say.
I'm taking it to my bank,
Earl Moon
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Date: Fri, 19 Apr 2002 07:52:10 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Randy Bock Sr." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Randy Bock Sr." <[log in to unmask]>
Subject: Re: OSP
X-To: "Wenger, George M." <[log in to unmask]>
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This is the best reply yet.. THANK YOU
----- Original Message -----
From: Wenger, George M. <[log in to unmask]>
To: <[log in to unmask]>
Sent: Thursday, April 18, 2002 9:53 PM
Subject: Re: [TN] OSP
> Earl,
>
> I'd like to expand and comment on you question "Where have all the board
people gone, long time passing". Unfortunately the board people whet by the
wayside just like many other technical people. Companies have down sized
their technical efforts and increased their supply chain efforts with the
rational that we don't have to pay for technical information because our
suppliers will give us what we need for free. Well the one thing most
people learn during their life time is you get what you pay for. In the
past 18 months or more the attendance at technical conferences and seminars
has decreased, the technical content in email forms such as TechNet have
decreased and when you ask a supplier for technical date you get sales
information.
> I'm not sure how or if there is going to be a reversal but I sure hope
that young engineers entering the work place keep letting their management
know that engineering date not sales information is needed to make informed
decisions and effective risk assesments.
>
> -----Original Message-----
> From: Earl Moon [mailto:[log in to unmask]]
> Sent: Thursday, April 18, 2002 3:15 PM
> To: [log in to unmask]
> Subject: Re: [TN] OSP
>
>
> Outstanding Rick,
>
> I agree and side with Kerry as well but for his "boring" comment. I know
he
> meant well as we all try CPI.
>
> Other folks, me included, have commented on the lack of board type people
> participating enough on this forum. I certainly have done my best to get
> them back but probably have bored them and others to leaving because of my
> excessive time on the forum.
>
> Phil Hinton said this forum is becoming an "good old boys club" or some
such
> thing. I agreed then as now but we have the freedom to participate or not.
>
> I just want the facts man, just the facts. I have way more questions than
> answers but one thing is sure - we need more fabricators on this thing.
>
> I just finished a concurrent engineering conference with my assembler, my
> company, and my fab supplier. Excellent results concerning solder wetting,
> or not.
>
> Turns out our great fab supplier (Proto Engineering)provided highly
> solderable ENIG boards that didn't look that great after assembly in some
> areas. Also turns out, our fantastic assembler (MPI) uses the latest DEK
> stencil printers with ProFlo heads. Because of this, and the large pads
> required for a few parts, MPI requested steicils with "window pane"
> apertures for these large pads. Hence, non wetting on some pad areas. New
> one to me but greatly appreciated for us all.
>
> Where have all the board people gone, long time passing. I'll get of the
> fourm if it's me but we need fab folks no matter.
>
> MoonMan
>
> --------------------------------------------------------------------------
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Date: Fri, 19 Apr 2002 07:53:21 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Randy Bock Sr." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Randy Bock Sr." <[log in to unmask]>
Subject: Re: IPC SMT FOOTPRINT DESIGN GUIDLINES VS SUPPLIERS
X-To: [log in to unmask]
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Thank you !!!
----- Original Message -----=20
From: Gary Ferrari=20
To: [log in to unmask]
Sent: Thursday, April 18, 2002 7:15 PM
Subject: Re: [TN] IPC SMT FOOTPRINT DESIGN GUIDLINES VS SUPPLIERS
I would like to address a few of the comments that have been made.
First, when the same component parameters and design fillet goals are =
input into the current web based calculator they should yield the same =
land pattern as listed in the RLP section. We have on occasion found an =
error in the component data listed in the hard copy or web calculator =
and have made appropriate corrects. Any discrepancies found should be =
reported to John Perry at IPC.
Second is that the calculator is based on the same principles as found =
in the hard copy of the standard. It is true that land patterns for the =
newer components may not have been tested as the earlier ones were. But =
in many cases the basic principles remain untouched. However, the land =
pattern committee does approve each new pattern based on an assessment =
culled from their own experiences with that component as well as input =
from other industry sources.
The last issue is that the 782 land pattern committee is currently =
working on a complete revision to our land pattern document. I would =
point out that one should not perceive the revised document as an =
indication that there is something wrong with the current land patterns. =
This effort is addressing new component families as well as a new =
concept going forward.
The new standard will be identified as IPC-7351 and will be of a =
format that provides slash sheets for the various component families. =
This will enable new component additions to get released in a much more =
timely fashion. The standard will contain four columns of data for each =
component. The first column will be the existing 782 pattern data. The =
next three will represent minimum, median and maximum applications. All =
component types not currently in 782 will be released to this new =
format. AS we move forward, we will NOT be adding data under the 782 =
columns for components not currently listed in the current 782.
As a general point of information, you will find that the current 782 =
land patterns will fall someplace between the minimum and median =
columns. What is important to recognize is that compromises were taken =
to reach the smaller sizes and it will be quite apparent where they were =
made. It would be wise for the designer to obtain approval from those =
affected by the compromises before using the smaller sizes.
The first release will contain the current 782 listed components with =
additional component slash sheets released in rapid succession =
thereafter.
Regards,
Gary Ferrari
Executive Director
IPC Designers Council
(860) 350-9300
Fax (413) 771-5386=20
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<BODY bgColor=3D#ffffff>
<DIV><FONT size=3D2>Thank you !!!</FONT></DIV>
<BLOCKQUOTE=20
style=3D"BORDER-LEFT: #000000 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: =
0px; PADDING-LEFT: 5px; PADDING-RIGHT: 0px">
<DIV style=3D"FONT: 10pt arial">----- Original Message ----- </DIV>
<DIV=20
style=3D"BACKGROUND: #e4e4e4; FONT: 10pt arial; font-color: =
black"><B>From:</B>=20
<A href=3D"mailto:[log in to unmask]" [log in to unmask]>Gary =
Ferrari</A> </DIV>
<DIV style=3D"FONT: 10pt arial"><B>To:</B> <A =
href=3D"mailto:[log in to unmask]"=20
[log in to unmask]>[log in to unmask]</A> </DIV>
<DIV style=3D"FONT: 10pt arial"><B>Sent:</B> Thursday, April 18, 2002 =
7:15=20
PM</DIV>
<DIV style=3D"FONT: 10pt arial"><B>Subject:</B> Re: [TN] IPC SMT =
FOOTPRINT=20
DESIGN GUIDLINES VS SUPPLIERS</DIV>
<DIV><BR></DIV><FONT face=3Darial,helvetica><FONT color=3D#8000ff=20
face=3D"Comic Sans MS" lang=3D0 size=3D2 FAMILY=3D"SCRIPT"><B><I>I =
would like to=20
address a few of the comments that have been made.<BR><BR>First, when =
the same=20
component parameters and design fillet goals are input into the =
current web=20
based calculator they should yield the same land pattern as listed in =
the RLP=20
section. We have on occasion found an error in the component data =
listed in=20
the hard copy or web calculator and have made appropriate corrects. =
Any=20
discrepancies found should be reported to John Perry at =
IPC.<BR><BR>Second is=20
that the calculator is based on the same principles as found in the =
hard copy=20
of the standard. It is true that land patterns for the newer =
components may=20
not have been tested as the earlier ones were. But in many cases the =
basic=20
principles remain untouched. However, the land pattern committee does =
approve=20
each new pattern based on an assessment culled from their own =
experiences with=20
that component as well as input from other industry =
sources.<BR><BR>The last=20
issue is that the 782 land pattern committee is currently working on a =
complete revision to our land pattern document. I would point out that =
one=20
should not perceive the revised document as an indication that there =
is=20
something wrong with the current land patterns. This effort is =
addressing new=20
component families as well as a new concept going forward.<BR><BR>The =
new=20
standard will be identified as IPC-7351 and will be of a format that =
provides=20
slash sheets for the various component families. This will enable new=20
component additions to get released in a much more timely fashion. The =
standard will contain four columns of data for each component. The =
first=20
column will be the existing 782 pattern data. The next three will =
represent=20
minimum, median and maximum applications. All component types not =
currently in=20
782 will be released to this new format. AS we move forward, we will =
NOT be=20
adding data under the 782 columns for components not currently listed =
in the=20
current 782.<BR><BR>As a general point of information, you will find =
that the=20
current 782 land patterns will fall someplace between the minimum and =
median=20
columns. What is important to recognize is that compromises were taken =
to=20
reach the smaller sizes and it will be quite apparent where they were =
made. It=20
would be wise for the designer to obtain approval from those affected =
by the=20
compromises before using the smaller sizes.<BR><BR>The first release =
will=20
contain the current 782 listed components with additional component =
slash=20
sheets released in rapid succession thereafter.<BR></FONT><FONT =
color=3D#000000=20
face=3D"Comic Sans MS" lang=3D0 size=3D2 style=3D"BACKGROUND-COLOR: =
#ffffff"=20
FAMILY=3D"SCRIPT"></B></I><BR></FONT><FONT color=3D#8000ff =
face=3D"Comic Sans MS"=20
lang=3D0 size=3D2 style=3D"BACKGROUND-COLOR: #ffffff"=20
FAMILY=3D"SCRIPT"><B><I>Regards,<BR><BR>Gary Ferrari<BR>Executive=20
Director<BR>IPC Designers Council<BR>(860) 350-9300<BR>Fax (413)=20
771-5386</B></I></FONT> </FONT></BLOCKQUOTE></BODY></HTML>
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Date: Fri, 19 Apr 2002 08:17:23 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Charlie McMahon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Charlie McMahon <[log in to unmask]>
Subject: Re: OSP
X-To: Earl Moon <[log in to unmask]>
MIME-Version: 1.0
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Earl/George:
As a board/assembly supplier for many years in the New England area (as
well as Texas) I have worked with a myriad of fabricators
each expressing they were leaders in one product or another. The reasons
for one surviving versus another was rarely technical but
almost always related to price. It is from this vantage that all
discussions would initiate.
The point about fabricators participating in the forum (which I believe
is the best available/thanks to expert contributions of the participants)
prompted a response. I personally believe in the Deming principals of
Co-operative Engineering when servicing clients. The people I serve
do not. I believe in DFM/CE functions coupled with the customers product
marketing team when determining optimum designs to meet competitive
pressures
of the marketplace. The companies I have called on do not. I could go on
but you get the point. The reason....money, time, hubris (who is
smarter), I can speculate as well as any.
As one who believe as you do Earl in the total design approach to
successful board manufacture and assembly, we are in the minority. Yet,
I so firmly believe
in the method because of its obvious monetary and quality benefits (not
necessarily in that order) I will continue to advocate for it at every
opportunity.
I recall when I was providing fabrication services to a major user in
New England who's specifications were so loose that the fabricators of
which I was one
would be measured on a moving scale based on how the
QA/Assembly/Inspection team felt that day. Suspect rejections were
rampant, design flaws constant, resulting in tremendous effort by all
parties to try and guess; what did this company want?. Up to this point,
ANY questioning of the companies expertise at any level
was met with a threat of termination as a vendor. It was so egregious
that I suggested to the company that we have a PCB Summit meeting to
agree on a holistic specification for all with the goal of providing
consistent quality product.
The meeting took place with all vendors present (approx. 6-8 at the
time) and in comes the VP of Mfg'ing who states the following: "Before
we get started, we are reducing the vendor base after this meeting.
Thank you for coming and have a good meeting".
Needless to say nothing was changed. And that brings me to today. Please
continue Earl in your work towards the co-operative engineering method
as I will.
For US electronics manufacturing to survive in the next decade, we must
convince our associates/friends that this is the appropriate path.
I apologize for the long post....just felt you should hear from the
fabrication side.
By the way....I know what a photomicrograph is and have been providing
them since 1982.
Keep up the quality inputs Earl and George
Charlie McMahon.
Earl Moon wrote:
>George,
>
>Thank you very much for shedding some light on an important, to us all,
>subject. Sure glad, for us all, you stick around though you're obviously
>thought of as much more than a board person.
>
>As for my experiences, and some of my friends in the business, I used to get
>mostly "up front" consulting jobs. Now, I get mostly "fix it" type work. I'm
>not complaining but, as you said, there seems a new way of designing,
>fabricating, and assembling product.
>
>The two examples, of my supplier base that's been with me for years, are
>good examples of concurrent engineering staffs. Sanmina Hadco, in its
>Haverhill tech center, still has this capability and I desparately hope it
>continues but, with the closure of its assembly tech center in Austin, I
>have to wonder if the pendulum is swinging back to "traditional" sales
>techniques (used car type approach).
>
>Though still providing good product, some of the other PCB technical
>"giants" don't talk technical anymore. They and many assembly houses talk
>the talk of sales folks mostly telling us/me what we/I want to hear. What
>they don't understand is I want to hear technical content with their ability
>to back it up.
>
>As much as I love my favorite board shop, PE, I have had few in depth
>technical discussions with them. As one example, I requested
>photomicrographs to accompany slugs before and after thermal stress to
>visually confirm their report. I was asked, when questioning why no pics
>were avaialable, as very nice sales lady, apparently, asked "what is
>photomicrographs?"
>
>I recognize my client's management, as many other companies, have limited
>knowledge concerning PCB's. That, in my opinion, is whay they should look
>for folks having up front approaches to preventing defect, through DFM/CE,
>at the design level.
>
>As you say, we need more good young engineers having the knowledge, talent,
>desire, and ability to do this ever more important job as the technical
>world gets more complex. I sure look back on a different world, but don't we
>all. Was it any better, I think so when it came to PCB's.
>
>Earl
>
>---------------------------------------------------------------------------------
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>the BODY (NOT the subject field): SIGNOFF Technet
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>information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700 ext.5315
>---------------------------------------------------------------------------------
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<head>
</head>
<body>
Earl/George:<br>
<br>
As a board/assembly supplier for many years in the New England area (as well
as Texas) I have worked with a myriad of fabricators <br>
each expressing they were leaders in one product or another. The reasons
for one surviving versus another was rarely technical but <br>
almost always related to price. It is from this vantage that all discussions
would initiate.<br>
<br>
The point about fabricators participating in the forum (which I believe is
the best available/thanks to expert contributions of the participants)<br>
prompted a response. I personally believe in the Deming principals of Co-operative
Engineering when servicing clients. <b>The people I serve <br>
do not</b>. I believe in DFM/CE functions coupled with the customers product
marketing team when determining optimum designs to meet competitive pressures<br>
of the marketplace. <b>The companies I have called on do not</b>. I could
go on but you get the point. The reason....money, time, hubris (who is smarter),
I can speculate as well as any.<br>
<br>
As one who believe as you do Earl in the total design approach to successful
board manufacture and assembly, we are in the minority. Yet, I so firmly
believe<br>
in the method because of its obvious monetary and quality benefits (not necessarily
in that order) I will continue to advocate for it at every opportunity.<br>
<br>
I recall when I was providing fabrication services to a major user in New
England who's specifications were so loose that the fabricators of which
I was one<br>
would be measured on a moving scale based on how the QA/Assembly/Inspection
team felt that day. Suspect rejections were rampant, design flaws constant,
resulting in tremendous effort by all parties to try and guess; what did
this company want?. Up to this point, ANY questioning of the companies expertise
at any level<br>
was met with a threat of termination as a vendor. It was so egregious that
I suggested to the company that we have a PCB Summit meeting to agree on
a holistic specification for all with the goal of providing consistent quality
product. <br>
<br>
The meeting took place with all vendors present (approx. 6-8 at the time)
and in comes the VP of Mfg'ing who states the following: "Before we get started,
we are reducing the vendor base after this meeting. Thank you for coming
and have a good meeting". <br>
<br>
Needless to say nothing was changed. And that brings me to today. Please
continue Earl in your work towards the co-operative engineering method as
I will. <br>
For US electronics manufacturing to survive in the next decade, we must convince
our associates/friends that this is the appropriate path.<br>
<br>
I apologize for the long post....just felt you should hear from the fabrication
side. <br>
By the way....I know what a photomicrograph is and have been providing them
since 1982.<br>
<br>
Keep up the quality inputs Earl and George<br>
<br>
<br>
Charlie McMahon. <br>
<br>
<br>
Earl Moon wrote:<br>
<blockquote type="cite" cite="mid:[log in to unmask]">
<pre wrap="">George,<br><br>Thank you very much for shedding some light on an important, to us all,<br>subject. Sure glad, for us all, you stick around though you're obviously<br>thought of as much more than a board person.<br><br>As for my experiences, and some of my friends in the business, I used to get<br>mostly "up front" consulting jobs. Now, I get mostly "fix it" type work. I'm<br>not complaining but, as you said, there seems a new way of designing,<br>fabricating, and assembling product.<br><br>The two examples, of my supplier base that's been with me for years, are<br>good examples of concurrent engineering staffs. Sanmina Hadco, in its<br>Haverhill tech center, still has this capability and I desparately hope it<br>continues but, with the closure of its assembly tech center in Austin, I<br>have to wonder if the pendulum is swinging back to "traditional" sales<br>techniques (used car type approach).<br><br>Though still providing good product, some of the other PCB
technical<br>"giants" don't talk technical anymore. They and many assembly houses talk<br>the talk of sales folks mostly telling us/me what we/I want to hear. What<br>they don't understand is I want to hear technical content with their ability<br>to back it up.<br><br>As much as I love my favorite board shop, PE, I have had few in depth<br>technical discussions with them. As one example, I requested<br>photomicrographs to accompany slugs before and after thermal stress to<br>visually confirm their report. I was asked, when questioning why no pics<br>were avaialable, as very nice sales lady, apparently, asked "what is<br>photomicrographs?"<br><br>I recognize my client's management, as many other companies, have limited<br>knowledge concerning PCB's. That, in my opinion, is whay they should look<br>for folks having up front approaches to preventing defect, through DFM/CE,<br>at the design level.<br><br>As you say, we need more good young engineers having the knowledge, talent,
<br>desire, and ability to do this ever more important job as the technical<br>world gets more complex. I sure look back on a different world, but don't we<br>all. Was it any better, I think so when it came to PCB's.<br><br>Earl<br><br>---------------------------------------------------------------------------------<br>Technet Mail List provided as a free service by IPC using LISTSERV 1.8d<br>To unsubscribe, send a message to <a class="moz-txt-link-abbreviated" href="mailto:[log in to unmask]">[log in to unmask]</a> with following text in<br>the BODY (NOT the subject field): SIGNOFF Technet<br>To temporarily halt delivery of Technet send e-mail to <a class="moz-txt-link-abbreviated" href="mailto:[log in to unmask]:">[log in to unmask]:</a> SET Technet NOMAIL<br>To receive ONE mailing per day of all the posts: send e-mail to <a class="moz-txt-link-abbreviated" href="mailto:[log in to unmask]:">[log in to unmask]:</a> SET Technet Digest<br>Search the archives of previous posts at: <a class
="moz-txt-link-freetext" href="http://listserv.ipc.org/archives">http://listserv.ipc.org/archives</a><br>Please visit IPC web site <a class="moz-txt-link-freetext" href="http://www.ipc.org/html/forum.htm">http://www.ipc.org/html/forum.htm</a> for additional<br>information, or contact Keach Sasamori at <a class="moz-txt-link-abbreviated" href="mailto:[log in to unmask]">[log in to unmask]</a> or 847-509-9700 ext.5315<br>---------------------------------------------------------------------------------<br><br></pre>
</blockquote>
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=========================================================================
Date: Fri, 19 Apr 2002 08:55:31 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Safavi-Bayat Shahed <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Safavi-Bayat Shahed <[log in to unmask]>
Subject: Re: Via in Pad: Filling of vias using silver epoxy!?!?
X-To: Ken Patel <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Ken,
Here are some references that may help you,
http://www.protoengineering.com/pdf/viaplug.pdf
http://www.circuitree.com/CDA/ArticleInformation/features/BNP__Features__Ite
m/0,2133,72451,00.html
http://www.ammagazine.com/CDA/ArticleInformation/features/BNP__Features__Ite
m/0,2606,5918,00.html
http://www.asat.com/AdditionalInfo/tg1004.pdf
http://extra.ivf.se/ngl/F-MCM/ChapterF2.htm
http://www.ece.gatech.edu/research/labs/gsigroup/publications/chirag_imaps.p
df
Regards,
Shahed
-----Original Message-----
From: Ken Patel [mailto:[log in to unmask]]
Sent: Thursday, April 18, 2002 6:21 PM
To: [log in to unmask]
Subject: [TN] Via in Pad: Filling of vias using silver epoxy!?!?
Guys,
I am dealing with high frequency board which is 25 mil thick and made of
Rogers material. The other side is totally exposed copper. How should I
handle as there via in pads (VIP)? I have heard about filling the vias
using silver epoxy and then plating it over. Can someone shed some more
light?
re,
ken patel
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Date: Fri, 19 Apr 2002 08:01:02 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: OSP
X-To: [log in to unmask]
Charlie,
Thanks for that insight. It sure brings out the near rage in me and, at the
same time, excites to make me want to do better. Actually, I just wish
everyone wanted to do better like the folks on this forum always asking
questions and providing answers to them.
I think sometimes I should go back to school and become a much better
engineer as well as businessman.
You cited Demming. He and Juran are my heroes along with the Georges,
Steves, Werners, Daves, Dougs, and all the rest of the folks contributing so
much to our industry. Hell, don't forget all the folks at IPC like David,
Jack, and all, and so many more folks with little ego but a strong desire to
do it right.
I know it's getting harder out here. The technology is advancing at an
exponential pace. Managers are forcing the timeline to market as investors
demand more return on investments. Engineers maybe are not getting all they
should from and out of school and, especially, we keep fixing stuff too often.
I'm not at all discouraged by all that's going on. Foolishly, maybe as Brian
has said, I believe in the DFM/CE concept and keep trying to reach some
folks. As George said, fewer people are out there attending, listening, and
learning and taking it home to do it right the first time.
Hell, It's a living but I think it used to be so much more,
Earl
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Date: Fri, 19 Apr 2002 08:11:19 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Misner, Bruce" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Misner, Bruce" <[log in to unmask]>
Subject: Re: Hole cracking of Teflon PCB after screwing
X-To: "[log in to unmask]" <[log in to unmask]>
Shirley,
That's the nature of the beast. That's why they usually are bonded to
aluminum backer plates. You could try to use large flat washers and set the
torque requirements quite low (you will need torque requirements). Loctite
or equivalent is a must to hold the screw (I am assuming you are screwing
through the board to something metal on the other side, other wise you are
in serious trouble or I don't have enough information to understand your
application and configuration).
Good Luck,
Bruce Misner
> ----------
> From: [log in to unmask][SMTP:[log in to unmask]]
> Reply To: TechNet E-Mail Forum.;[log in to unmask]
> Sent: Thursday, April 18, 2002 5:32 PM
> To: [log in to unmask]
> Subject: Re: [TN] Hole cracking of Teflon PCB after screwing
>
> that even sounds painfull, sorry couldn't resist!
>
>
>
>
>
>
>
> Shirley Xiao <[log in to unmask]> on 04/18/2002 05:00:47 AM
>
> Please respond to "TechNet E-Mail Forum." <[log in to unmask]>; Please
> respond to
> Shirley Xiao <[log in to unmask]>
>
>
>
>
>
>
>
>
> To: [log in to unmask]
>
> cc: (bcc: Warren Crow/US/I-O INC)
>
>
>
> Subject: [TN] Hole cracking of Teflon PCB after screwing
>
>
>
>
>
>
>
>
> One batch of double sided PCB using teflon materials
> have hole cracking problems after screwing by electric
> driver.The borad is easy to break if I bent it. Is it
> do to laminate quality problem?
> What kind of test shall I have?
>
> Thanks in advance!
>
> __________________________________________________
> Do You Yahoo!?
> Yahoo! Tax Center - online filing with TurboTax
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> --------------------------------------------------------------------------
> -------
>
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>
> --------------------------------------------------------------------------
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Date: Fri, 19 Apr 2002 09:08:11 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"McMullen, Kerry" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "McMullen, Kerry" <[log in to unmask]>
Subject: Re: Immersion Silver
X-To: "Wenger, George M." <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Hi George,
Thanks for the reply.
One final question I have for Technet.
Bellcore GR-78-CORE:
Section 3.2 Materials
3.2.4 regarding Silver.
Then check, Section 6.1.1 Printed Wiring Board Requirements:
6.1.1.5 Conductor Materials and finishes R6-8 Silver shall not be
used as a conductor or contact finish.
Am I to understand I cannot ship an Immersion Silver board to a customer
that requires we adhere to Bellcore standards? Is the Bellcore standard
changing?
Thanks,
Kerry
-----Original Message-----
From: Wenger, George M. [mailto:[log in to unmask]]
Sent: Thursday, April 18, 2002 9:31 PM
To: [log in to unmask]
Subject: Re: [TN] Immersion Silver
Kerry,
What you heard is partially correct. The exception I take in the statement
is that you need to make sure that your soldermask is compatible with any
finial finish that is applied to PWBs after the solder mask operation. It is
my understanding that because of the chemicals and low temperature (compared
to other finial finishes)associated with immersion silver replacement
plating the solder mask concern is no worst than other finial finishes. In
fact there are some fabricators that apply NiAu finial finishes prior to
solder mask because the sodler mask they use is affected by the electroless
nickel plating chemistry.
The finial finish needs to be selected based on design, fabrication issues,
solder joint integrity/reliability, availability, and cost. If you're doing
SMT reflow of fine pitch components and are required to use 3 to 6 mil thick
stencils you probably need to avoid HASL. If you're building 2 to 4 GHz RF
products on low low subtrates with long microstrips you probably need to
avoid the use of NiAu or at least make the nickel plating real thin (25-50
micro inches) which presents problems to fabricators. If your fabricator
has problems controlling tin-strip and solder mask processes you probably
need to avoid OSP. If you fabricator privides boards wrapped with rubber
bands or in brown paper or if you place boards on trays after reflow
assembly rather than in metal racks you proably want to stay away fro
immersion silver. If you need to do wire bonding you'll probably windup
using thick electrolytic or electroless gold or you might even get away with
ENIG. On the other hand if you're using 1mm or smaller pitch CSP or area
array packages or high I/O BGAs you probably need to know as much as
possible about "Black Pad"
Sorry for the long winded answer but my point is you need to assess the
compatibility, interactions and requirments associated with fabrication,
assembly, and use in order to decide what finial surface finish works for
your application.
-----Original Message-----
From: McMullen, Kerry [mailto:[log in to unmask]]
Sent: Thursday, April 18, 2002 3:57 PM
To: [log in to unmask]
Subject: Re: [TN] Immersion Silver
Hi Earl / Rick F.
I am still doing my research. I recently heard you have to make sure that
your soldermask is compatible with the Immersion Silver process. That is
where I am at now in my evaluation.
Rick F. made some good points. NiAu , Ag, Sn, HASL should be selected based
on the design. For example, I would rather press compliant pins into HASL
plated through holes than NiAU holes.
Cheers,
Kerry
-----Original Message-----
From: Earl Moon [mailto:[log in to unmask]]
Sent: Thursday, April 18, 2002 2:59 PM
To: [log in to unmask]; McMullen, Kerry
Subject: Re: Immersion Silver
Kerry,
You helped me greatly with your reflow profile. Help me, and us all, again
with the results of your silver findings.
Earl
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Date: Fri, 19 Apr 2002 09:47:47 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"WEEKES, MICHAEL HS-SNS" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "WEEKES, MICHAEL HS-SNS" <[log in to unmask]>
Subject: Re: OSP
X-To: "Randy Bock Sr." <[log in to unmask]>
X-cc: "Lutfy, Gary HS-SNS" <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
I'd be willing to talk to one or two older codgers with J STD 001 and Mil
Spec experience to help my company move from one to the other. We're about 7
yrs. late - please suggest names or contacts - perhaps a one month contract
agreement. (consultant-type) - humble, please, not arrogant.
-----Original Message-----
From: Randy Bock Sr. [mailto:[log in to unmask]]
Sent: Friday, April 19, 2002 6:52 AM
To: [log in to unmask]
Subject: Re: [TN] OSP
This is the best reply yet.. THANK YOU
----- Original Message -----
From: Wenger, George M. <[log in to unmask]>
To: <[log in to unmask]>
Sent: Thursday, April 18, 2002 9:53 PM
Subject: Re: [TN] OSP
> Earl,
>
> I'd like to expand and comment on you question "Where have all the board
people gone, long time passing". Unfortunately the board people whet by the
wayside just like many other technical people. Companies have down sized
their technical efforts and increased their supply chain efforts with the
rational that we don't have to pay for technical information because our
suppliers will give us what we need for free. Well the one thing most
people learn during their life time is you get what you pay for. In the
past 18 months or more the attendance at technical conferences and seminars
has decreased, the technical content in email forms such as TechNet have
decreased and when you ask a supplier for technical date you get sales
information.
> I'm not sure how or if there is going to be a reversal but I sure hope
that young engineers entering the work place keep letting their management
know that engineering date not sales information is needed to make informed
decisions and effective risk assesments.
>
> -----Original Message-----
> From: Earl Moon [mailto:[log in to unmask]]
> Sent: Thursday, April 18, 2002 3:15 PM
> To: [log in to unmask]
> Subject: Re: [TN] OSP
>
>
> Outstanding Rick,
>
> I agree and side with Kerry as well but for his "boring" comment. I know
he
> meant well as we all try CPI.
>
> Other folks, me included, have commented on the lack of board type people
> participating enough on this forum. I certainly have done my best to get
> them back but probably have bored them and others to leaving because of my
> excessive time on the forum.
>
> Phil Hinton said this forum is becoming an "good old boys club" or some
such
> thing. I agreed then as now but we have the freedom to participate or not.
>
> I just want the facts man, just the facts. I have way more questions than
> answers but one thing is sure - we need more fabricators on this thing.
>
> I just finished a concurrent engineering conference with my assembler, my
> company, and my fab supplier. Excellent results concerning solder wetting,
> or not.
>
> Turns out our great fab supplier (Proto Engineering)provided highly
> solderable ENIG boards that didn't look that great after assembly in some
> areas. Also turns out, our fantastic assembler (MPI) uses the latest DEK
> stencil printers with ProFlo heads. Because of this, and the large pads
> required for a few parts, MPI requested steicils with "window pane"
> apertures for these large pads. Hence, non wetting on some pad areas. New
> one to me but greatly appreciated for us all.
>
> Where have all the board people gone, long time passing. I'll get of the
> fourm if it's me but we need fab folks no matter.
>
> MoonMan
>
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Date: Fri, 19 Apr 2002 09:53:38 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Wenger, George M." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Wenger, George M." <[log in to unmask]>
Subject: Re: Immersion Silver
X-To: "McMullen, Kerry" <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
Kerry,
Telcordia-78-CORE Section 3.2.4 SILVER
CR3-15 [52] Silver containing materials shall not be used where there is =
a possibility of silver migration that could cause circuit =
malfunction, especially wherre these materials are separated by or =
associated with materials that can absorb moisture
Although the statement says "shall not be used" it has the qualifier of =
"where there is a possibility of silver migration". The data I've seen =
from Ford, Intel, Rockwell, MacDeermid, Alphametals, NCMS, etc. shows =
that their testing indicates immersion silver passes the Telcordia =
electromigration test. When I was with Lucent we did electromigration =
testing of immersion silver surface finish on the technologies (i.e., =
board materials, solder mask materials, assembly fluxes and processes) =
we used for telecommunication product and showed we passed the =
electromigration requirements.
As for 6.1.1.5, currently we are not using immersion silver as a =
conductor or contact finish. Actually we're using immersion silver as =
an indicator that the copper it was plated to is clean (i.e., no tin =
strip or solder mask residue) and should be solderable. I think Section =
6.1.1.5 does not stop anyone from using immersion silver as a contact =
because if you read the second sentence in Section 6.1.1.5 "This =
restriction also applies to the use of silver in conductive polymeric =
materials used in the manufacture of PWBs, unless acceptable reliability =
data is provided to the Network Operator or its designaed =
representative." The ws I read this requirment is that you can use =
immersion silver if you've done your homework and have generated the =
acceptable reliability data.=20
I don't have the latest "McDonald billboard style numbers" indicating =
the number of billions of solder interconnections made to immersion =
silver boards but if you look at the IPC National Conference On Surface =
Finishes and Soldering in the 1997 to 199 time frame and the SurFin 2000 =
proceeding I think you'll find that there have been millions of boards =
with immersion silver surface finish sold to Telcordia customers.
Regards,
George
George M. Wenger (908)-546-4531 [log in to unmask]
Distinguished Member Technical Staff
Celiant Corporation, FMA Lab, 40 Technology Drive, NJ 07059
-----Original Message-----
From: McMullen, Kerry [mailto:[log in to unmask]]
Sent: Friday, April 19, 2002 9:08 AM
To: 'TechNet E-Mail Forum.'; Wenger, George M.
Subject: RE: [TN] Immersion Silver
Hi George,
Thanks for the reply.
One final question I have for Technet.=20
Bellcore GR-78-CORE:
=20
Section 3.2 Materials
3.2.4 regarding Silver.
Then check, Section 6.1.1 Printed Wiring Board Requirements:
6.1.1.5 Conductor Materials and finishes R6-8 Silver shall not be
used as a conductor or contact finish.
Am I to understand I cannot ship an Immersion Silver board to a customer
that requires we adhere to Bellcore standards? Is the Bellcore standard
changing?=20
Thanks,
Kerry
-----Original Message-----
From: Wenger, George M. [mailto:[log in to unmask]]
Sent: Thursday, April 18, 2002 9:31 PM
To: [log in to unmask]
Subject: Re: [TN] Immersion Silver
Kerry,
What you heard is partially correct. The exception I take in the =
statement
is that you need to make sure that your soldermask is compatible with =
any
finial finish that is applied to PWBs after the solder mask operation. =
It is
my understanding that because of the chemicals and low temperature =
(compared
to other finial finishes)associated with immersion silver replacement
plating the solder mask concern is no worst than other finial finishes. =
In
fact there are some fabricators that apply NiAu finial finishes prior to
solder mask because the sodler mask they use is affected by the =
electroless
nickel plating chemistry.
The finial finish needs to be selected based on design, fabrication =
issues,
solder joint integrity/reliability, availability, and cost. If you're =
doing
SMT reflow of fine pitch components and are required to use 3 to 6 mil =
thick
stencils you probably need to avoid HASL. If you're building 2 to 4 GHz =
RF
products on low low subtrates with long microstrips you probably need to
avoid the use of NiAu or at least make the nickel plating real thin =
(25-50
micro inches) which presents problems to fabricators. If your =
fabricator
has problems controlling tin-strip and solder mask processes you =
probably
need to avoid OSP. If you fabricator privides boards wrapped with =
rubber
bands or in brown paper or if you place boards on trays after reflow
assembly rather than in metal racks you proably want to stay away fro
immersion silver. If you need to do wire bonding you'll probably windup
using thick electrolytic or electroless gold or you might even get away =
with
ENIG. On the other hand if you're using 1mm or smaller pitch CSP or =
area
array packages or high I/O BGAs you probably need to know as much as
possible about "Black Pad"
Sorry for the long winded answer but my point is you need to assess the
compatibility, interactions and requirments associated with fabrication,
assembly, and use in order to decide what finial surface finish works =
for
your application.
-----Original Message-----
From: McMullen, Kerry [mailto:[log in to unmask]]
Sent: Thursday, April 18, 2002 3:57 PM
To: [log in to unmask]
Subject: Re: [TN] Immersion Silver
Hi Earl / Rick F.
I am still doing my research. I recently heard you have to make sure =
that
your soldermask is compatible with the Immersion Silver process. That =
is
where I am at now in my evaluation.
Rick F. made some good points. NiAu , Ag, Sn, HASL should be selected =
based
on the design. For example, I would rather press compliant pins into =
HASL
plated through holes than NiAU holes.
Cheers,
Kerry
-----Original Message-----
From: Earl Moon [mailto:[log in to unmask]]
Sent: Thursday, April 18, 2002 2:59 PM
To: [log in to unmask]; McMullen, Kerry
Subject: Re: Immersion Silver
Kerry,
You helped me greatly with your reflow profile. Help me, and us all, =
again
with the results of your silver findings.
Earl
-------------------------------------------------------------------------=
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in
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SET
Technet NOMAIL
To receive ONE mailing per day of all the posts: send e-mail to
[log in to unmask]: SET Technet Digest
Search the archives of previous posts at: =
http://listserv.ipc.org/archives
Please visit IPC web site http://www.ipc.org/html/forum.htm for =
additional
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Technet NOMAIL
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http://listserv.ipc.org/archives
Please visit IPC web site http://www.ipc.org/html/forum.htm for =
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Date: Fri, 19 Apr 2002 09:02:35 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
[log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Dave Hillman <[log in to unmask]>
Subject: Re: OSP Re: [TN] Immersion Silver
X-To: [log in to unmask]
MIME-Version: 1.0
Content-type: text/plain; charset="us-ascii"
Hi Doug! Wonderful response and good information! Let add a couple of
things:
"What I do know is that the modern OSPs are capable of withstanding up to 6
heat cycles, ie you can
glue cure, wave solder, paste reflow and handsolder without losing
solderability. I don't know what the cleaning process in between will do"
*** Some of the OSPs we have investigated did survive 6 thermal excursions
but that type of performance was found on a inconsistent basis. Having the
OSP survive 4 thermal excursions has become a very routine, consistent way
of life for soldering processes. I just haven't seen good consistency for 6
thermal excursions yet.
"One OEM company wanted to do accelerated ageing by using steam ageing - a
technique developed to artificially age reflowed tin lead, but pounced on
as
the 'be all and end all' method for ALL surface finishes. Not surprisingly,
it failed miserably and the company dismissed OSP as an alternative. "
*** The Alternative Final Finishes, JSTD-002 and JSTD-003 committees have
been making a very deliberate effort to re-educate the industry that steam
"aging" is not aging. The use of steam is one conditioning method for
determining the robustness of a surface finish. There have been a number of
studies which have shown that the oxide morphology/species produced in
steam conditioning is not the same oxide morphology/species after a year of
ambient conditions. And the perception that steam conditioning is
applicable to all surface finishes is incorrect, as you example shows. The
Alternative Final Finishes committee, chaired by Denny Fritz, is working
very diligently on determining a conditioning recipe that is more
applicable to all finishes and they will be issuing a report this year. The
JSTD-003 committee intends to use that report to revise the steam
conditioning requirements.
"I don't understand this issue as all the solder joints on an assembly were
made at the time the board was first soldered, any surface finish on the
raw
card has been incorporated into the solder joint or disappeared through
volatisation at the point of soldering. Surely any rework soldering will be
on a solder joint, not on an ancient surface finish?"
*** You are correct and if I had given a more complete answer it would have
helped dispel the confusion. There are some areas on the assemblies which
are left unsoldered for future component additions, modifications, and
there are always test points. If you don't deposit solder on these during
the initial assembly process then later in life they become a real bear to
solder/test. And yes, one way to avoid that problem would be to just
deposit some solder on those locations during initial assembly. However,
because we allow surface finish variation from lot to lot (we give our
vendors a choice of surface finish on many designs in an attempt to make
the pwb fabrication process as robust as possible) we don't always need to
"pretin" those vacant locations. We also don't want to have multiple
stencils or finish specific stencils stored on the assembly floor. The days
of just have HASL finish did have some advantages.
Hope that clears up the confusion.
Dave Hillman
Rockwell Collins
[log in to unmask]
Dougal Stewart <[log in to unmask]>@ipc.org> on 04/19/2002
04:14:18 AM
Please respond to Dougal Stewart <[log in to unmask]>
Sent by: TechNet <[log in to unmask]>
To: [log in to unmask]
cc:
Subject: Re: [TN] OSP Re: [TN] Immersion Silver
Sorry Eric, I'm afraid that I can't answer your specific questions, as I am
not very experienced on the assembly side of the operation (last did
assembly in 1986 when it was still all through hole). What I do know is
that
the modern OSPs are capable of withstanding up to 6 heat cycles, ie you can
glue cure, wave solder, paste reflow and handsolder without losing
solderability. I don't know what the cleaning process in between will do -
you would have to ask the OSP supplier like Cookson for compatibility -
Entec 106A is a Cookson product that they support from all angles - OSP
chemistry, paste, flux, cleaners etc.
I was involved with surface finishes a number of years ago, and found the
ignorance in some (assembly) companies astounding, whilst others fully
understood what they were dealing with.
One OEM company wanted to do accelerated ageing by using steam ageing - a
technique developed to artificially age reflowed tin lead, but pounced on
as
the 'be all and end all' method for ALL surface finishes. Not surprisingly,
it failed miserably and the company dismissed OSP as an alternative. After
much persuasion they tried again, and 8 weeks after supplying product to
them, they told me that OSP had failed due to its inability to solder after
the first side. What they didn't tell me, at first, was that they tried to
solder side 2 four weeks after side 1, because this simulated what happened
in their production. Sad to say they have now closed that factory, losing
over 1000 jobs, and all their work is now manufactured by CEMs somewhere in
the far east. I think the inability to understand the basics of JIT
contributed to this greatly.
On the positive side, I worked closely with a (very) major telecomms
company, who saw the benefits of OSP and worked on the basis of never put a
board into assembly unless it can be SHIPPED within 24 hours. They are
still
a very successful Telecomm company despite the worldwide downturn.
I have read all the other mails responding to my plea, and I think that the
general message is that surface finish should be related to need and data,
not fashion and opinion.
I would also like to answer Dave Hillman's point
-> 'Field repair - OSPs don't provide the long term solderability on pwa's
which have been in the field for a number of years which sometimes are
subjected to upgrades/changes. It is typically an uphill struggle to have
good solderability for HASL for servicing an assembly which has been in the
field for 5-10 years anyway and OSPs just give up the ghost way to early in
comparison to metallic surface finishes.'
I don't understand this issue as all the solder joints on an assembly were
made at the time the board was first soldered, any surface finish on the
raw
card has been incorporated into the solder joint or disappeared through
volatisation at the point of soldering. Surely any rework soldering will be
on a solder joint, not on an ancient surface finish? However, I am glad to
hear that Rockwell use OSP as one of their finishes, on the basis of the
right finish for the right reason.
Rich Fudalewski (and Bob Furrow) stated: 'The other area where OSP can fail
is with via in pad (VIP) product. If there is any residue remaining in the
holes it will cause a degradation of the OSP coating. determine to not be
the OSP process at fault, but rather things like unseen soldermask residues
or incomplete removal of the tin etch resist. Doug, this seems to be a
problem with your board manufactures control of the process.'
I couldn't agree more with this, and have seen even worse issues with
immersion tin, where the thiourea emerges from the VIP during the first
side
reflow. I have seen issues with immersion silver where the undercut of the
soldermask traps residues that corrode the finish, and problems with ENIG
where nickel foot has almost shorted between pads. I return to my original
point - only OSP is reworkable in these situations. All of the other
finishes will end up with scrapping the raw card rather than rework, and
even though companies go bust if they cannot control their processes, scrap
is always paid for by us the end customers somewhere down the line (even if
its to pay higher national insurance or tax to cover the unemployment
benefit of those who lost their jobs).
I hope not to have preached too much, and that Rich F has his faith
restored
that Fab people do respond ! I am glad to have rekindled some interest
anyway!
Dougal Stewart
email: [log in to unmask]
phone: +44 1896 822204
mob: +44 7984 629667
----- Original Message -----
From: "Eric Dawson" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Thursday, April 18, 2002 1:40 PM
Subject: Re: [TN] Immersion Silver
> Hi Dougal,
> OSP sounds attractive but can I seek your views on a couple of points?
> We double side reflow and clean between operations to avoid baking the
flux
> on. These are complex boards and can take several days to progress
through
> the line. Will the OSP stay fresh for the second side reflow or would we
> have to treat the surface? Will cleaning take it off? (Prozone).
> Regards
> Eric Dawson
>
>
> > -----Original Message-----
> > From: Dougal Stewart [SMTP:[log in to unmask]]
> > Sent: Thursday, April 18, 2002 10:57 AM
> > To: [log in to unmask]
> > Subject: Re: [TN] Immersion Silver
> >
> > I would like to know why people don't use OSP - from a board shop's
> > viewpoint, it is the best finish to put on a board - why ? because it
is
> > very simple chemistry, puts no thermal shock on the product, is applied
on
> > a
> > SHORT conveyor line, and can be easily reworked unlike ANY of the other
> > finishes. The assembly guys don't like it if they start assembling a
> > product
> > and then stop because they don't have the parts to finish the job, but
> > anyone that puts a board into assembly without the ability to finish it
> > within 6 hours obviously knows nothing about world class manufacturing
> > practise. As for shelf life, if your stock is even 2 years old, send
the
> > boards back to the board shop and for a small fee they just put them
back
> > down the line again and you have a finish that is good as new, without
> > having undergone a vicious chemical attack to remove the finish.
> > Just my thoughts !
> > Dougal Stewart
> >
> > email: [log in to unmask]
> > phone: +44 1896 822204
> > mob: +44 7984 629667
> > ----- Original Message -----
> > From: "Jack C. Olson" <[log in to unmask]>
> > To: <[log in to unmask]>
> > Sent: Wednesday, April 17, 2002 4:22 PM
> > Subject: Re: [TN] Immersion Silver
> >
> >
> > > Hmmm,
> > >
> > > Well, at some point in EVERY new technology it was used by less
> > > than 3% of the world, eh? Guess I'm just a trailblazer....
> > >
> > > naw, just kiddin ya.
> > > I subscribed to a magazine called Circuitree, and the last issue
> > > came bundled with another publication called "The Board Authority"
> > > which has some very well written (and well researched!) articles
> > > on alternate finishes. I can't see any downside to using silver
> > > in our applications, and I've looked all through the archives for
> > > Technet, DesignerCouncil and PCDlist forums, still no show-stoppers,
> > > so we tried it for the first time on our last design. Yes, HASL and
> > > NiGold do work fine, but maybe we can get the same functionality
> > > for cheaper, and do our fab vendor a favor in the process, since
> > > they seem to prefer it (less steps? more reliable? not sure) maybe
> > > the fab guys can answer that one....
> > >
> > > Jack
> > >
> > >
> > >
> > >
> > >
> > > "WEEKES, MICHAEL HS-SNS" <[log in to unmask]>
> > > 17Apr2002 09:16 AM
> > >
> > >
> > > To: "'TechNet E-Mail Forum.'" <[log in to unmask]>
> > > "'Jack C. Olson'" <[log in to unmask]>
> > > cc:
> > >
> > > Subject: RE: [TN] Immersion Silver
> > > Retain Until: 05/17/2002 Retention Category: G90 - Information and
> > Reports
> > > Caterpillar Confidential: Green
> > >
> > >
> > > There must be some reason why less than 3% of the world has moved
toward
> > > immersion silver. Why doesn't HASL or NiGold work for your
application?
> > >
> > > Mike
> > >
> > > -----Original Message-----
> > > From: Jack C. Olson [mailto:[log in to unmask]]
> > > Sent: Wednesday, April 17, 2002 7:39 AM
> > > To: [log in to unmask]
> > > Subject: Re: [TN] Immersion Silver
> > >
> > >
> > > The PCD magazine list went down before I could get an
> > > answer to this question, does anyone have experience
> > > with silver and contact switches?
> > >
> > > ==============================================
> > >
> > > Most sources say a silver surface will not be solderable
> > > after a month or so unprotected. (Even in a baggie it will
> > > be okay a year later?)
> > > Anyway, you say it is good for switches, which would solve
> > > some of our hard gold plating problems.
> > >
> > > But I would think the "unsolderability" of the aged silver
> > > surface (unprotected in the unit and tarnished?) would
> > > affect the reliability of the switches, wouldn't it?
> > >
> > > Jack
> > >
> > >
> > >
> > >
> > >
> > >
> > > Rob Mongey <[log in to unmask]>@freelists.org
> > > 4Apr2002 06:08 AM
> > >
> > > Please respond to [log in to unmask]
> > >
> > > Sent by: [log in to unmask]
> > >
> > >
> > >
> > > To: [log in to unmask]
> > > cc:
> > >
> > > Subject: [pcdlist] Re: Immersion Silver
> > > Retain Until: 05/04/2002 Retention Category: G90 - Information and
> > Reports
> > > Caterpillar Confidential: Green
> > >
> > >
> > >
> > > Hi all,
> > > Good to see Immersion Silver is starting to take off. We've been
> > using
> > > it
> > > in here for about two years, and it is now our prefered board finish
(We
> > > get silver finish unless we specify differently.) More common useage
> > will
> > > mean that maybe more Far Eastern shops will start supplying it.
> > >
> > > We started to use Silver because it is so adaptable to what we
need
> > > our
> > > PCB surface finish to do, namely:
> > >
> > > 1. Good solderability. (Silver excels at this, ask any vendor).
> > > 2. Flatness for fine pitch SMT. (Silver is as flat, if not flatter
than
> > > Gold)
> > > 3. Mechanical strength for carbon pill switch contacts / Elastomer
> > > contacts. ( Flash Gold is weak, and hard Gold gives SMT solderability
> > > problems)
> > > 4. Stability for compression power contacts. (We have power contacts
on
> > our
> > > PCBs that mate to battery contacts via a spring compression. We found
> > that
> > > the nickel under gold can cause problems with electrochemical
migration
> > > toward our battery contact.)
> > >
> > > Immersion silver is the most suitable choice that can do all four.
I'd
> > use
> > > gold as an alternative, but we'd have to compromise our designs
> > somewhat.
> > >
> > > We specify our Silver finish as 0.1 Microns Min to 0.2 Microns Max,
over
> > > bare copper. Anyone else do it differently? Or do we trust our board
> > shops?
> > > :)
> > >
> > > Regards,
> > > Rob
Mongey.
> > > CAD
Technician.
> > >
> > > Robert Mongey <[log in to unmask]> Tel : +353 (0)91 774300
> > > Bio Medical Research Direct : +353 (0)91 774338
> > > BMR House, Fax : +353 (0)91 774302
> > > Parkmore Business Park West, Mobile : +353 (0)87 2485262
> > > Galway
> > > Rep of Ireland.
> > >
> > >
>
>
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Date: Fri, 19 Apr 2002 09:15:31 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Mel Parrish <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Mel Parrish <[log in to unmask]>
Subject: Re: Silver
X-To: Scott Kauling <[log in to unmask]>
In-Reply-To: <43EE6214823FD11191AB00A0C98454583D275B@WINNT-SERVR-01>
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Scott,
The content of 610 regarding silver plate wire is one of those dinosaurs
that is left over from the 70s and that originated in the very early Mil
Specs or maybe even NHB. You will not even find a reference in MIL-STD-2000
to restrict silver.
Contract documents and BOM commonly reference silver wire for production and
the justification as I recall was improved shelf life and solderability.
Additionally silver plate wire achieved preferred performance in
solderability testing after steam aging required under 202.
I'm sure there was a justification originally for the restriction but it was
before my time and that is saying sumpin.
Mel Parrish
Soldering Technology International
102 Tribble Drive
Madison, AL 35758
256 705 5530
256 705 5538 Fax
[log in to unmask]
www.solderingtech.com
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Scott Kauling
Sent: Thursday, April 18, 2002 5:15 PM
To: [log in to unmask]
Subject: [TN] Silver
With all of the discussion about the immersion silver, I have a few
questions.
Why can you not use silver jumper wire per IPC-A-610, but it is OK to use
it for a board finish?
I was given a sample of a conductive pen to try as an alternate for jumper
wires and it contains silver. Is anyone using a product such as this on
production boards or is this something that should be kept in the
engineering lab as products are being developed?
I am sure that you folks will clear up my confusion.
SCOTT
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Date: Fri, 19 Apr 2002 10:27:45 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Jack C. Olson" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Jack C. Olson" <[log in to unmask]>
Subject: Re: Immersion Silver
X-To: Rob Legg <[log in to unmask]>
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
oh, I probably wasted your time.
I was talking about little pushbutton dome switches like
for a remote control. In the past it was a requirement to
use hard gold electroplating, which meant I had to design
in plating bars, but it would be convenient for me if the
Immersion silver could do the same job.
thanks for the info, though, I appreciate it
Jack
"Rob Legg" <[log in to unmask]>
17Apr2002 01:54 PM
To: "TechNet E-Mail Forum." <[log in to unmask]>
"Jack C. Olson" <[log in to unmask]>
cc:
Subject: Re: Re: [TN] Immersion Silver
Retain Until: 05/17/2002 Retention Category: G90 - Information and Reports
Caterpillar Confidential: Green
Silver finds it's way into high energy switchgear contacts (not solder
terminations) due to it's ability to maintain a functional contact surface
in the presence of arcing. Normal contamination of surfaces is defeated
through the wiping action forced on these contacts, when in transition.
Arcing and static surfaces of the contact are partitioned, where possible.
High rel components (mtbf still sucks) are hermetically sealed.
The mfring process is generally hostile to all switchgear; uncovered or
unsealed parts require special handling to reduce fallout.
Silver has no greater suitability for forming reliable solder joints, on or
in switchgear, than it has anywhere else.
A month is a very short time to guarantee solderability. Have you looked at
the date-codes on some of your electromechanical parts?
RL
[log in to unmask]
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Date: Fri, 19 Apr 2002 09:16:44 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Greg Scott <[log in to unmask]>
Organization: Cray Inc
Subject: Re: IPC SMT FOOTPRINT DESIGN GUIDLINES VS SUPPLIERS
X-To: Rob Legg <[log in to unmask]>
MIME-Version: 1.0
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Gary- great idea, IPC needed to expand it list of component land
patterns.
Having choices between HDI footprints and relaxed (typical)
designs is something
most of us designers have to constantly do on our own. I
work in an environment
where 40% of my designs require changes to footprint designs
(Both IPC and Supplier)
to accommodate for lack of real-estate.
Missing footprint option in new IPC-7351 format.
Descretes need a design showing VIP (via in pad)
configuration. Most people trying this in design would agree
via should be located off center from the pad. For power
inductance reasons we place them on the
inside edge of pads. So vias are as close to each other as
practical. I know this could be a reach for IPC
to join in on this concept, but it is here to stay. HDI
design require this concept to work.
Since the council has both fabrication and assembly members
they should show how they prefer
VIP technology.
Greg Scott
Cray Inc.
Rob Legg wrote:
> That's what I like about standards. No ambiguity, good resale value
> and low-cost maintenance for the end user. RL
>
> ----- Original Message -----
> From: Gary Ferrari
> To: [log in to unmask]
> Sent: Thursday, April 18, 2002 7:15 PM
> Subject: Re: [TN] IPC SMT FOOTPRINT DESIGN GUIDLINES VS
> SUPPLIERS
> I would like to address a few of the comments that have
> been made.
>
> First, when the same component parameters and design fillet
> goals are input into the current web based calculator they
> should yield the same land pattern as listed in the RLP
> section. We have on occasion found an error in the component
> data listed in the hard copy or web calculator and have made
> appropriate corrects. Any discrepancies found should be
> reported to John Perry at IPC.
>
> Second is that the calculator is based on the same
> principles as found in the hard copy of the standard. It is
> true that land patterns for the newer components may not
> have been tested as the earlier ones were. But in many cases
> the basic principles remain untouched. However, the land
> pattern committee does approve each new pattern based on an
> assessment culled from their own experiences with that
> component as well as input from other industry sources.
>
> The last issue is that the 782 land pattern committee is
> currently working on a complete revision to our land pattern
> document. I would point out that one should not perceive the
> revised document as an indication that there is something
> wrong with the current land patterns. This effort is
> addressing new component families as well as a new concept
> going forward.
>
> The new standard will be identified as IPC-7351 and will be
> of a format that provides slash sheets for the various
> component families. This will enable new component additions
> to get released in a much more timely fashion. The standard
> will contain four columns of data for each component. The
> first column will be the existing 782 pattern data. The next
> three will represent minimum, median and maximum
> applications. All component types not currently in 782 will
> be released to this new format. AS we move forward, we will
> NOT be adding data under the 782 columns for components not
> currently listed in the current 782.
>
> As a general point of information, you will find that the
> current 782 land patterns will fall someplace between the
> minimum and median columns. What is important to recognize
> is that compromises were taken to reach the smaller sizes
> and it will be quite apparent where they were made. It would
> be wise for the designer to obtain approval from those
> affected by the compromises before using the smaller sizes.
>
> The first release will contain the current 782 listed
> components with additional component slash sheets released
> in rapid succession thereafter.
>
> Regards,
>
> Gary Ferrari
> Executive Director
> IPC Designers Council
> (860) 350-9300
> Fax (413) 771-5386
>
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Gary- great idea, IPC needed to expand it list of component land
patterns.
<br>
Having choices between HDI footprints and relaxed (typical) designs is
something
<br>
most of us designers have to constantly do on our own. I work in
an environment
<br>
where 40% of my designs require changes to footprint designs (Both IPC
and Supplier)
<br>
to accommodate for lack of real-estate.
<p> Missing
footprint option in new IPC-7351 format.
<br>
Descretes need a design showing VIP (via in pad) configuration. Most
people trying this in design would agree
<br>
via should be located off center from the pad. For power inductance
reasons we place them on the
<br>
inside edge of pads. So vias are as close to each other as practical.
I know this could be a reach for IPC
<br>
to join in on this concept, but it is here to stay. HDI design require
this concept to work.
<p> Since
the council has both fabrication and assembly members they should show
how they prefer
<br>
VIP technology.
<br>
<p>Greg Scott
<br>Cray Inc.
<br>
<br>
<p>Rob Legg wrote:
<blockquote TYPE=CITE><style></style>
<font face="Arial"><font size=-1>That's
what I like about standards. No ambiguity, good resale value and low-cost
maintenance for the end user.</font></font> <font face="Arial"><font size=-1>RL</font></font>
<blockquote
style="PADDING-RIGHT: 0px; PADDING-LEFT: 5px; MARGIN-LEFT: 5px; BORDER-LEFT: #000000 2px solid; MARGIN-RIGHT: 0px">
<div style="FONT: 10pt arial">----- Original Message -----</div>
<div
style="BACKGROUND: #e4e4e4; FONT: 10pt arial; font-color: black"><b>From:</b>
<a href="mailto:[log in to unmask]" title="[log in to unmask]">Gary Ferrari</a></div>
<div style="FONT: 10pt arial"><b>To:</b> <a href="mailto:[log in to unmask]" title="[log in to unmask]">[log in to unmask]</a></div>
<div style="FONT: 10pt arial"><b>Sent:</b> Thursday, April 18, 2002 7:15
PM</div>
<div style="FONT: 10pt arial"><b>Subject:</b> Re: [TN] IPC SMT FOOTPRINT
DESIGN GUIDLINES VS SUPPLIERS</div>
<b><i><font face="Comic Sans MS"><font color="#8000FF"><font size=-1>I
would like to address a few of the comments that have been made.</font></font></font></i></b>
<p><b><i><font face="Comic Sans MS"><font color="#8000FF"><font size=-1>First,
when the same component parameters and design fillet goals are input into
the current web based calculator they should yield the same land pattern
as listed in the RLP section. We have on occasion found an error in the
component data listed in the hard copy or web calculator and have made
appropriate corrects. Any discrepancies found should be reported to John
Perry at IPC.</font></font></font></i></b>
<p><b><i><font face="Comic Sans MS"><font color="#8000FF"><font size=-1>Second
is that the calculator is based on the same principles as found in the
hard copy of the standard. It is true that land patterns for the newer
components may not have been tested as the earlier ones were. But in many
cases the basic principles remain untouched. However, the land pattern
committee does approve each new pattern based on an assessment culled from
their own experiences with that component as well as input from other industry
sources.</font></font></font></i></b>
<p><b><i><font face="Comic Sans MS"><font color="#8000FF"><font size=-1>The
last issue is that the 782 land pattern committee is currently working
on a complete revision to our land pattern document. I would point out
that one should not perceive the revised document as an indication that
there is something wrong with the current land patterns. This effort is
addressing new component families as well as a new concept going forward.</font></font></font></i></b>
<p><b><i><font face="Comic Sans MS"><font color="#8000FF"><font size=-1>The
new standard will be identified as IPC-7351 and will be of a format that
provides slash sheets for the various component families. This will enable
new component additions to get released in a much more timely fashion.
The standard will contain four columns of data for each component. The
first column will be the existing 782 pattern data. The next three will
represent minimum, median and maximum applications. All component types
not currently in 782 will be released to this new format. AS we move forward,
we will NOT be adding data under the 782 columns for components not currently
listed in the current 782.</font></font></font></i></b>
<p><b><i><font face="Comic Sans MS"><font color="#8000FF"><font size=-1>As
a general point of information, you will find that the current 782 land
patterns will fall someplace between the minimum and median columns. What
is important to recognize is that compromises were taken to reach the smaller
sizes and it will be quite apparent where they were made. It would be wise
for the designer to obtain approval from those affected by the compromises
before using the smaller sizes.</font></font></font></i></b>
<p><b><i><font face="Comic Sans MS"><font color="#8000FF"><font size=-1>The
first release will contain the current 782 listed components with additional
component slash sheets released in rapid succession thereafter.</font></font></font></i></b>
<p><b><i><font face="Comic Sans MS"><font color="#8000FF"><font size=-1>Regards,</font></font></font></i></b>
<p><b><i><font face="Comic Sans MS"><font color="#8000FF"><font size=-1>Gary
Ferrari</font></font></font></i></b>
<br><b><i><font face="Comic Sans MS"><font color="#8000FF"><font size=-1>Executive
Director</font></font></font></i></b>
<br><b><i><font face="Comic Sans MS"><font color="#8000FF"><font size=-1>IPC
Designers Council</font></font></font></i></b>
<br><b><i><font face="Comic Sans MS"><font color="#8000FF"><font size=-1>(860)
350-9300</font></font></font></i></b>
<br><b><i><font face="Comic Sans MS"><font color="#8000FF"><font size=-1>Fax
(413) 771-5386</font></font></font></i></b></blockquote>
</blockquote>
</body>
</html>
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Date: Fri, 19 Apr 2002 13:19:21 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Louis, Edwin @ CSE" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Louis, Edwin @ CSE" <[log in to unmask]>
Subject: Re: OSP
X-To: "Wenger, George M." <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
George, where are you? I called your phone number about two weeks ago and it
was non-functional.
-----Original Message-----
From: Wenger, George M. [mailto:[log in to unmask]]
Sent: Thursday, April 18, 2002 9:53 PM
To: [log in to unmask]
Subject: Re: [TN] OSP
Earl,
I'd like to expand and comment on you question "Where have all the board
people gone, long time passing". Unfortunately the board people whet by the
wayside just like many other technical people. Companies have down sized
their technical efforts and increased their supply chain efforts with the
rational that we don't have to pay for technical information because our
suppliers will give us what we need for free. Well the one thing most
people learn during their life time is you get what you pay for. In the
past 18 months or more the attendance at technical conferences and seminars
has decreased, the technical content in email forms such as TechNet have
decreased and when you ask a supplier for technical date you get sales
information.
I'm not sure how or if there is going to be a reversal but I sure hope that
young engineers entering the work place keep letting their management know
that engineering date not sales information is needed to make informed
decisions and effective risk assesments.
-----Original Message-----
From: Earl Moon [mailto:[log in to unmask]]
Sent: Thursday, April 18, 2002 3:15 PM
To: [log in to unmask]
Subject: Re: [TN] OSP
Outstanding Rick,
I agree and side with Kerry as well but for his "boring" comment. I know he
meant well as we all try CPI.
Other folks, me included, have commented on the lack of board type people
participating enough on this forum. I certainly have done my best to get
them back but probably have bored them and others to leaving because of my
excessive time on the forum.
Phil Hinton said this forum is becoming an "good old boys club" or some such
thing. I agreed then as now but we have the freedom to participate or not.
I just want the facts man, just the facts. I have way more questions than
answers but one thing is sure - we need more fabricators on this thing.
I just finished a concurrent engineering conference with my assembler, my
company, and my fab supplier. Excellent results concerning solder wetting,
or not.
Turns out our great fab supplier (Proto Engineering)provided highly
solderable ENIG boards that didn't look that great after assembly in some
areas. Also turns out, our fantastic assembler (MPI) uses the latest DEK
stencil printers with ProFlo heads. Because of this, and the large pads
required for a few parts, MPI requested steicils with "window pane"
apertures for these large pads. Hence, non wetting on some pad areas. New
one to me but greatly appreciated for us all.
Where have all the board people gone, long time passing. I'll get of the
fourm if it's me but we need fab folks no matter.
MoonMan
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Date: Fri, 19 Apr 2002 12:19:48 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Strickland, Mark" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Strickland, Mark" <[log in to unmask]>
Subject: Re: Silver
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
-----Original Message-----
From: Mel Parrish [mailto:[log in to unmask]]
Sent: Friday, April 19, 2002 9:16 AM
To: [log in to unmask]
Subject: Re: [TN] Silver
NASA's restriction for silver plated wire was due to a fear of cuprous
oxide. We have seen it but to my knowledge it hasn't caused a failure -
just fear. It was reported to me (w/o data) several years ago that the USSR
had failures in the utility (power) distribution industry due to silver
plated wire over copper (the silver plating must have been pitted).
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Date: Fri, 19 Apr 2002 13:36:38 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Steve Kelly <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Steve Kelly <[log in to unmask]>
Subject: Bonding of metal stiffeners onto flex
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit
I am looking for a material I can use to bond metal stiffeners onto flex but
it must have very low moisture absorption properties - standard acrylis or
epoxies will not do.
Regards Steve Kelly
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Date: Fri, 19 Apr 2002 14:29:54 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Sauer, Steven T." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Sauer, Steven T." <[log in to unmask]>
Subject: Re: Silver
X-To: Mel Parrish <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
To add to what Mel said: the reason for the disallowance had to do with the
susceptibility for "red plague" formation.
This is not to imply that I've been around longer than Mel, it was well
before my time but my mind is full of "usually nonimportant" trivial things
that at times prove to be useful!
Steve Sauer
Mfg Engineer
Northrop Grumman, Xetron
-----Original Message-----
From: Mel Parrish [mailto:[log in to unmask]]
Sent: Friday, April 19, 2002 10:16 AM
To: [log in to unmask]
Subject: Re: [TN] Silver
The content of 610 regarding silver plate wire is one of those dinosaurs
that is left over from the 70s and that originated in the very early Mil
Specs or maybe even NHB. You will not even find a reference in MIL-STD-2000
to restrict silver.
Contract documents and BOM commonly reference silver wire for production and
the justification as I recall was improved shelf life and solderability.
Additionally silver plate wire achieved preferred performance in
solderability testing after steam aging required under 202.
I'm sure there was a justification originally for the restriction but it was
before my time and that is saying sumpin.
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Date: Fri, 19 Apr 2002 11:50:23 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Ken Patel <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Ken Patel <[log in to unmask]>
Organization: interWAVE Communications, Inc.
Subject: Labor Price difference for 1-up v/s 4-up
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
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Assemblers,
What is the normal price reduction (discount) for 1-up board v/s 4-up on
a panel? 18x24 panel will give me 21 boards if I go for single or say
1-up while I can get only 16 boards if I go for 4-up on panel.
I have to make a decision should I go for 1-up or 4-up.
re,
ken patel
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Date: Fri, 19 Apr 2002 15:45:05 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
[log in to unmask]
Sender: TechNet <[log in to unmask]>
From: "Brian L. Guidi" <[log in to unmask]>
Subject: Peelable Soldermask
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
Good afternoon fellow techies...
I am searching for information on peelable soldermask, or an
acceptable alternative. I have an application which requires temporary
coverage of immersion gold plated fingers, through subsequent wet process
operations (additional 'electrolytic' gold plating). I need to cover the
fingers so they do not plate up when the electro-deposited gold is added
(the nets are connected) to the other end of the board. The situation is
complicated by the fact that the area requiring coverage is approximately
.012" below the external surface of the board, therefore standard
etch/plate dryfilm is not practical due to voiding. I'll try to provide a
mental picture: Imaging a rectangular board 2" long by .500" wide. It's a 6
layer board. On one end, a portion of L4/5 about .750" long, extends beyond
the rest of the part (along the length) about .400". These "wings" are the
portion requiring coverage during the plating process that is happening at
the other end of the board.
Platers tape has been ruled out as an option due to volume. The plan
is to apply a dryfilm soldermask to the external board surfaces to
permanently protect/insulate the via's, and then apply a peelable mask over
the same area which would conform to the 'drop-down' (.012") and cover the
exposed fingers on L4/5. The peelable soldermask would then be removed to
expose the fingers to the cleaning solutions.
I am looking for material recommendations, vendors providing peelable
mask application services, and any practical experience anyone has had with
a similar situation. I hope the explanation is not too foggy. It is Friday
after all, and I have a meeting with Sam Adams in about an hour and a half!
Thanks in advance for your help and insight...
Brian Guidi
Product Engineer
Teledyne Electronic Technologies
Tel: (603) 889-6191 X:310
Fax: (603) 886-2977
E-mail: [log in to unmask]
Any technical information attached to this document is intended for the
recipient only. Also, the export and use of the information is regulated
by the export laws of the United States. Diversion contrary to U.S. law is
prohibited. U.S. law prohibits sharing this information with any end-user
for any end-use related to the design, development, production, stockpiling
or use of chemical, biological or nuclear weapons or missiles, without the
prior approval of the United States Government.
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Date: Fri, 19 Apr 2002 14:51:00 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
[log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Filter Recommendation
MIME-Version: 1.0
Content-type: text/plain; charset="us-ascii"
Good day all,
We are implementing a wider use of one of our urethane-based adhesives here
at Rockwell. This product gives off low levels of isocyanate, as most
urethanes do. It is well under NIOSH limits, but our Occupational Safety
and Health folks have followed the course of prudence and indicated that if
our ovens are not vented to the outside, then they must be fitted with an
organic vapor filter before being exhausted into the workplace. I agree
with the approach, but our overworked and underappreciated staff is a
little slow in getting back some suggestions on model numbers and types,
etc.
So, I turn to my deep store of corporate knowledge (Technet) and ask Y'all
if you cure urethanes and what filters you use. I have been thinking
activated carbon, but some here figure that solution is unworkable.
Doug Pauls
Rockwell Collins
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=========================================================================
Date: Fri, 19 Apr 2002 16:13:53 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Scott Kauling <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Scott Kauling <[log in to unmask]>
Organization: Tri-onics, Inc.
Subject: Re: Labor Price difference for 1-up v/s 4-up
X-To: Ken Patel <[log in to unmask]>
Ken,
This is something that you should work out with your assembler. The
decision should be more along the lines of how will each of your array
configurations fit into their equipment.
SCOTT
-----Original Message-----
From: Ken Patel [SMTP:[log in to unmask]]
Sent: Friday, April 19, 2002 1:50 PM
To: [log in to unmask]
Subject: [TN] Labor Price difference for 1-up v/s 4-up
Assemblers,
What is the normal price reduction (discount) for 1-up board v/s 4-up on
a panel? 18x24 panel will give me 21 boards if I go for single or say
1-up while I can get only 16 boards if I go for 4-up on panel.
I have to make a decision should I go for 1-up or 4-up.
re,
ken patel
------------------------------------------------------------------------
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=========================================================================
Date: Fri, 19 Apr 2002 16:22:48 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Scott Kauling <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Scott Kauling <[log in to unmask]>
Organization: Tri-onics, Inc.
Subject: Re: Labor Price difference for 1-up v/s 4-up
X-To: Ken Patel <[log in to unmask]>
Ken,
If you are having someone else build your boards you should work it out
with your CM. Not only should you be concerned with labor and handling
time, you should also make sure that the panel configuration is compatible
with ALL of their assembly equipment needed to produce your assembly.
Scott Kauling
-----Original Message-----
From: Ken Patel [SMTP:[log in to unmask]]
Sent: Friday, April 19, 2002 1:50 PM
To: [log in to unmask]
Subject: [TN] Labor Price difference for 1-up v/s 4-up
Assemblers,
What is the normal price reduction (discount) for 1-up board v/s 4-up on
a panel? 18x24 panel will give me 21 boards if I go for single or say
1-up while I can get only 16 boards if I go for 4-up on panel.
I have to make a decision should I go for 1-up or 4-up.
re,
ken patel
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=========================================================================
Date: Fri, 19 Apr 2002 14:47:35 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Barmuta, Mike" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Barmuta, Mike" <[log in to unmask]>
Subject: Re: Peelable Soldermask
X-To: "[log in to unmask]" <[log in to unmask]>
MIME-Version: 1.0
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Brian:
There are several vinyl based temporary peelable masks that should work.
These products can be applied by printing using an imaged screen, similar
to(non-photoimageable)permanent soldermask application. They normally
require a post application bake to achieve the proper chemical resistant
properties and release characteristics.
It should stand up to your electroplated Ni and Au processes. In some cases
it is somewhat of a pain to remove depending on the size and configuration,
but worth a try.
Lackwerke Peters GmbH, MacDermid, Electra and Alpha Metals all used to carry
these types of products.
Regards
Michael Barmuta
Staff Engineer
Fluke Corp.
Everett WA
425-446-6076
-----Original Message-----
From: Brian L. Guidi [mailto:[log in to unmask]]
Sent: Friday, April 19, 2002 12:45 PM
To: [log in to unmask]
Subject: [TN] Peelable Soldermask
Good afternoon fellow techies...
I am searching for information on peelable soldermask, or an
acceptable alternative. I have an application which requires temporary
coverage of immersion gold plated fingers, through subsequent wet process
operations (additional 'electrolytic' gold plating). I need to cover the
fingers so they do not plate up when the electro-deposited gold is added
(the nets are connected) to the other end of the board. The situation is
complicated by the fact that the area requiring coverage is approximately
.012" below the external surface of the board, therefore standard
etch/plate dryfilm is not practical due to voiding. I'll try to provide a
mental picture: Imaging a rectangular board 2" long by .500" wide. It's a 6
layer board. On one end, a portion of L4/5 about .750" long, extends beyond
the rest of the part (along the length) about .400". These "wings" are the
portion requiring coverage during the plating process that is happening at
the other end of the board.
Platers tape has been ruled out as an option due to volume. The plan
is to apply a dryfilm soldermask to the external board surfaces to
permanently protect/insulate the via's, and then apply a peelable mask over
the same area which would conform to the 'drop-down' (.012") and cover the
exposed fingers on L4/5. The peelable soldermask would then be removed to
expose the fingers to the cleaning solutions.
I am looking for material recommendations, vendors providing peelable
mask application services, and any practical experience anyone has had with
a similar situation. I hope the explanation is not too foggy. It is Friday
after all, and I have a meeting with Sam Adams in about an hour and a half!
Thanks in advance for your help and insight...
Brian Guidi
Product Engineer
Teledyne Electronic Technologies
Tel: (603) 889-6191 X:310
Fax: (603) 886-2977
E-mail: [log in to unmask]
Any technical information attached to this document is intended for the
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by the export laws of the United States. Diversion contrary to U.S. law is
prohibited. U.S. law prohibits sharing this information with any end-user
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Date: Fri, 19 Apr 2002 17:15:23 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
[log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Dave Hillman <[log in to unmask]>
Subject: Re: Cracking Chip Resistors
X-To: [log in to unmask]
MIME-Version: 1.0
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Hi TechNet! Just wanted to say thanks to everyone for the suggestions you
generated concerning my cracking resistor question. And here is "the rest
of the story"! I was able to successfully solder the chip resistors using a
reflow solder process. I am guessing the problem was a solder
process/material incompatibility. The flexural strength of the three
materials is Al2O3 = 80 ksi, BeO = 30 ksi, AlN = 50 ksi (sorry Steve - I am
metrically impaired so I switched everything to ksi!) covering a pretty
wide range. The reflow soldering process allowed both terminations to
"float" in a uniform manner when the solder solidified thus creating a much
more uniform stress impact on the resistor. The hand soldering operation
was most likely putting a larger stress on the resistor due to the
independent solidification of the terminations. We are also going to try
Vapor Phase soldering to see if we can repeat our success. Thanks again for
the assist!
Dave Hillman
Rockwell Collins
[log in to unmask]
"Creswick, Steven" <[log in to unmask]> on 04/16/2002 11:44:09 AM
To: "'TechNet E-Mail Forum.'" <[log in to unmask]>,
"[log in to unmask]" <[log in to unmask]>
cc:
Subject: RE: [TN] Cracking Chip Resistors
Dave,
As I recall AlN (4-4.5 ppm) has a lower TCE than either Alumina (7 ppm) or
Beo (7.2-8ppm) at soldering temperatures. One would expect that as the
PWB contracted during cooling (having a still greater TCE), that the
resistor would be in compression - not a problem here! Is the contraction
of the individual solder joints sufficient to crack the body??
I looked in my records but wouldn't you know it, I am missing tensile
strength info for AlN. But, yes it is weaker than Alumina.
Al2O3 - 0.193 GPa, BeO - 0.062-0.069GPa, AlN - ?
Flexural Strength -
Al2O3 - 0.274-0.4 GPa, BeO - 0.110 GPa, AlN - 0.25-0.32 GPa
Got me baffled as well. Never soldered BeO or AlN chip resistors - sorry.
Guess I need to down another Vernors Ginger Ale!
Steven Creswick - Gentex Corp
-----Original Message-----
From: Dave Hillman [mailto:[log in to unmask]]
Sent: Tuesday, April 16, 2002 10:28 AM
To: [log in to unmask]
Subject: [TN] Cracking Chip Resistors
Hi folks! I have ran into a problem which has me baffled and the extra 20
ounces of Coke I consumed this morning didn't bring about any better
thought clarity so I would like to bounce the problem off the minds of
TechNet. I have been attempting to hand solder a chip resistor (50 x 100)
but have immediate cracking of the resistor across the width of the
component. The resistor is either Aluminum Nitride or BeO (I'm still trying
to find out which material). And yes, we are using proper soldering
technique(s) and the resistor pad geometries are our standard dimensions. I
know that the typical resistor body material is Alumina. Has anyone had
good or bad experiences in hand soldering AlN or BeO resistors? Have I run
into a material flexural strength issue?
Dave Hillman
Rockwell Collins
[log in to unmask]
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Date: Sat, 20 Apr 2002 00:54:40 +0100
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Alan Groves <[log in to unmask]>
Subject: Re: Silver
X-To: "Sauer, Steven T." <[log in to unmask]>
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
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It is because of "usually nonimportant trivial things
that at times prove to be useful" that I am a reader of this forum!
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Sauer, Steven T.
Sent: Friday, April 19, 2002 7:30 PM
To: [log in to unmask]
Subject: Re: [TN] Silver
To add to what Mel said: the reason for the disallowance had to do with the
susceptibility for "red plague" formation.
This is not to imply that I've been around longer than Mel, it was well
before my time but my mind is full of "usually nonimportant" trivial things
that at times prove to be useful!
Steve Sauer
Mfg Engineer
Northrop Grumman, Xetron
-----Original Message-----
From: Mel Parrish [mailto:[log in to unmask]]
Sent: Friday, April 19, 2002 10:16 AM
To: [log in to unmask]
Subject: Re: [TN] Silver
The content of 610 regarding silver plate wire is one of those dinosaurs
that is left over from the 70s and that originated in the very early Mil
Specs or maybe even NHB. You will not even find a reference in MIL-STD-2000
to restrict silver.
Contract documents and BOM commonly reference silver wire for production and
the justification as I recall was improved shelf life and solderability.
Additionally silver plate wire achieved preferred performance in
solderability testing after steam aging required under 202.
I'm sure there was a justification originally for the restriction but it was
before my time and that is saying sumpin.
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Date: Sat, 20 Apr 2002 01:04:23 +0100
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Alan Groves <[log in to unmask]>
Subject: Re: Labor Price difference for 1-up v/s 4-up
X-To: Ken Patel <[log in to unmask]>
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
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Go for the best! Trial and error, always stipulate "If in doubt ask", if you
don't know, ask!
I am fairly new (13 years) in this game and I still am pretty stupid when it
comes to chemistry (and the whole fab process) but by asking I am learning!
The "if in doubt, ask" bit is Dickensian, I know, but the principal is
intact, whether (Shakespearean) you are a lender or a borrower!!!!
Hey Guys, this is my 'free' time.
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Ken Patel
Sent: Friday, April 19, 2002 7:50 PM
To: [log in to unmask]
Subject: [TN] Labor Price difference for 1-up v/s 4-up
Assemblers,
What is the normal price reduction (discount) for 1-up board v/s 4-up on
a panel? 18x24 panel will give me 21 boards if I go for single or say
1-up while I can get only 16 boards if I go for 4-up on panel.
I have to make a decision should I go for 1-up or 4-up.
re,
ken patel
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Date: Sat, 20 Apr 2002 07:04:23 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Glynn Shaw <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Glynn Shaw <[log in to unmask]>
Subject: Re: OSP
X-To: Earl Moon <[log in to unmask]>
In-Reply-To: <[log in to unmask]>
Mime-Version: 1.0
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After reading this Earl, I figured I better go explain to the frontline
that if a customer asks for photomicrographs then they are asking for
pictures of their cross sections. So she asks: Do I need to dress up?
Should I hold them in my hand and smile? or Should I display them like
those actors holding coke cans in the movies?
PS: do you want jpg's or gif's?
At 06:06 AM 4/19/02 -0500, you wrote:
>George,
>
>Thank you very much for shedding some light on an important, to us all,
>subject. Sure glad, for us all, you stick around though you're obviously
>thought of as much more than a board person.
>
>As for my experiences, and some of my friends in the business, I used to get
>mostly "up front" consulting jobs. Now, I get mostly "fix it" type work. I'm
>not complaining but, as you said, there seems a new way of designing,
>fabricating, and assembling product.
>
>The two examples, of my supplier base that's been with me for years, are
>good examples of concurrent engineering staffs. Sanmina Hadco, in its
>Haverhill tech center, still has this capability and I desparately hope it
>continues but, with the closure of its assembly tech center in Austin, I
>have to wonder if the pendulum is swinging back to "traditional" sales
>techniques (used car type approach).
>
>Though still providing good product, some of the other PCB technical
>"giants" don't talk technical anymore. They and many assembly houses talk
>the talk of sales folks mostly telling us/me what we/I want to hear. What
>they don't understand is I want to hear technical content with their ability
>to back it up.
>
>As much as I love my favorite board shop, PE, I have had few in depth
>technical discussions with them. As one example, I requested
>photomicrographs to accompany slugs before and after thermal stress to
>visually confirm their report. I was asked, when questioning why no pics
>were avaialable, as very nice sales lady, apparently, asked "what is
>photomicrographs?"
>
>I recognize my client's management, as many other companies, have limited
>knowledge concerning PCB's. That, in my opinion, is whay they should look
>for folks having up front approaches to preventing defect, through DFM/CE,
>at the design level.
>
>As you say, we need more good young engineers having the knowledge, talent,
>desire, and ability to do this ever more important job as the technical
>world gets more complex. I sure look back on a different world, but don't we
>all. Was it any better, I think so when it came to PCB's.
>
>Earl
>
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>information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700
>ext.5315
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>
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Date: Sat, 20 Apr 2002 09:04:30 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: OSP
X-To: [log in to unmask]
Hy Glynn,
Hoped to draw you out with that one. Just yanking PE's chain while giving
praise for fine work.
jpg's are fine with us all. Please send them to Ken Carlile as your people
have been communicating very well with him.
On other notes of importance, I/we are cleaning up our designs desparately
needing. New designs are coming along as well.
If you didn't know, ECC has several large Asian customers, and angels,
designing and using product for satellite communications as this area of the
world has no fiber optic land based cable. It appears one very bright spot
in the telecommunications world.
To this end, some or our designs are going into the 100,000 quanntities very
soon. Therefore, I need an Asian connection for these customers. You still
working with Star, the PCB fabricator, and do you have any Asian connections
with assemblers.
I have evaluated several assemblers, including xxx in China, but found them
very lacking in their capability to product quality, high reliability
assemblies.
Thanks for the reply and hope you are doing well,
Earl
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Date: Mon, 22 Apr 2002 09:54:04 +0100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Bernard, David" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Bernard, David" <[log in to unmask]>
Subject: Bar Code Standards
MIME-Version: 1.0
Content-Type: text/plain
Dear Technetters,
Can anybody tell me if there are any recommended standards for the
suggested data content within bar codes used on boards?
Thank you,
David
David Bernard
Dage Holdings Plc
Rabans Lane
Aylesbury
Buckinghamshire
HP19 8RG
United Kingdom
Tel: 01296 317860 - Direct
Tel: 01296 317800
Fax: 01296 435408
E: [log in to unmask]
W: www.dage-group.com
intY (www.inty.com) has automatically scanned this email using Sophos Anti-Virus
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Date: Mon, 22 Apr 2002 12:19:38 +0100
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Alan Groves <[log in to unmask]>
Subject: uBGA routing
MIME-Version: 1.0
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Hi Technetters, any help that could be given on following problem would be
greatly appreciated...
I am currently routing a PCB which has 532 pin uBGAs on it, these have a
pitch of 0,8mm (31,5 thou). I have followed manufacturer's design guidelines
in the past but am still receiving complaints from fabricators. I have
resolved vertically by having a 6 thou microvia drilled thru pad centres to
layer 2, then routed on layer 2 to a buried via (layers 2-7) of 10 thou
drill, 19 thou land. The track and gap allowance is 4 thou minimum. I am
using thermal connection pads of 17 (internal) and 26 (external) thou, and
isolating pads of 24 thou - all only on buried vias, I cannot increase these
pad sizes (much) or I could block GND and PWR from getting to destinations.
Fabricators complain of copper features too close to drill hole, are they
talking skew, or 'tear out' by that much (8 thou 'ish)?
The board is 1,6mm thick FR4, 8 conducting layers, no controlled impedance.
Can anyone suggest any tricks or tweaks to sizes that would assist?
Thanks in advance,
Alan Groves,
Senior PCB Designer CID
Spectel Head Office, 21 Stillorgan Ind. Park, Stillorgan,
Co. Dublin. Ireland.
Phone: 353 907 62803
Fax: 353 1 2953740
Email: [log in to unmask]
Internet: www.spectel.com
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Date: Mon, 22 Apr 2002 14:23:55 +0200
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Marki Sasportas <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Marki Sasportas <[log in to unmask]>
Subject: Boards Cleaning
MIME-Version: 1.0
Content-Type: text/plain; charset="windows-1255"
Dear Technetters,
Can anybody recommend me on cleaning process/materials for no-clean
assembled boards.
We have some problems with flux residues after touch up.
Thanks,
Marki Sasportas.
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Date: Mon, 22 Apr 2002 06:31:46 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
YH Koh <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: YH Koh <[log in to unmask]>
Subject: Contact Resistant on the Board
Dear Technet,
Would like to determine if there is a specification to check for the
surface contact resistant of the board when a metal dome (form the keypad)
is pressed on top on the boards. The resistance tolerance should be well
around +/-0.001 ohm. The reason is to address any intermittent contact
(like increse in resistnace) if there is an oxide layer or contamination on
the boards.
Appreicate any inputs.
Regards,
YH Koh
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Date: Mon, 22 Apr 2002 08:48:34 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Randy Bock Sr." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Randy Bock Sr." <[log in to unmask]>
Subject: Re: Contact Resistant on the Board
X-To: YH Koh <[log in to unmask]>
MIME-Version: 1.0
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Don't know of any at this time, but have had the same issue from time to
time and all we do is scrape away a little pf the surface. We have found an
excess build up of the carbon which causes an intermittent contact with the
keys.
Randy Bock Sr.
Quality Manager
Bryce Office Systems LLC
[log in to unmask]
----- Original Message -----
From: YH Koh <[log in to unmask]>
To: <[log in to unmask]>
Sent: Monday, April 22, 2002 7:31 AM
Subject: [TN] Contact Resistant on the Board
> Dear Technet,
>
> Would like to determine if there is a specification to check for the
> surface contact resistant of the board when a metal dome (form the keypad)
> is pressed on top on the boards. The resistance tolerance should be well
> around +/-0.001 ohm. The reason is to address any intermittent contact
> (like increse in resistnace) if there is an oxide layer or contamination
on
> the boards.
>
> Appreicate any inputs.
>
> Regards,
> YH Koh
>
> --------------------------------------------------------------------------
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>
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Date: Mon, 22 Apr 2002 15:49:37 +0300
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Brian Ellis <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Brian Ellis <[log in to unmask]>
Subject: Re: Boards Cleaning
X-To: Marki Sasportas <[log in to unmask]>
MIME-Version: 1.0
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Marki
Can you please give us some more details. As a general rule, I do not
recommend mixing "no-clean" and cleaning. The chemistry of "no-clean" is
designed for what it is and *some* such materials will not clean for
love nor money. Others will apparently clean but leave with some process
but may leave dangerous, but invisible, residues. This is a very complex
subject not to be taken lightly.
What is the nature of your problems? What are the products you are
currently using and any others you may have tried. What are the numbers
of boards you wish to clean?
Brian
Marki Sasportas wrote:
>
> Dear Technetters,
>
> Can anybody recommend me on cleaning process/materials for no-clean
> assembled boards.
> We have some problems with flux residues after touch up.
>
> Thanks,
> Marki Sasportas.
>
> ---------------------------------------------------------------------------------
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> information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700 ext.5315
> ---------------------------------------------------------------------------------
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Date: Mon, 22 Apr 2002 08:50:40 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Randy Bock Sr." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Randy Bock Sr." <[log in to unmask]>
Subject: Re: Boards Cleaning
X-To: Marki Sasportas <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="windows-1255"
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Our Repair Department uses Denatured Alcohol or IPA. Seem to work ok for
touch-up issues.
Randy Bock Sr.
Quality Manager
Bryce Office Systems LLC
[log in to unmask]
----- Original Message -----
From: Marki Sasportas <[log in to unmask]>
To: <[log in to unmask]>
Sent: Monday, April 22, 2002 8:23 AM
Subject: [TN] Boards Cleaning
> Dear Technetters,
>
> Can anybody recommend me on cleaning process/materials for no-clean
> assembled boards.
> We have some problems with flux residues after touch up.
>
> Thanks,
> Marki Sasportas.
>
> --------------------------------------------------------------------------
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> --------------------------------------------------------------------------
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>
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Date: Mon, 22 Apr 2002 08:53:33 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Randy Bock Sr." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Randy Bock Sr." <[log in to unmask]>
Subject: Re: Bar Code Standards
X-To: "Bernard, David" <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
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Data content for us is aboard prefix plus S/N. Font size is 10 - 12
normally.
IPC requires it to be readable with the unaided eye.
Randy Bock Sr.
Quality Manager
Bryce Office Systems LLC
[log in to unmask]
----- Original Message -----
From: Bernard, David <[log in to unmask]>
To: <[log in to unmask]>
Sent: Monday, April 22, 2002 4:54 AM
Subject: [TN] Bar Code Standards
> Dear Technetters,
>
> Can anybody tell me if there are any recommended standards for the
> suggested data content within bar codes used on boards?
>
> Thank you,
>
> David
>
> David Bernard
>
> Dage Holdings Plc
> Rabans Lane
> Aylesbury
> Buckinghamshire
> HP19 8RG
> United Kingdom
>
> Tel: 01296 317860 - Direct
> Tel: 01296 317800
> Fax: 01296 435408
> E: [log in to unmask]
> W: www.dage-group.com
>
>
>
> intY (www.inty.com) has automatically scanned this email using Sophos
Anti-Virus
>
> --------------------------------------------------------------------------
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> information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700
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> --------------------------------------------------------------------------
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>
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Date: Mon, 22 Apr 2002 08:56:45 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Golembiewski, Ray" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Golembiewski, Ray" <[log in to unmask]>
Subject: Conveyor belt
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
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I need help finding a new conveyor belt for my reflow oven. I
cannot even bare to list the equipment manufacturers price for this item
because it is so large. If you have any contact information that could
aid me in my search, it would be greatly appreciated. Thanks,
Ray Golembiewski C.I.D.
Manufacturing Test Engineer
Projects Unlimited, Inc.
(937) 918-2200
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Date: Mon, 22 Apr 2002 06:38:20 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
[log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Dewey Whittaker <[log in to unmask]>
Subject: Re: Bar Code Standards
X-To: [log in to unmask]
MIME-Version: 1.0
Content-Type: text/plain
David,
There is,but it depends on a lot of things.Your
market,specifications,customer requirements,end use enviroment,scanning
capabilities and data string recognition requirements.If you want to call me
I will try to help.
Dewey 602-436-2766
> -----Original Message-----
> From: Bernard, David [SMTP:[log in to unmask]]
> Sent: Monday, April 22, 2002 1:54 AM
> To: [log in to unmask]
> Subject: [TN] Bar Code Standards
>
> Dear Technetters,
>
> Can anybody tell me if there are any recommended standards for the
> suggested data content within bar codes used on boards?
>
> Thank you,
>
> David
>
> David Bernard
>
> Dage Holdings Plc
> Rabans Lane
> Aylesbury
> Buckinghamshire
> HP19 8RG
> United Kingdom
>
> Tel: 01296 317860 - Direct
> Tel: 01296 317800
> Fax: 01296 435408
> E: [log in to unmask]
> W: www.dage-group.com
>
>
>
> intY (www.inty.com) has automatically scanned this email using Sophos
> Anti-Virus
>
> --------------------------------------------------------------------------
> -------
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> information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700
> ext.5315
> --------------------------------------------------------------------------
> -------
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=========================================================================
Date: Mon, 22 Apr 2002 10:15:32 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Tempea, Ioan" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Tempea, Ioan" <[log in to unmask]>
Subject: Flip-flop panels
MIME-Version: 1.0
Content-Type: text/plain
Hi Technos,
I want to elaborate on an idea I gto from Technet some time ago. Steve Z was
talking about panelizing boards so that the adjoining boards are flipped one
with respect to the other. One stencil, one setup, one insertion program,
etc.
I am considering implementing it, since we have some piggy backs that would
be well suited for.
What I would really appreciate is your experienced inputs on:
what does this imply at the board house level (cost rise?, special
software?)
what does this imply at the PCB design level
any hints on how to use Fujicam to program the insertion machines
any other considerations
Thanks,
Ioan
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Date: Mon, 22 Apr 2002 10:30:27 EDT
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Gary Ferrari <[log in to unmask]>
Subject: Re: IPC SMT FOOTPRINT DESIGN GUIDLINES VS SUPPLIERS
X-cc: [log in to unmask]
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In a message dated 4/19/2002 12:28:29 PM Eastern Daylight Time,
[log in to unmask] writes:
>
>
> Gary- great idea, IPC needed to expand it list of component land patterns.
>
> Having choices between HDI footprints and relaxed (typical)
> designs is something
> most of us designers have to constantly do on our own. I work
> in an environment
> where 40% of my designs require changes to footprint designs
> (Both IPC and Supplier)
> to accommodate for lack of real-estate. Missing
> footprint option in new IPC-7351 format.
> Descretes need a design showing VIP (via in pad) configuration.
> Most people trying this in design would agree
> via should be located off center from the pad. For power
> inductance reasons we place them on the
> inside edge of pads. So vias are as close to each other as
> practical. I know this could be a reach for IPC
> to join in on this concept, but it is here to stay. HDI design
> require this concept to work. Since the council has both
> fabrication and assembly members they should show how they prefer
> VIP technology.
> Greg Scott
> Cray Inc.
>
>
>
Greg,
Thank you for the input, I will look into it and refer the request to the
committee. I do know that the size of the via is determined by a number of
characteristics of the solder paste used. Perhaps a dialog on appropriate
location may suffice,
Regards,
Gary Ferrari
Executive Director
IPC Designers Council
(860) 350-9300
Fax (413) 771-5386
--part1_ba.24be4ffe.29f57883_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
<HTML><FONT FACE=arial,helvetica><BODY BGCOLOR="#dee9ef"><FONT COLOR="#8000ff" SIZE=2 FAMILY="SCRIPT" FACE="Comic Sans MS" LANG="0"><B><I>In a message dated 4/19/2002 12:28:29 PM Eastern Daylight Time, [log in to unmask] writes:<BR>
<BR>
</FONT><FONT COLOR="#000000" style="BACKGROUND-COLOR: #dee9ef" SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0"></B></I><BR>
<BLOCKQUOTE TYPE=CITE style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px"><BR>
<BR>
Gary- great idea, IPC needed to expand it list of component land patterns. <BR>
Having choices between HDI footprints and relaxed (typical) designs is something <BR>
most of us designers have to constantly do on our own. I work in an environment <BR>
where 40% of my designs require changes to footprint designs (Both IPC and Supplier) <BR>
to accommodate for lack of real-estate. Missing footprint option in new IPC-7351 format. <BR>
Descretes need a design showing VIP (via in pad) configuration. Most people trying this in design would agree <BR>
via should be located off center from the pad. For power inductance reasons we place them on the <BR>
inside edge of pads. So vias are as close to each other as practical. I know this could be a reach for IPC <BR>
to join in on this concept, but it is here to stay. HDI design require this concept to work. Since the council has both fabrication and assembly members they should show how they prefer <BR>
VIP technology. <BR>
Greg Scott <BR>
Cray Inc. <BR>
<BR>
<BR>
</BLOCKQUOTE><BR>
</FONT><FONT COLOR="#8000ff" style="BACKGROUND-COLOR: #dee9ef" SIZE=2 FAMILY="SCRIPT" FACE="Comic Sans MS" LANG="0"><B><I>Greg,<BR>
<BR>
Thank you for the input, I will look into it and refer the request to the committee. I do know that the size of the via is determined by a number of characteristics of the solder paste used. Perhaps a dialog on appropriate location may suffice,<BR>
<BR>
<BR>
<BR>
Regards,<BR>
<BR>
Gary Ferrari<BR>
Executive Director<BR>
IPC Designers Council<BR>
(860) 350-9300<BR>
Fax (413) 771-5386</B></I></FONT></HTML>
--part1_ba.24be4ffe.29f57883_boundary--
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=========================================================================
Date: Mon, 22 Apr 2002 10:04:04 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Beerman, Dennis" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Beerman, Dennis" <[log in to unmask]>
Subject: Re: Flip-flop panels
X-To: "Tempea, Ioan" <[log in to unmask]>
From the board design viewpoint, there is no impact.
If the designer is responsible for creating the panelized artwork to send to
a fab shop, they more than likely have the capability to rotate, copy, or
mirror the image with their current post-processing tools. A board fab shop
would already have the software to create a panelized gerber themselves.
Be sure the fab shop and your assembly house know each others requirements
so that the panel will be something the assembly house can use.
There should be no additional cost incurred, and your fab house is probably
already doing this for other customers.
I believe the assembly house should be able to read in a single image
insertion file and manipulate the data to correspond to the panel layout.
-----Original Message-----
From: Tempea, Ioan [mailto:[log in to unmask]]
Sent: Monday, April 22, 2002 10:16 AM
To: [log in to unmask]
Subject: [TN] Flip-flop panels
Hi Technos,
I want to elaborate on an idea I gto from Technet some time ago. Steve Z was
talking about panelizing boards so that the adjoining boards are flipped one
with respect to the other. One stencil, one setup, one insertion program,
etc.
I am considering implementing it, since we have some piggy backs that would
be well suited for.
What I would really appreciate is your experienced inputs on:
what does this imply at the board house level (cost rise?, special
software?)
what does this imply at the PCB design level
any hints on how to use Fujicam to program the insertion machines
any other considerations
Thanks,
Ioan
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Date: Mon, 22 Apr 2002 10:46:14 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Don Vischulis <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Don Vischulis <[log in to unmask]>
Subject: Re: Conveyor belt
X-To: "Golembiewski, Ray" <[log in to unmask]>
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
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Ray
Are you certain that the whole belt requires replacement? Often replacement
sections can be spliced into the belt to replace damaged ones.
Don Vischulis
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Golembiewski, Ray
Sent: Monday, April 22, 2002 7:57 AM
To: [log in to unmask]
Subject: [TN] Conveyor belt
I need help finding a new conveyor belt for my reflow oven. I
cannot even bare to list the equipment manufacturers price for this item
because it is so large. If you have any contact information that could
aid me in my search, it would be greatly appreciated. Thanks,
Ray Golembiewski C.I.D.
Manufacturing Test Engineer
Projects Unlimited, Inc.
(937) 918-2200
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Date: Mon, 22 Apr 2002 08:52:15 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Jac Kroeker <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Jac Kroeker <[log in to unmask]>
Subject: Re: Flip-flop panels
X-To: "Tempea, Ioan" <[log in to unmask]>
In-Reply-To: <[log in to unmask]
.qc.ca>
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Ioan;
Go ahead and flip-flop. As long as your not a politician.
From a board house point of view - there is no extra cost involved. In
fact, we save on film at the photoplotting stage. The big benefit here is
at the plating stage. It is hard to plate evenly to both sides of the panel
if there is only power/ground on one side and a few signal traces on the
other. Left to our own devices we always flip-flop on our panels.
Jac
www.omnigraph.com
At 10:15 AM 4/22/02 -0400, you wrote:
>Hi Technos,
>
>I want to elaborate on an idea I gto from Technet some time ago. Steve Z was
>talking about panelizing boards so that the adjoining boards are flipped one
>with respect to the other. One stencil, one setup, one insertion program,
>etc.
>
>I am considering implementing it, since we have some piggy backs that would
>be well suited for.
>
>What I would really appreciate is your experienced inputs on:
>what does this imply at the board house level (cost rise?, special
>software?)
>what does this imply at the PCB design level
>any hints on how to use Fujicam to program the insertion machines
>any other considerations
>
>Thanks,
>Ioan
>
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Date: Mon, 22 Apr 2002 12:05:10 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Phil Nutting <[log in to unmask]>
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From: Phil Nutting <[log in to unmask]>
Subject: Chart for similar / dissimilar metals
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During my formative years I came across a neat chart that listed all the =
different metals and their position relative to compatibility with other =
metals. (Re: my post about aluminum vs. copper) Unfortunately I can't =
put my hands on it. Anybody know of a location on the web that might =
have this information?
Thanks in advance,
Phil Nutting
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Date: Mon, 22 Apr 2002 11:24:15 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Jason <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Jason <[log in to unmask]>
Subject: 20 Mhz crystal start-up woes
Has anyone had difficulty with crystal start-up.
Currently we are having problems with a circuit that uses a PIC16C711-
201/P, 2 @ 22pF load caps and a 20 Mhz AT crystal. The configuration is for
fundamental operation.
We are using a high temp screen (85 deg C storage before functional check)
to try and weed out problems but have still found modules not functional at
the production plant.
Sleepy crystals have been discussed but we have experimented with three
different manufactures of crystals we have ruled this out.
One of our action items is to redesign and use 10 Mhz, but right now we
aren't sure of the root cause of failure so there really isn't a guarantee
that this plan will work.
What are some specific design parameters that could be measured to arrive
at the root cause?
Thanks,
Jason
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Date: Mon, 22 Apr 2002 12:48:40 EDT
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Rudy Sedlak <[log in to unmask]>
Subject: Re: Chart for similar / dissimilar metals
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Phil:
Uhh, my guess would be that such a chart would be simplistic and naive, and
that is on the good days. So much depends on the conditions that the metals
are exposed to, as to whether or not they are compatible.
One guys opinion.
Rudy Sedlak
RD Chemical Company
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Date: Mon, 22 Apr 2002 12:08:41 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Jorge Santana <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Jorge Santana <[log in to unmask]>
Subject: Re: Chart for similar / dissimilar metals
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Phil,
I don't known if have the info that you are looking for, but you should try
http://www.webelements.com
Thanks
Jorge Santana
LWT
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Phil Nutting
Sent: Monday, April 22, 2002 11:05 AM
To: [log in to unmask]
Subject: [TN] Chart for similar / dissimilar metals
During my formative years I came across a neat chart that listed all the
different metals and their position relative to compatibility with other
metals. (Re: my post about aluminum vs. copper) Unfortunately I can't put
my hands on it. Anybody know of a location on the web that might have this
information?
Thanks in advance,
Phil Nutting
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Date: Mon, 22 Apr 2002 13:08:22 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"WEEKES, MICHAEL HS-SNS" <[log in to unmask]>
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From: "WEEKES, MICHAEL HS-SNS" <[log in to unmask]>
Subject: lighting and J STD 001
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J STD 001 calls out 1000 lumens/m sq. - this seems awfully bright - is this
for just repair only or for plant lighting in general - I thought 100
lumens was pretty bright.
Mike Weekes
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Date: Mon, 22 Apr 2002 10:13:50 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Trace width to carry high current
X-To: Don Vischulis <[log in to unmask]>
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Dear Technetters,
Can anybody tell me the total trace width required to carry 100 amp for 1 second
between two connections that is onch inch apart. Should the trace(s) better to
be on the outer layers than inner layers to avoid cold solder joints?
Any information is appreciated.
Thanks,
Patrick
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Date: Mon, 22 Apr 2002 10:47:51 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Thorup, John" <[log in to unmask]>
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From: "Thorup, John" <[log in to unmask]>
Subject: Re: Chart for similar / dissimilar metals
X-To: Phil Nutting <[log in to unmask]>
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morning Phil
try www.eaa1000.av.org/technicl/corrosion/galvanic.htm
also, one of the big EMI shielding manufacturers has a chart in their
catalog. don't remember which one
John Thorup
> -----Original Message-----
> From: Phil Nutting [SMTP:[log in to unmask]]
> Sent: Monday, April 22, 2002 9:05 AM
> To: [log in to unmask]
> Subject: [TN] Chart for similar / dissimilar metals
>
> During my formative years I came across a neat chart that listed all the
> different metals and their position relative to compatibility with other
> metals. (Re: my post about aluminum vs. copper) Unfortunately I can't put
> my hands on it. Anybody know of a location on the web that might have
> this information?
>
> Thanks in advance,
>
> Phil Nutting
>
> --------------------------------------------------------------------------
> -------
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Date: Mon, 22 Apr 2002 11:04:59 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Pelkey, Glenn" <[log in to unmask]>
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From: "Pelkey, Glenn" <[log in to unmask]>
Subject: Re: Chart for similar / dissimilar metals
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I have one posted on my wall from Mil-P-55624, page 19. Very easy to
understand with EMF potential and Anodic Index.
Glenn
-----Original Message-----
From: Phil Nutting [mailto:[log in to unmask]]
Sent: Monday, April 22, 2002 9:05 AM
To: [log in to unmask]
Subject: [TN] Chart for similar / dissimilar metals
During my formative years I came across a neat chart that listed all the
different metals and their position relative to compatibility with other
metals. (Re: my post about aluminum vs. copper) Unfortunately I can't put
my hands on it. Anybody know of a location on the web that might have this
information?
Thanks in advance,
Phil Nutting
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<P><FONT SIZE=3D2>I have one posted on my wall from Mil-P-55624, page =
19. Very easy to understand with EMF potential and Anodic =
Index.</FONT>
</P>
<P><FONT SIZE=3D2>Glenn</FONT>
</P>
<P><FONT SIZE=3D2>-----Original Message-----</FONT>
<BR><FONT SIZE=3D2>From: Phil Nutting [<A =
HREF=3D"mailto:[log in to unmask]">mailto:PNutting@KAISERSYSTEMS=
.COM</A>]</FONT>
<BR><FONT SIZE=3D2>Sent: Monday, April 22, 2002 9:05 AM</FONT>
<BR><FONT SIZE=3D2>To: [log in to unmask]</FONT>
<BR><FONT SIZE=3D2>Subject: [TN] Chart for similar / dissimilar =
metals</FONT>
</P>
<BR>
<P><FONT SIZE=3D2>During my formative years I came across a neat chart =
that listed all the different metals and their position relative to =
compatibility with other metals. (Re: my post about aluminum vs. =
copper) Unfortunately I can't put my hands on it. Anybody =
know of a location on the web that might have this =
information?</FONT></P>
<P><FONT SIZE=3D2>Thanks in advance,</FONT>
</P>
<P><FONT SIZE=3D2>Phil Nutting</FONT>
</P>
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Date: Mon, 22 Apr 2002 13:30:38 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
[log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Dave Hillman <[log in to unmask]>
Subject: Re: Chart for similar / dissimilar metals
X-To: [log in to unmask]
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Hi Phil! There is undoubtedly several websites with galvanic tables but
just in case the electrons don't flow here are a couple of "fiber" sources:
Corrosion Engineering, Fontana & Greene, ISBN 0-07-021461-1 or Corrosion,
Vol. 13, ASM Metals Handbook Series, Ninth Ed., ISBN 0-87170-007-7. Good
Luck.
Dave Hillman
Rockwell Collins
[log in to unmask]
Phil Nutting <[log in to unmask]>@ipc.org> on 04/22/2002 11:05:10
AM
Please respond to "TechNet E-Mail Forum." <[log in to unmask]>; Please respond
to Phil Nutting <[log in to unmask]>
Sent by: TechNet <[log in to unmask]>
To: [log in to unmask]
cc:
Subject: [TN] Chart for similar / dissimilar metals
During my formative years I came across a neat chart that listed all the
different metals and their position relative to compatibility with other
metals. (Re: my post about aluminum vs. copper) Unfortunately I can't put
my hands on it. Anybody know of a location on the web that might have this
information?
Thanks in advance,
Phil Nutting
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Date: Mon, 22 Apr 2002 14:32:22 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Keith Calhoun <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Keith Calhoun <[log in to unmask]>
Organization: Sierra Research, an Integrated Defense Technologies company
Subject: Re: Chart for similar / dissimilar metals
X-To: Phil Nutting <[log in to unmask]>
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Phil;
The one that comes to my mind is MIL-F-14072, Table VI, listing
compatible couples for dissimilar metals. This is basically a listing
of metals in order of galvonic potential, starting with gold at one end
with magnesium at the other.
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Date: Mon, 22 Apr 2002 11:50:15 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Crepeau, Phil" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Crepeau, Phil" <[log in to unmask]>
Subject: Re: Chart for similar / dissimilar metals
X-To: [log in to unmask]
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mil-std-889 has this table.
phil
-----Original Message-----
From: Phil Nutting [mailto:[log in to unmask]]
Sent: Monday, April 22, 2002 9:05 AM
To: [log in to unmask]
Subject: [TN] Chart for similar / dissimilar metals
During my formative years I came across a neat chart that listed all the different metals and their position relative to compatibility with other metals. (Re: my post about aluminum vs. copper) Unfortunately I can't put my hands on it. Anybody know of a location on the web that might have this information?
Thanks in advance,
Phil Nutting
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Date: Mon, 22 Apr 2002 15:07:43 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Rob Legg <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Rob Legg <[log in to unmask]>
Subject: Re: Conveyor belt
X-To: "Golembiewski, Ray" <[log in to unmask]>
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ExSelect Engineering in Concord ON has rebuilt, refurbished and replaced
entire drives in WS equipment for years.
Bill Sund can even build from scratch, and regularly did so, when I knew
him. His daughter may have taken over supervision and design of some of the
work, by now.
http://www.exselect.com/
[log in to unmask]
Rob Legg
[log in to unmask]
----- Original Message -----
From: "Golembiewski, Ray" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Monday, April 22, 2002 8:56 AM
Subject: [TN] Conveyor belt
> I need help finding a new conveyor belt for my reflow oven. I
> cannot even bare to list the equipment manufacturers price for this item
> because it is so large. If you have any contact information that could
> aid me in my search, it would be greatly appreciated. Thanks,
>
> Ray Golembiewski C.I.D.
> Manufacturing Test Engineer
> Projects Unlimited, Inc.
> (937) 918-2200
>
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Date: Mon, 22 Apr 2002 15:30:02 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Rob Legg <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Rob Legg <[log in to unmask]>
Subject: Re: 20 Mhz crystal start-up woes
X-To: Jason <[log in to unmask]>
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You'll find extensive coverage on this topic if you research google group
threads on sci.electronics.design.
http://groups.google.com/groups?q=sci.electronics.design&hl=en&btnG=Google+S
earch&meta=
If the problem is just start-up time, this can be increased by splitting the
final capacitor value into two parts connected as a divider between ground
and the chip supply rail. Their transient charge accumulation, at start,
should be set to bias the device linearly, without waitng for the parts to
charge through the feedback biasing resistor.
Gain is improved also, if the downstream C value is larger than the input C
value - of course the net series effective C should be maintained at the
specified value (11pf in your circuit).
If the problem is xtal mortality, degeneration, drift, then make sure you
are not overdriving the thing. a resistor in series with the output gate,
before the first capacitor, absorbs excessive drive power.
general app notes:
http://www.wenzel.com/documents/library.html
http://www.foxonline.com/main_other.htm
http://www.ctscorp.com/reeves/fdefault.htm
----- Original Message -----
From: "Jason" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Monday, April 22, 2002 12:24 PM
Subject: [TN] 20 Mhz crystal start-up woes
> Has anyone had difficulty with crystal start-up.
> Currently we are having problems with a circuit that uses a PIC16C711-
> 201/P, 2 @ 22pF load caps and a 20 Mhz AT crystal. The configuration is
for
> fundamental operation.
>
> We are using a high temp screen (85 deg C storage before functional check)
> to try and weed out problems but have still found modules not functional
at
> the production plant.
> Sleepy crystals have been discussed but we have experimented with three
> different manufactures of crystals we have ruled this out.
> One of our action items is to redesign and use 10 Mhz, but right now we
> aren't sure of the root cause of failure so there really isn't a guarantee
> that this plan will work.
>
> What are some specific design parameters that could be measured to arrive
> at the root cause?
>
> Thanks,
> Jason
>
> --------------------------------------------------------------------------
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Date: Mon, 22 Apr 2002 15:33:03 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Rob Legg <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Rob Legg <[log in to unmask]>
Subject: Re: Trace width to carry high current
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Depends on start temperature repetition rate and failure criteria.
RL
----- Original Message -----
From: <[log in to unmask]>
To: <[log in to unmask]>
Sent: Monday, April 22, 2002 1:13 PM
Subject: [TN] Trace width to carry high current
> Dear Technetters,
>
> Can anybody tell me the total trace width required to carry 100 amp for 1
second
> between two connections that is onch inch apart. Should the trace(s)
better to
> be on the outer layers than inner layers to avoid cold solder joints?
>
> Any information is appreciated.
>
> Thanks,
> Patrick
>
> This e-mail may contain SEL confidential information. The opinions
expressed
> are not necessarily those of SEL. Any unauthorized disclosure,
distribution or
> other use is prohibited. If you received this e-mail in error, please
notify
> the sender, permanently delete it, and destroy any printout. Thank you.
>
> --------------------------------------------------------------------------
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Date: Mon, 22 Apr 2002 15:44:41 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Furrow, Robert Gordon (Bob)" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Furrow, Robert Gordon (Bob)" <[log in to unmask]>
Subject: Removal of Cured Nomenclature Ink
MIME-Version: 1.0
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Hi TechNet,
I have been asked what chemical(s) would be required to remove cured
nomenclature ink (also known as silkscreen) from a bare board without
damaging the board itself. I am assuming it is an epoxy ink, but I do not
know the exact formulation. Any input is appreciated. I should know the
exact formulation of the applied nomenclature ink tomorrow, but thought that
maybe there is a generic answer.
Thanks,
Robert Furrow
Printed Wiring Board Engineer
Supply Chain Networks
Lucent Technologies
978-960-3224 [log in to unmask]
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Date: Mon, 22 Apr 2002 13:01:25 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Trace width to carry high current
X-To: Rob Legg <[log in to unmask]>
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Boundary="0__=QyvZ3HdiTQ4eSAsxSA5n5y7j0MQhF1GahVWrJWelfB1cP4NleldAgYhA"
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Rob,
Thanks for the response.
It's an AC 50-60HZ, at room temperature, one time only, no repetition.
Thanks,
Patrick
Rob Legg <[log in to unmask]> on 04/22/2002 12:33:03 PM
Please respond to "TechNet E-Mail Forum." <[log in to unmask]>; Please respond to
Rob Legg <[log in to unmask]>
To: [log in to unmask]
cc: (bcc: Patrick Lam/SEL)
Subject: Re: [TN] Trace width to carry high current
Depends on start temperature repetition rate and failure criteria.
RL
----- Original Message -----
From: <[log in to unmask]>
To: <[log in to unmask]>
Sent: Monday, April 22, 2002 1:13 PM
Subject: [TN] Trace width to carry high current
> Dear Technetters,
>
> Can anybody tell me the total trace width required to carry 100 amp for 1
second
> between two connections that is onch inch apart. Should the trace(s)
better to
> be on the outer layers than inner layers to avoid cold solder joints?
>
> Any information is appreciated.
>
> Thanks,
> Patrick
>
> This e-mail may contain SEL confidential information. The opinions
expressed
> are not necessarily those of SEL. Any unauthorized disclosure,
distribution or
> other use is prohibited. If you received this e-mail in error, please
notify
> the sender, permanently delete it, and destroy any printout. Thank you.
>
> --------------------------------------------------------------------------
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>
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Date: Mon, 22 Apr 2002 16:18:48 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
tony steinke <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: tony steinke <[log in to unmask]>
Subject: Re: Removal of Cured Nomenclature Ink
MIME-Version: 1.0
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Robert,
If the ink is fully cured it may be next to impossible to remove without
attacking the soldermask. Do you need
to remove the entire silkscreen or just certain areas?
You may be better off contacting your board manufacturer
and have him apply soldermask over the existing silkscreen and re apply the
new rev of the silkscreen that you need. You can contact me offline if you
would like once you get more details.
Tony Steinke
[log in to unmask]
----- Original Message -----
From: "Furrow, Robert Gordon (Bob)" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Monday, April 22, 2002 12:44 PM
Subject: [TN] Removal of Cured Nomenclature Ink
> Hi TechNet,
>
> I have been asked what chemical(s) would be required to remove cured
> nomenclature ink (also known as silkscreen) from a bare board without
> damaging the board itself. I am assuming it is an epoxy ink, but I do not
> know the exact formulation. Any input is appreciated. I should know the
> exact formulation of the applied nomenclature ink tomorrow, but thought
that
> maybe there is a generic answer.
>
> Thanks,
> Robert Furrow
> Printed Wiring Board Engineer
> Supply Chain Networks
> Lucent Technologies
> 978-960-3224 [log in to unmask]
>
> --------------------------------------------------------------------------
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> --------------------------------------------------------------------------
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Date: Mon, 22 Apr 2002 16:32:08 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Sauer, Steven T." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Sauer, Steven T." <[log in to unmask]>
Subject: Re: lighting and J STD 001
X-To: "WEEKES, MICHAEL HS-SNS" <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Good Afternoon Mike,
For the record, there is no lighting requirement in J-STD-001 (the word
should is used in the text). Although the guideline of 1000 lm/m2 seems
high, it is the minimum level of illumination in which operators and
inspectors should be expected to perform their tasks. You may need to check
with your plant safety department and OSHA regulations for other
requirements.
Steve Sauer
Mfg Engineer
Northrop Grumman, Xetron
-----Original Message-----
From: WEEKES, MICHAEL HS-SNS
J STD 001 calls out 1000 lumens/m sq. - this seems awfully bright - is this
for just repair only or for plant lighting in general - I thought 100
lumens was pretty bright.
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Date: Mon, 22 Apr 2002 14:59:30 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Russell Burdick <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Russell Burdick <[log in to unmask]>
Subject: cupric chloride
Mime-Version: 1.0
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Hello TechNet,
I am in need of a cupric chloride solution recipe. The shop I'm now employed
at (Prototron Printed Circuits, Tuscon) uses ammoniacal etchant for both
inners and outers. I will be using the solution to strip/leach the
electroless copper tank each week and wish to reuse the etchant until it is
fully loaded with copper, approx. 25 oz/gal.
Thanks in advance for any help.
Russ Burdick, Process Engineer
Prototron Printed Circuits
ph 520-745-8515
_________________________________________________________________
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Date: Mon, 22 Apr 2002 18:34:08 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Rob Legg <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Rob Legg <[log in to unmask]>
Subject: Re: Trace width to carry high current
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I'm assuming this is a safety ground trace test, and that failure is
represented by an open circuit / visible discoloration/damage or detectable
outgassing.
The test connection interface will contribute to the temperature rise if the
junction is poor.This effect is best reduced by using a soldered connection
at the point of stimulator contact to the circuit under test.
You have also neglected to mention copper weight.
***I will assume 3oz, as this is a test being performed on a power circuit.
***I will also assume that the track is on only one layer, and that the
layer is not buried, although it makes little difference in this case.
In one second, the only effect on temperature rise is the thermal capacity
of the heating element, as determined by it's material's specific heat, the
material's mass and the power being absorbed. If the substrate material is
FR4, the thermal capacity is so low as to have no beneficial effect over
that of the copper alone. Ceramic or filled substrates would contribute to
the effective mass.
***I will assume a permitted temperature rise that exceeds the UL normal
rise limit in non-accessible locations, by a factor of 50%, as this is a
temporary excursion limited by the vaporization temperature of the
***assumed FR4 substrate.
The specific heat of copper is .092cal/gdegC.
The permitted temperature rise from room temperature is
95degC x1.5 = 137 degrees for a hotspot temperature of 160degC.
Maximum permitted energy input will be:
.092 x 137 = 12.6 cal/g
or 4.19 x 12.6 = 52.8 watt.sec/g
or 52watts/gram in the one second time interval.
The power dissipation of the trace is I^2.R.
I=100A
R=K x L x W
K=1.61E-4 for 3oz copper and
L/W is the length/width ratio in 'squares'.
The mass of the trace is equal to .105mm x L x W x 8.89E-3g/mm^3
.105mm is the thickness of 3oz copper
8.89E-3g/mm^3 is the density of copper
Combine the two equations
52.8 = 1.61E-4 x L x (100)^2 / 0.105 x L x W^2 x8.89E-3
Minimum trace width W= 5.76 mm, with the length having no effect.
Note: If the conduction interval exceeds 1sec, the temperature of the track
will continue to rise at the rate of 130degC/sec.
If on the other hand, you have a trace width already laid out, you can use
the same method to figure out what the transient rise will actually be in
one or two seconds.
RL
PS: useful copper track resistance numbers -
Copper Resistance: Rc= r . L/HW r = 1.7241WcmE-6 or
6.786WinchE-7
Tempco Tc= +.039%/°C
R = K L/W
K @ 1oz (H=.0014 or .035mm) = 4.84E-4
@ 2oz (H=.0028 or .070mm) = 2.43E-4
@ 3oz (H=.0042 or .105mm) = 1.61E-4
@ 4oz (H=.0056 or .140mm) = 1.21E-4
@ foil .01 = 6.79E-5
@ foil .02 = 3.39E-5
@ foil .05 = 1.37E-5
@ bar .10 = 6.8E-6
Note: K is traditionally expressed as ohms/square, as L/W of the 'printed'
square is 1.
The resistivity of 1oz copper can therefore be considered as 0.48
milliohms/sq.
1oz PTH .062L .0017H
dia. 0.02 W=0.0613 R=0.48mW
dia. 0.04 W=0.1257 R=0.24mW
dia. 0.06 W=0.1885 R=0.159mW
L/W 2oz 3oz 4oz
1 .243 .16 .121 mW
10 2.43 1.61 1.21 mW
100 24.3 16.1 12.1 mW
----- Original Message -----
From: <[log in to unmask]>
To: "TechNet E-Mail Forum." <[log in to unmask]>; "Rob Legg" <[log in to unmask]>
Sent: Monday, April 22, 2002 4:01 PM
Subject: Re: [TN] Trace width to carry high current
>
>
> Rob,
>
> Thanks for the response.
> It's an AC 50-60HZ, at room temperature, one time only, no repetition.
>
> Thanks,
> Patrick
>
>
>
>
>
> Rob Legg <[log in to unmask]> on 04/22/2002 12:33:03 PM
>
> Please respond to "TechNet E-Mail Forum." <[log in to unmask]>; Please
respond to
> Rob Legg <[log in to unmask]>
>
> To: [log in to unmask]
> cc: (bcc: Patrick Lam/SEL)
> Subject: Re: [TN] Trace width to carry high current
>
>
>
> Depends on start temperature repetition rate and failure criteria.
>
> RL
>
> ----- Original Message -----
> From: <[log in to unmask]>
> To: <[log in to unmask]>
> Sent: Monday, April 22, 2002 1:13 PM
> Subject: [TN] Trace width to carry high current
>
>
> > Dear Technetters,
> >
> > Can anybody tell me the total trace width required to carry 100 amp for
1
> second
> > between two connections that is onch inch apart. Should the trace(s)
> better to
> > be on the outer layers than inner layers to avoid cold solder joints?
> >
> > Any information is appreciated.
> >
> > Thanks,
> > Patrick
> >
> > This e-mail may contain SEL confidential information. The opinions
> expressed
> > are not necessarily those of SEL. Any unauthorized disclosure,
> distribution or
> > other use is prohibited. If you received this e-mail in error, please
> notify
> > the sender, permanently delete it, and destroy any printout. Thank you.
> >
>
> --------------------------------------------------------------------------
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Date: Mon, 22 Apr 2002 16:39:29 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Trace width to carry high current
X-To: Rob Legg <[log in to unmask]>
Mime-Version: 1.0
Content-type: text/plain; charset=us-ascii
Rob,
You are good!!! Thanks also for the prompt response. The equations are great.
Your help is highly appreciated.
Patrick
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Date: Mon, 22 Apr 2002 20:49:19 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Jack Bryant <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Jack Bryant <[log in to unmask]>
Subject: Re: Bar Code Standards
X-To: "Bernard, David" <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
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David,
Within the general IPC guideline and generally speaking, "human readable"
and "barcode", assembly no., date code, unique serial no. and CM identifier
will usually suffice the basic needs in a small footprint. Having worked for
a CM designing barcode labels for assembly processes, customer products, and
internal procedures the labels are personal to each customer with creative
ways of building intelligence into the limited barcode encrypted data. Don't
know of a standard barcode format either. Some of the common barcodes I've
seen would be the UPC code with check digit commonly seen on consumer
products, code 39, and code 128 to name a few, code 128 being the most
flexible. However, now with the introduction of the 2D barcode labels short
stories can be encrypted into barcodes that are only 1" wide and 1" long and
hold complete paragraphs of data never before considered as part of
sub-assembly labeling information. Barcode labels don't have to be just
black and white lines anymore.
AJB
----- Original Message -----
From: "Bernard, David" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Monday, April 22, 2002 4:54 AM
Subject: [TN] Bar Code Standards
> Dear Technetters,
>
> Can anybody tell me if there are any recommended standards for the
> suggested data content within bar codes used on boards?
>
> Thank you,
>
> David
>
> David Bernard
>
> Dage Holdings Plc
> Rabans Lane
> Aylesbury
> Buckinghamshire
> HP19 8RG
> United Kingdom
>
> Tel: 01296 317860 - Direct
> Tel: 01296 317800
> Fax: 01296 435408
> E: [log in to unmask]
> W: www.dage-group.com
>
>
>
> intY (www.inty.com) has automatically scanned this email using Sophos
Anti-Virus
>
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>
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Date: Mon, 22 Apr 2002 21:06:47 EDT
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Secondary reflow over wave...
MIME-Version: 1.0
Content-Type: text/plain; charset="US-ASCII"
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Hi All!
Got a situation here that I think is secondary reflow...
Have a board here that has some J-leaded DRAM that in functional test, they
can get the board to pass test by putting some pressure on top of some of the
40-pin J-leaded DRAM's that are causing them to fail...
Out of SMT things look fine, but I have observed some boards that have
failed, show an unusual solder joint appearance after wave. The board is
"swiss-cheesed" with vias, and none of them are tented. Every pad has a via,
they alternate, some have .050" traces to the pad, some have .020" traces to
the pad.
Where we're seeing problems is where there is a bank of them (like a grid of
2 by 8 of them layed-out side by side).
I'm thinking secondary reflow because of the open vias...or could be CTE
mis-match between the part and the board. It's a .062" FR4 board, with fairly
large 40-pin SOJ's, could be experiencing some hellacious mismatch, no? The
gull-wing parts we don't see the problem, even though the via placement is
the same standard as with the J-leaded parts...J-leads aren't as compliant?
Gonna hook-up the mole tomorrow, attaching it to one of the J-leaded parts to
learn what it is seeing...will tell me a lot...
Just wondering if anybody else has run into this before...
-Steve Gregory-
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Date: Tue, 23 Apr 2002 09:08:53 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Trace width to carry high current
X-To: [log in to unmask]
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
What copper weight are you using, Patrick?
Peter
[log in to unmask] 23/04/2002 01:13 AM
Sent by: TechNet <[log in to unmask]>
Please respond to "TechNet E-Mail Forum."; Please respond to Patrick_Lam
To: [log in to unmask]
cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST Aero/ST Group)
Subject: [TN] Trace width to carry high current
Dear Technetters,
Can anybody tell me the total trace width required to carry 100 amp for 1
second
between two connections that is onch inch apart. Should the trace(s) better
to
be on the outer layers than inner layers to avoid cold solder joints?
Any information is appreciated.
Thanks,
Patrick
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Date: Mon, 22 Apr 2002 21:41:39 EDT
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Rudy Sedlak <[log in to unmask]>
Subject: Re: cupric chloride
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="part1_4b.1c1fd0ed.29f615d3_boundary"
--part1_4b.1c1fd0ed.29f615d3_boundary
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
Russ:
Great idea in theory, probably not what you want in actual practice.
Why not give me a call tomorrow, Tuesday AM, and I will give you the formula,
and then explain to you why you do not want to use it.
Rudy Sedlak
RD Chemical Company
650-962-8004
--part1_4b.1c1fd0ed.29f615d3_boundary
Content-Type: text/html; charset="US-ASCII"
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<HTML><FONT FACE=arial,helvetica><FONT SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0">Russ:<BR>
<BR>
Great idea in theory, probably not what you want in actual practice.<BR>
<BR>
Why not give me a call tomorrow, Tuesday AM, and I will give you the formula, and then explain to you why you do not want to use it.<BR>
<BR>
Rudy Sedlak<BR>
RD Chemical Company<BR>
650-962-8004</FONT></HTML>
--part1_4b.1c1fd0ed.29f615d3_boundary--
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Date: Mon, 22 Apr 2002 21:25:43 -0500
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: "Robert B. Denbo" <[log in to unmask]>
Subject: Re: Flip-flop panels
X-To: "Tempea, Ioan" <[log in to unmask]>
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
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Ioan:
You are not asking for anything that unusual. Back in the days of screened
thermal masks, we used to set up panels with flipped images so we only had
to produce one screen. Prior to using original films for imaging we would
make two diazo copies of the film and start production. As an added benefit
designs that you have described come out with balanced plating areas front -
to - back. We already flip parts in the production panel on designs that are
highly imbalanced. There is no additional charge for arrays like this. Board
shops have been doing this for years.
Robert B. Denbo
Engineering Manager
Midwest Printed Circuit Services, Inc.
http://www.midwestpcb.com
mailto:[log in to unmask]
847.740.4120
847.740.4187 Fax
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Tempea, Ioan
Sent: Monday, April 22, 2002 9:16 AM
To: [log in to unmask]
Subject: [TN] Flip-flop panels
Hi Technos,
I want to elaborate on an idea I gto from Technet some time ago. Steve Z was
talking about panelizing boards so that the adjoining boards are flipped one
with respect to the other. One stencil, one setup, one insertion program,
etc.
I am considering implementing it, since we have some piggy backs that would
be well suited for.
What I would really appreciate is your experienced inputs on:
what does this imply at the board house level (cost rise?, special
software?)
what does this imply at the PCB design level
any hints on how to use Fujicam to program the insertion machines
any other considerations
Thanks,
Ioan
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Date: Tue, 23 Apr 2002 13:20:00 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Wanted: AM79C970AVIW
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
I'm getting kinda desperate here, trying to find someone - anyone - who can
come up with 100 pcs of AMD's old Ethernet Controller part AM79C970AVIW. By
any chance, does any of you know of a quiet corner where some of these
parts may still survive unclaimed and unwanted, so I can adopt them (for a
consideration, of course)?
I've spent all morning and my lunch break hunting through web sites using
every search word I can think of, only to draw a complete blank. Even if
there aren't 100 pcs in one place, I'll take them piece-meal.
MTIA
Peter
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Date: Tue, 23 Apr 2002 08:18:13 +0100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Eric Dawson <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Eric Dawson <[log in to unmask]>
Subject: Re: Secondary reflow over wave...
MIME-Version: 1.0
Content-Type: text/plain
Hi Steve,
I have not seen this on J leads but definitely under bga.s.
I measured up to 200C under a topside bga* when it went over the wave, so I
reduced the preheat (it was too hot anyway) and used peelable solder mask
under the bga vias. This did the trick but was time consuming.
I was fortunate that I was able to convert the process flow to double side
reflow with pin in hole.
Hope this helps.
Regards
Eric Dawson
* An image has just formed in my mind of a bottom side bga going over a
wave. I think I need to lie down in a darkened room.
> -----Original Message-----
> From: [log in to unmask] [SMTP:[log in to unmask]]
> Sent: Tuesday, April 23, 2002 2:07 AM
> To: [log in to unmask]
> Subject: [TN] Secondary reflow over wave...
>
> Hi All!
>
> Got a situation here that I think is secondary reflow...
>
> Have a board here that has some J-leaded DRAM that in functional test,
> they
> can get the board to pass test by putting some pressure on top of some of
> the
> 40-pin J-leaded DRAM's that are causing them to fail...
>
> Out of SMT things look fine, but I have observed some boards that have
> failed, show an unusual solder joint appearance after wave. The board is
> "swiss-cheesed" with vias, and none of them are tented. Every pad has a
> via,
> they alternate, some have .050" traces to the pad, some have .020" traces
> to
> the pad.
>
> Where we're seeing problems is where there is a bank of them (like a grid
> of
> 2 by 8 of them layed-out side by side).
>
> I'm thinking secondary reflow because of the open vias...or could be CTE
> mis-match between the part and the board. It's a .062" FR4 board, with
> fairly
> large 40-pin SOJ's, could be experiencing some hellacious mismatch, no?
> The
> gull-wing parts we don't see the problem, even though the via placement is
> the same standard as with the J-leaded parts...J-leads aren't as
> compliant?
>
> Gonna hook-up the mole tomorrow, attaching it to one of the J-leaded parts
> to
> learn what it is seeing...will tell me a lot...
>
> Just wondering if anybody else has run into this before...
>
> -Steve Gregory-
>
> --------------------------------------------------------------------------
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Date: Tue, 23 Apr 2002 06:14:13 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Dieselberg, Ron" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Dieselberg, Ron" <[log in to unmask]>
Subject: Re: 20 Mhz crystal start-up woes
X-To: Jason <[log in to unmask]>
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Check the feedback circuit. Maybe the crystal is not getting enough
excitation to kick start it.
Ron Dieselberg
Trainer/Auditor
CMC ELECTRONICS
CINCINNATI
[log in to unmask]
-----Original Message-----
From: Jason [mailto:[log in to unmask]]
Sent: Monday, April 22, 2002 12:24 PM
To: [log in to unmask]
Subject: [TN] 20 Mhz crystal start-up woes
Has anyone had difficulty with crystal start-up.
Currently we are having problems with a circuit that uses a
PIC16C711-
201/P, 2 @ 22pF load caps and a 20 Mhz AT crystal. The
configuration is for
fundamental operation.
We are using a high temp screen (85 deg C storage before
functional check)
to try and weed out problems but have still found modules
not functional at
the production plant.
Sleepy crystals have been discussed but we have experimented
with three
different manufactures of crystals we have ruled this out.
One of our action items is to redesign and use 10 Mhz, but
right now we
aren't sure of the root cause of failure so there really
isn't a guarantee
that this plan will work.
What are some specific design parameters that could be
measured to arrive
at the root cause?
Thanks,
Jason
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<TITLE>RE: [TN] 20 Mhz crystal start-up woes</TITLE>
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<P><FONT SIZE=3D2 FACE=3D"Arial">Check the feedback circuit. Maybe the =
crystal is not getting enough excitation to kick start it.</FONT>
</P>
<P><FONT SIZE=3D2 FACE=3D"Courier New">Ron Dieselberg</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Courier New">Trainer/Auditor</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Courier New">CMC ELECTRONICS</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Courier New">CINCINNATI</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Courier New">[log in to unmask]</FONT>
</P>
<UL><UL>
<P><A NAME=3D"_MailData"><FONT SIZE=3D2 FACE=3D"Arial">-----Original =
Message-----</FONT></A>
<BR><B><FONT SIZE=3D2 FACE=3D"Arial">From: Jason [<A =
HREF=3D"mailto:[log in to unmask]">mailto:jlarson@PACIFICINSIGHT=
.COM</A>]</FONT></B>
<BR><B><FONT SIZE=3D2 FACE=3D"Arial">Sent: </FONT></B> <FONT =
SIZE=3D2 FACE=3D"Arial">Monday, April 22, 2002 12:24 PM</FONT>
<BR><B><FONT SIZE=3D2 =
FACE=3D"Arial">To: </FONT></B> <FONT SIZE=3D2 =
FACE=3D"Arial">[log in to unmask]</FONT>
<BR><B><FONT SIZE=3D2 =
FACE=3D"Arial">Subject: </FONT>=
</B> <FONT SIZE=3D2 FACE=3D"Arial">[TN] 20 Mhz crystal start-up =
woes</FONT>
</P>
<P><FONT SIZE=3D2 FACE=3D"Arial">Has anyone had difficulty with crystal =
start-up.</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">Currently we are having problems with =
a circuit that uses a PIC16C711-</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">201/P, 2 @ 22pF load caps and a 20 =
Mhz AT crystal. The configuration is for</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">fundamental operation.</FONT>
</P>
<P><FONT SIZE=3D2 FACE=3D"Arial">We are using a high temp screen (85 =
deg C storage before functional check)</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">to try and weed out problems but have =
still found modules not functional at</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">the production plant.</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">Sleepy crystals have been discussed =
but we have experimented with three</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">different manufactures of crystals we =
have ruled this out.</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">One of our action items is to =
redesign and use 10 Mhz, but right now we</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">aren't sure of the root cause of =
failure so there really isn't a guarantee</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">that this plan will work.</FONT>
</P>
<P><FONT SIZE=3D2 FACE=3D"Arial">What are some specific design =
parameters that could be measured to arrive</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">at the root cause?</FONT>
</P>
<P><FONT SIZE=3D2 FACE=3D"Arial">Thanks,</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">Jason</FONT>
</P>
<P><FONT SIZE=3D2 =
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Date: Tue, 23 Apr 2002 07:37:17 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Randy Bock Sr." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Randy Bock Sr." <[log in to unmask]>
Subject: Re: Bar Code Standards
X-To: Jack Bryant <[log in to unmask]>
MIME-Version: 1.0
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We use bar codes on our boards and have allot of trouble with defining some
sort of specification for it. Info will help, thanks..
----- Original Message -----
From: Jack Bryant <[log in to unmask]>
To: <[log in to unmask]>
Sent: Monday, April 22, 2002 8:49 PM
Subject: Re: [TN] Bar Code Standards
> David,
>
> Within the general IPC guideline and generally speaking, "human readable"
> and "barcode", assembly no., date code, unique serial no. and CM
identifier
> will usually suffice the basic needs in a small footprint. Having worked
for
> a CM designing barcode labels for assembly processes, customer products,
and
> internal procedures the labels are personal to each customer with creative
> ways of building intelligence into the limited barcode encrypted data.
Don't
> know of a standard barcode format either. Some of the common barcodes I've
> seen would be the UPC code with check digit commonly seen on consumer
> products, code 39, and code 128 to name a few, code 128 being the most
> flexible. However, now with the introduction of the 2D barcode labels
short
> stories can be encrypted into barcodes that are only 1" wide and 1" long
and
> hold complete paragraphs of data never before considered as part of
> sub-assembly labeling information. Barcode labels don't have to be just
> black and white lines anymore.
>
> AJB
>
>
>
>
> ----- Original Message -----
> From: "Bernard, David" <[log in to unmask]>
> To: <[log in to unmask]>
> Sent: Monday, April 22, 2002 4:54 AM
> Subject: [TN] Bar Code Standards
>
>
> > Dear Technetters,
> >
> > Can anybody tell me if there are any recommended standards for the
> > suggested data content within bar codes used on boards?
> >
> > Thank you,
> >
> > David
> >
> > David Bernard
> >
> > Dage Holdings Plc
> > Rabans Lane
> > Aylesbury
> > Buckinghamshire
> > HP19 8RG
> > United Kingdom
> >
> > Tel: 01296 317860 - Direct
> > Tel: 01296 317800
> > Fax: 01296 435408
> > E: [log in to unmask]
> > W: www.dage-group.com
> >
> >
> >
> > intY (www.inty.com) has automatically scanned this email using Sophos
> Anti-Virus
> >
>
> --------------------------------------------------------------------------
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> > information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700
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>
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> >
>
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Date: Tue, 23 Apr 2002 07:44:29 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Guy Ramsey <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Guy Ramsey <[log in to unmask]>
Subject: Re: 20 Mhz crystal start-up woes
X-To: Jason <[log in to unmask]>
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
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I have seen crystals damaged by overdriving during in-circuit test (bad
programing).
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Jason
> Sent: Monday, April 22, 2002 12:24 PM
> To: [log in to unmask]
> Subject: [TN] 20 Mhz crystal start-up woes
>
>
> Has anyone had difficulty with crystal start-up.
> Currently we are having problems with a circuit that uses a PIC16C711-
> 201/P, 2 @ 22pF load caps and a 20 Mhz AT crystal. The
> configuration is for
> fundamental operation.
>
> We are using a high temp screen (85 deg C storage before functional check)
> to try and weed out problems but have still found modules not
> functional at
> the production plant.
> Sleepy crystals have been discussed but we have experimented with three
> different manufactures of crystals we have ruled this out.
> One of our action items is to redesign and use 10 Mhz, but right now we
> aren't sure of the root cause of failure so there really isn't a guarantee
> that this plan will work.
>
> What are some specific design parameters that could be measured to arrive
> at the root cause?
>
> Thanks,
> Jason
>
> ------------------------------------------------------------------
> ---------------
> Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
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>
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Date: Tue, 23 Apr 2002 07:54:48 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Bev Christian <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Bev Christian <[log in to unmask]>
Subject: Re: Secondary reflow over wave...
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Steve,
1) Do the vias go all the way through the board?
2) Are they connected to a massive ground plane?
3) Any way to test the parts BEFORE wave soldering?
4) I wonder if the parts are experiencing a latent dewetting
regards,
Bev Christian
Research in Motion
-----Original Message-----
From: [log in to unmask] [mailto:[log in to unmask]]
Sent: April 22, 2002 9:07 PM
To: [log in to unmask]
Subject: [TN] Secondary reflow over wave...
Hi All!
Got a situation here that I think is secondary reflow...
Have a board here that has some J-leaded DRAM that in functional test, they
can get the board to pass test by putting some pressure on top of some of
the
40-pin J-leaded DRAM's that are causing them to fail...
Out of SMT things look fine, but I have observed some boards that have
failed, show an unusual solder joint appearance after wave. The board is
"swiss-cheesed" with vias, and none of them are tented. Every pad has a via,
they alternate, some have .050" traces to the pad, some have .020" traces to
the pad.
Where we're seeing problems is where there is a bank of them (like a grid of
2 by 8 of them layed-out side by side).
I'm thinking secondary reflow because of the open vias...or could be CTE
mis-match between the part and the board. It's a .062" FR4 board, with
fairly
large 40-pin SOJ's, could be experiencing some hellacious mismatch, no? The
gull-wing parts we don't see the problem, even though the via placement is
the same standard as with the J-leaded parts...J-leads aren't as compliant?
Gonna hook-up the mole tomorrow, attaching it to one of the J-leaded parts
to
learn what it is seeing...will tell me a lot...
Just wondering if anybody else has run into this before...
-Steve Gregory-
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Date: Tue, 23 Apr 2002 15:36:43 +0300
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Brian Ellis <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Brian Ellis <[log in to unmask]>
Subject: Re: 20 Mhz crystal start-up woes
X-To: Jason <[log in to unmask]>
MIME-Version: 1.0
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Jason
Are you using ultrasonic cleaning? This is a sure way of buggering up
quartz crystals.
Brian
Jason wrote:
>
> Has anyone had difficulty with crystal start-up.
> Currently we are having problems with a circuit that uses a PIC16C711-
> 201/P, 2 @ 22pF load caps and a 20 Mhz AT crystal. The configuration is for
> fundamental operation.
>
> We are using a high temp screen (85 deg C storage before functional check)
> to try and weed out problems but have still found modules not functional at
> the production plant.
> Sleepy crystals have been discussed but we have experimented with three
> different manufactures of crystals we have ruled this out.
> One of our action items is to redesign and use 10 Mhz, but right now we
> aren't sure of the root cause of failure so there really isn't a guarantee
> that this plan will work.
>
> What are some specific design parameters that could be measured to arrive
> at the root cause?
>
> Thanks,
> Jason
>
> ---------------------------------------------------------------------------------
> Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
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> ---------------------------------------------------------------------------------
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Date: Tue, 23 Apr 2002 09:13:20 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Tempea, Ioan" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Tempea, Ioan" <[log in to unmask]>
Subject: Flip-flop panels... thanks
MIME-Version: 1.0
Content-Type: text/plain
Big thanks to all that answered, this should give me enough ammo to pass the
idea to the PCB designers.
Regards,
Ioan
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Date: Tue, 23 Apr 2002 09:18:12 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Guy Ramsey <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Guy Ramsey <[log in to unmask]>
Subject: Re: Secondary reflow over wave...
X-To: Bev Christian <[log in to unmask]>
In-Reply-To: <[log in to unmask]>
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What is latent dewetting?
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Bev Christian
> Sent: Tuesday, April 23, 2002 7:55 AM
> To: [log in to unmask]
> Subject: Re: [TN] Secondary reflow over wave...
>
>
> Steve,
> 1) Do the vias go all the way through the board?
> 2) Are they connected to a massive ground plane?
> 3) Any way to test the parts BEFORE wave soldering?
> 4) I wonder if the parts are experiencing a latent dewetting
>
> regards,
> Bev Christian
> Research in Motion
>
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Date: Tue, 23 Apr 2002 06:19:06 -0700
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Ed Popielarski <[log in to unmask]>
Subject: Re: Conveyor Belt
Ray,
Take a peek at www.wirebelt.com
I think this is what you are looking for.
Regards,
Ed Popielarski
QTA Machine
10 Mc Laren, Ste D
Irvine, Ca. 92618
Ph: 949-581-6601
Fx: 949-581-2448
Cl: 949-337-2578
WWW.QTA.NET
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Date: Tue, 23 Apr 2002 07:03:49 -0700
Reply-To: David Hoover <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: David Hoover <[log in to unmask]>
Subject: Looking for Dwayne Kincade
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Anyone know where this guy is?
Is he still somewhere in the midwest?
Dave Hoover
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Date: Tue, 23 Apr 2002 09:35:11 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Jorge Santana <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Jorge Santana <[log in to unmask]>
Subject: Re: Secondary reflow over wave...
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Steve
We have seen this on a SOIC that has coplanarity issue on the leads and
the problem was caught at wave solder when the part reflowed at top side of
the board leaving one open junction at the lead.
I have seen this also at BGA and we used Kapton tape to mask.
Thanks
Jorge Santana
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of [log in to unmask]
Sent: Monday, April 22, 2002 8:07 PM
To: [log in to unmask]
Subject: [TN] Secondary reflow over wave...
Hi All!
Got a situation here that I think is secondary reflow...
Have a board here that has some J-leaded DRAM that in functional test, they
can get the board to pass test by putting some pressure on top of some of
the
40-pin J-leaded DRAM's that are causing them to fail...
Out of SMT things look fine, but I have observed some boards that have
failed, show an unusual solder joint appearance after wave. The board is
"swiss-cheesed" with vias, and none of them are tented. Every pad has a via,
they alternate, some have .050" traces to the pad, some have .020" traces to
the pad.
Where we're seeing problems is where there is a bank of them (like a grid of
2 by 8 of them layed-out side by side).
I'm thinking secondary reflow because of the open vias...or could be CTE
mis-match between the part and the board. It's a .062" FR4 board, with
fairly
large 40-pin SOJ's, could be experiencing some hellacious mismatch, no? The
gull-wing parts we don't see the problem, even though the via placement is
the same standard as with the J-leaded parts...J-leads aren't as compliant?
Gonna hook-up the mole tomorrow, attaching it to one of the J-leaded parts
to
learn what it is seeing...will tell me a lot...
Just wondering if anybody else has run into this before...
-Steve Gregory-
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Date: Tue, 23 Apr 2002 07:31:07 -0700
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Ahne Oosterhof <[log in to unmask]>
Subject: Re: Trace width to carry high current
X-To: Rob Legg <[log in to unmask]>
In-Reply-To: <020501c1ea4d$d92449e0$6332fea9@twitty>
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Now that is an answer, full of information. And rather than asking for more
details before giving any answer at all you indicate what the missing
details are and fill them in with appropriate assumptions, allowing the
questioner to replace them with details fitting his situation.
Such responses make reading this forum more fun.
Thanks,
Ahne.
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of Rob Legg
Sent: Monday, April 22, 2002 15:34
To: [log in to unmask]
Subject: Re: [TN] Trace width to carry high current
I'm assuming this is a safety ground trace test, and that failure is
represented by an open circuit / visible discoloration/damage or detectable
outgassing.
The test connection interface will contribute to the temperature rise if the
junction is poor.This effect is best reduced by using a soldered connection
at the point of stimulator contact to the circuit under test.
You have also neglected to mention copper weight.
***I will assume 3oz, as this is a test being performed on a power circuit.
***I will also assume that the track is on only one layer, and that the
layer is not buried, although it makes little difference in this case.
In one second, the only effect on temperature rise is the thermal capacity
of the heating element, as determined by it's material's specific heat, the
material's mass and the power being absorbed. If the substrate material is
FR4, the thermal capacity is so low as to have no beneficial effect over
that of the copper alone. Ceramic or filled substrates would contribute to
the effective mass.
***I will assume a permitted temperature rise that exceeds the UL normal
rise limit in non-accessible locations, by a factor of 50%, as this is a
temporary excursion limited by the vaporization temperature of the
***assumed FR4 substrate.
The specific heat of copper is .092cal/gdegC.
The permitted temperature rise from room temperature is
95degC x1.5 = 137 degrees for a hotspot temperature of 160degC.
Maximum permitted energy input will be:
.092 x 137 = 12.6 cal/g
or 4.19 x 12.6 = 52.8 watt.sec/g
or 52watts/gram in the one second time interval.
The power dissipation of the trace is I^2.R.
I=100A
R=K x L x W
K=1.61E-4 for 3oz copper and
L/W is the length/width ratio in 'squares'.
The mass of the trace is equal to .105mm x L x W x 8.89E-3g/mm^3
.105mm is the thickness of 3oz copper
8.89E-3g/mm^3 is the density of copper
Combine the two equations
52.8 = 1.61E-4 x L x (100)^2 / 0.105 x L x W^2 x8.89E-3
Minimum trace width W= 5.76 mm, with the length having no effect.
Note: If the conduction interval exceeds 1sec, the temperature of the track
will continue to rise at the rate of 130degC/sec.
If on the other hand, you have a trace width already laid out, you can use
the same method to figure out what the transient rise will actually be in
one or two seconds.
RL
PS: useful copper track resistance numbers -
Copper Resistance: Rc= r . L/HW r = 1.7241WcmE-6 or
6.786WinchE-7
Tempco Tc= +.039%/°C
R = K L/W
K @ 1oz (H=.0014 or .035mm) = 4.84E-4
@ 2oz (H=.0028 or .070mm) = 2.43E-4
@ 3oz (H=.0042 or .105mm) = 1.61E-4
@ 4oz (H=.0056 or .140mm) = 1.21E-4
@ foil .01 = 6.79E-5
@ foil .02 = 3.39E-5
@ foil .05 = 1.37E-5
@ bar .10 = 6.8E-6
Note: K is traditionally expressed as ohms/square, as L/W of the 'printed'
square is 1.
The resistivity of 1oz copper can therefore be considered as 0.48
milliohms/sq.
1oz PTH .062L .0017H
dia. 0.02 W=0.0613 R=0.48mW
dia. 0.04 W=0.1257 R=0.24mW
dia. 0.06 W=0.1885 R=0.159mW
L/W 2oz 3oz 4oz
1 .243 .16 .121 mW
10 2.43 1.61 1.21 mW
100 24.3 16.1 12.1 mW
----- Original Message -----
From: <[log in to unmask]>
To: "TechNet E-Mail Forum." <[log in to unmask]>; "Rob Legg" <[log in to unmask]>
Sent: Monday, April 22, 2002 4:01 PM
Subject: Re: [TN] Trace width to carry high current
>
>
> Rob,
>
> Thanks for the response.
> It's an AC 50-60HZ, at room temperature, one time only, no repetition.
>
> Thanks,
> Patrick
>
>
>
>
>
> Rob Legg <[log in to unmask]> on 04/22/2002 12:33:03 PM
>
> Please respond to "TechNet E-Mail Forum." <[log in to unmask]>; Please
respond to
> Rob Legg <[log in to unmask]>
>
> To: [log in to unmask]
> cc: (bcc: Patrick Lam/SEL)
> Subject: Re: [TN] Trace width to carry high current
>
>
>
> Depends on start temperature repetition rate and failure criteria.
>
> RL
>
> ----- Original Message -----
> From: <[log in to unmask]>
> To: <[log in to unmask]>
> Sent: Monday, April 22, 2002 1:13 PM
> Subject: [TN] Trace width to carry high current
>
>
> > Dear Technetters,
> >
> > Can anybody tell me the total trace width required to carry 100 amp for
1
> second
> > between two connections that is onch inch apart. Should the trace(s)
> better to
> > be on the outer layers than inner layers to avoid cold solder joints?
> >
> > Any information is appreciated.
> >
> > Thanks,
> > Patrick
> >
> > This e-mail may contain SEL confidential information. The opinions
> expressed
> > are not necessarily those of SEL. Any unauthorized disclosure,
> distribution or
> > other use is prohibited. If you received this e-mail in error, please
> notify
> > the sender, permanently delete it, and destroy any printout. Thank you.
> >
>
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Date: Tue, 23 Apr 2002 15:48:09 +0100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Hinners Hans M Civ WRALC/LUGE <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Hinners Hans M Civ WRALC/LUGE <[log in to unmask]>
Subject: Re: IPC-A-610 has been DoD Adopted !
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Thanks Jack,
That's welcome news indeed.
Hans
-----Original Message-----
From: Jack Crawford [mailto:[log in to unmask]]
Sent: Saturday, April 13, 2002 5:30 PM
To: [log in to unmask]
Subject: [TN] IPC-A-610 has been DoD Adopted !
IPC-A-610 Acceptability of Electronic Assemblies now has the same DoD
adoption status as another industry standard IPC/EIA J-STD-001C Requirements
for Soldered Electrical and Electronic Assemblies, and the companion
IPC-HDBK-001 w/Amendment 1 Handbook and Guide to Supplement J-STD-001
(Includes J-STD-001B to C Comparison).
I downloaded the adoption notice from the DODSSP QuickSearch Assist website
http://astimage.daps.dla.mil/quicksearch/
<http://astimage.daps.dla.mil/quicksearch/> . This is an "open" site and
anyone can download the notice. Give me a couple of days to work through the
process and I'll also get the adoption notice downloadable from the
IPC-A-610C description page in the online bookstore www.ipc.org/bookstore
<http://www.ipc.org/bookstore> .
Cordially
Jack
Text of the announcement is copied below:
ADOPTION NOTICE
IPC-A610, "Acceptability of Electronic Assemblies", was adopted on 12-FEB-02
for use by the Department of Defense (DoD). Proposed changes by DoD
activities must be submitted to the DoD Adopting Activity: Commander, US
Army Tank-Automotive and Armaments Command, ATTN: AMSTA-TR-E/IE, Warren, MI
48397-5000. Copies of this document may be purchased from the The Institute
for Interconnecting and Packaging Electronic Circuits, 2215 Sanders Rd,
Suite 200 South, Northbrook, IL 60062.
http://www.ipc.org/ <http://www.ipc.org/>
------_=_NextPart_001_01C1EAD5.E2EB25DD
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charset="iso-8859-1"
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=iso-8859-1">
<META content="MSHTML 6.00.2712.300" name=GENERATOR></HEAD>
<BODY style="MARGIN-TOP: 2px; FONT: 8pt MS Sans Serif; MARGIN-LEFT: 2px">
<DIV><SPAN class=040434714-23042002><FONT size=1> Thanks
Jack,</FONT></SPAN></DIV>
<DIV><SPAN class=040434714-23042002><FONT size=1></FONT></SPAN> </DIV>
<DIV><SPAN class=040434714-23042002><FONT size=1>That's welcome news
indeed.</FONT></SPAN></DIV>
<DIV><SPAN class=040434714-23042002><FONT size=1></FONT></SPAN> </DIV>
<DIV><SPAN class=040434714-23042002><FONT size=1>Hans</FONT></SPAN></DIV>
<BLOCKQUOTE dir=ltr style="MARGIN-RIGHT: 0px">
<DIV class=OutlookMessageHeader dir=ltr align=left><FONT face=Tahoma
size=2>-----Original Message-----<BR><B>From:</B> Jack Crawford
[mailto:[log in to unmask]]<BR><B>Sent:</B> Saturday, April 13, 2002
5:30 PM<BR><B>To:</B> [log in to unmask]<BR><B>Subject:</B> [TN] IPC-A-610 has
been DoD Adopted !<BR><BR></FONT></DIV><FONT face="MS Sans Serif" size=1>
<DIV><FONT size=1>IPC-A-610 Acceptability of Electronic Assemblies now has the
same DoD adoption status as another industry standard IPC/EIA J-STD-001C
Requirements for Soldered Electrical and Electronic Assemblies, and the
companion IPC-HDBK-001 w/Amendment 1 Handbook and Guide to Supplement
J-STD-001 (Includes J-STD-001B to C Comparison).</FONT></DIV>
<DIV><FONT size=1></FONT> </DIV>
<DIV><FONT size=1>I downloaded the adoption notice from the DODSSP
QuickSearch Assist website <A
href="http://astimage.daps.dla.mil/quicksearch/">http://astimage.daps.dla.mil/quicksearch/</A>.
This is an "open" site and anyone can download the notice. G</FONT><FONT
size=1>ive me a couple of days to work through the process and I'll also get
the adoption notice downloadable from </FONT><FONT size=1>the IPC-A-610C
description page in the online bookstore <A
href="http://www.ipc.org/bookstore">www.ipc.org/bookstore</A>.</FONT></DIV>
<DIV><FONT size=1></FONT> </DIV>
<DIV><FONT size=1>Cordially</FONT></DIV>
<DIV><FONT size=1>Jack</FONT></DIV>
<DIV><FONT size=1></FONT> </DIV>
<DIV><FONT size=1>Text of the announcement is copied below:</FONT></DIV>
<DIV><FONT size=1></FONT> </DIV>
<DIV>ADOPTION NOTICE<BR>IPC-A610, "Acceptability of Electronic Assemblies",
was adopted on 12-FEB-02 for use by the Department of Defense (DoD). Proposed
changes by DoD activities must be submitted to the DoD Adopting Activity:
Commander, US Army Tank-Automotive and Armaments Command, ATTN: AMSTA-TR-E/IE,
Warren, MI 48397-5000. Copies of this document may be purchased from the The
Institute for Interconnecting and Packaging Electronic Circuits, 2215 Sanders
Rd, Suite 200 South, Northbrook, IL 60062.<BR><A
href="http://www.ipc.org/">http://www.ipc.org/</A>
<BR></DIV></BLOCKQUOTE></FONT></BODY></HTML>
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Date: Tue, 23 Apr 2002 11:01:02 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Randy Bock Sr." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Randy Bock Sr." <[log in to unmask]>
Subject: Re: Wanted: AM79C970AVIW
X-To: [log in to unmask]
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Did some checking, unable to help from my end.
Randy Bock Sr.
----- Original Message -----
From: <[log in to unmask]>
To: <[log in to unmask]>
Sent: Tuesday, April 23, 2002 1:20 AM
Subject: [TN] Wanted: AM79C970AVIW
> I'm getting kinda desperate here, trying to find someone - anyone - who
can
> come up with 100 pcs of AMD's old Ethernet Controller part AM79C970AVIW.
By
> any chance, does any of you know of a quiet corner where some of these
> parts may still survive unclaimed and unwanted, so I can adopt them (for a
> consideration, of course)?
>
> I've spent all morning and my lunch break hunting through web sites using
> every search word I can think of, only to draw a complete blank. Even if
> there aren't 100 pcs in one place, I'll take them piece-meal.
>
> MTIA
>
> Peter
>
> [This e-mail is confidential and may also be privileged. If you are not
the
> intended recipient, please delete it and notify us immediately; you should
> not copy or use it for any purpose, nor disclose its contents to any other
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Date: Tue, 23 Apr 2002 11:09:26 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Cyker, Howard A (Howie)" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Cyker, Howard A (Howie)" <[log in to unmask]>
Subject: Re: Secondary reflow over wave...
MIME-Version: 1.0
Content-Type: text/plain; charset="windows-1252"
Steve,
We have also seen this before. The cause was secondary reflow in most
cases, and required "tweaking" of the wave profile. If that's not
successful, then you may require a selective wave fixture, however that may
not be possible due to your board layout.
You said that ". . . every pad has a via, they alternate . . ." Are you
saying you have VIP (via in pad)? If yes, what size are the vias, and are
you also seeing solder being scavenged through the vias?
Howard A. Cyker
Lucent Technologies
New Product Engineering
Email [log in to unmask]
Phone 978-960-2964
-----Original Message-----
From: Jorge Santana [mailto:[log in to unmask]]
Sent: Tuesday, April 23, 2002 10:35 AM
To: [log in to unmask]
Subject: Re: [TN] Secondary reflow over wave...
Steve
We have seen this on a SOIC that has coplanarity issue on the leads and
the problem was caught at wave solder when the part reflowed at top side of
the board leaving one open junction at the lead.
I have seen this also at BGA and we used Kapton tape to mask.
Thanks
Jorge Santana
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of [log in to unmask]
Sent: Monday, April 22, 2002 8:07 PM
To: [log in to unmask]
Subject: [TN] Secondary reflow over wave...
Hi All!
Got a situation here that I think is secondary reflow...
Have a board here that has some J-leaded DRAM that in functional test, they
can get the board to pass test by putting some pressure on top of some of
the
40-pin J-leaded DRAM's that are causing them to fail...
Out of SMT things look fine, but I have observed some boards that have
failed, show an unusual solder joint appearance after wave. The board is
"swiss-cheesed" with vias, and none of them are tented. Every pad has a via,
they alternate, some have .050" traces to the pad, some have .020" traces to
the pad.
Where we're seeing problems is where there is a bank of them (like a grid of
2 by 8 of them layed-out side by side).
I'm thinking secondary reflow because of the open vias...or could be CTE
mis-match between the part and the board. It's a .062" FR4 board, with
fairly
large 40-pin SOJ's, could be experiencing some hellacious mismatch, no? The
gull-wing parts we don't see the problem, even though the via placement is
the same standard as with the J-leaded parts...J-leads aren't as compliant?
Gonna hook-up the mole tomorrow, attaching it to one of the J-leaded parts
to
learn what it is seeing...will tell me a lot...
Just wondering if anybody else has run into this before...
-Steve Gregory-
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Date: Tue, 23 Apr 2002 11:27:40 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
[log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: BGA Microscopes
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
Hello Technetters,
I'm familiar with the ERSA Scope.
Any experience on the ERSA or recommendations on other similar equipment.
I currently have X-ray capability, but would like to peek under the BGA and
see those balls.
Al
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Date: Tue, 23 Apr 2002 10:33:10 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Jason <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Jason <[log in to unmask]>
Subject: Re: 20 Mhz crystal start-up woes
The feedback circuit could definitly be in question as there is no series
resistance in the design, would offset cap values add any benefit? Instead
of using tow 22 pF, one 22 pF and one 32 pF?
Brian, no cleaning is ever done here!! We use no-clean flux, and never over
apply it either!! (note - high sarcasm in voice - warranty investigation
will do that to a person)
Right now the ESR of the crystals are being questioned, the designer is
worried about having too high of an ESR value, although one of the
suppliers of the crystal analysed the circuit and said the drive level was
too high from the controller when the ESR of the crystal was 11.2, I wonder
if there could be a stack-up error with high ESR values and low drive level
from the controller, and also low ESR and high drive level from the
controller.
Thanks for all the comments,
Jason
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Date: Tue, 23 Apr 2002 12:10:30 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
[log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: TAIYOYUDEN CERAMIC CAPS
MIME-Version: 1.0
Content-Type: multipart/mixed;
boundary="----=_NextPartTM-000-44b3fdd6-56cb-11d6-b135-00508be26895"
This is a multipart message in MIME format.
------=_NextPartTM-000-44b3fdd6-56cb-11d6-b135-00508be26895
Content-Type: multipart/alternative;
boundary="=_alternative 0058D75F85256BA4_="
--=_alternative 0058D75F85256BA4_=
Content-Type: text/plain; charset="us-ascii"
Fellow TNers,
Wanted to see if any one else has experienced this.
We are using a 1uF X7R 1206 of this particular cap and using the
recommended reflow profile for the solder paste. The test is to ground
one end of the cap and measure the noise level from the other end
through a 330kohm impedance circuit. What we have seen is that after the
PCB is reflowed and tested, the noise level is at some specific
amplitude. We can then re-solder the cap by hand and the noise level
will drop an order of magnitude. The reflow soldering appears to be good
- nice fillet, wetting, structurally sound. We were speculating if
perhaps the termination ends of the cap were disconnecting internally
during the reflow (CTE problems) and that the hand soldering is somehow
connecting it back. I have noticed that the recommended reflow profile
of the cap specifies a much shorter liquidous time than what the paste
profile requires. This could also be the problem. I have not yet been
able to speak with the component manufacture to get their opinion.
Sorry for the lengthy message and thanks for your feedback,
Danny
--=_alternative 0058D75F85256BA4_=
Content-Type: text/html; charset="us-ascii"
<br><font size=2 face="sans-serif">Fellow TNers,</font>
<br>
<br><font size=2 face="sans-serif">Wanted to see if any one else has experienced this.</font>
<br><font size=2 face="sans-serif">We are using a 1uF X7R 1206 of this particular cap and using the recommended reflow profile for the solder paste. The test is to ground one end of the cap and measure the noise level from the other end through a 330kohm impedance circuit. What we have seen is that after the PCB is reflowed and tested, the noise level is at some specific amplitude. We can then re-solder the cap by hand and the noise level will drop an order of magnitude. The reflow soldering appears to be good - nice fillet, wetting, structurally sound. We were speculating if perhaps the termination ends of the cap were disconnecting internally during the reflow (CTE problems) and that the hand soldering is somehow connecting it back. I have noticed that the recommended reflow profile of the cap specifies a much shorter liquidous time than what the paste profile requires. This could also be the problem. I have not yet been able to speak with the component manufacture to get !
their opinion. </font>
<br><font size=2 face="sans-serif">Sorry for the lengthy message and thanks for your feedback,</font>
<br><font size=2 face="sans-serif">Danny</font>
--=_alternative 0058D75F85256BA4_=--
------=_NextPartTM-000-44b3fdd6-56cb-11d6-b135-00508be26895--
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Date: Tue, 23 Apr 2002 11:09:01 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Andre Leclair <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Andre Leclair <[log in to unmask]>
Subject: Shorts in PLCC Sockets
We have recently run across a situation which has baffled us. On the PCB
in question there are 4 Wave soldered PLCC sockets. 1 of these is being
reported as having solder shorts underneath. On the returned units we x-
rayed the sockets ( can't see under) and found shorts on 1 socket location
only. The shorts were consistanly on the same pin area for all the sockets
were the shorts were found. We removed a socket only to find the board
very clean underneath...no shorts..
The socket has a bottom retainer to hold all the pins in place.. This was
pried off and to our surprise there was the short.. inside the connector.
The amount of solder was enough to surround 3 pins in 2 seperate areas.
The hole around the pins in the plastic base is no more then 0.002".
Does any one have any idea how solder could have gotten up inside the
connector ( consistantly in the same location)? Or has any one seen this
before?
We have run this assembly several times in the past with no difficulty.
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Date: Tue, 23 Apr 2002 09:25:57 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
phil bavaro <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: phil bavaro <[log in to unmask]>
Subject: Re: IPC SMT FOOTPRINT DESIGN GUIDLINES VS SUPPLIERS - and for
custom components?
In-Reply-To: <003201c1e798$ce642780$0302a8c0@randy>
Mime-Version: 1.0
Content-Type: text/plain; charset="us-ascii"; format=flowed
We build mostly high end RF circuit boards and are faced with component
land patterns that the IPC standards do not address.
Our rule of thumb is the exact opposite of what I have seen most of you
concur on, and that is, we use the manufacturers data sheet first, until we
find that it does not work. Very rarely do we have to change the land
patterns. And then it is primarily only when the circuit is not performing
adequately.
We also sell our chip set and therefore do a lot of work to prepare a
documented and well proven package for the customers. There is a lot to be
said for following the instructions that a supplier gives you when it comes
to custom components such as BCCs and duplexors.
I just don't want everyone to assume that the suppliers data sheets are
always junk. But I do wish that the customers would provide feedback
especially if they find a land pattern that works even better.
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Date: Tue, 23 Apr 2002 12:48:13 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Wenger, George M." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Wenger, George M." <[log in to unmask]>
Subject: Re: Secondary reflow over wave...
MIME-Version: 1.0
Content-Type: text/plain; charset="Windows-1252"
Content-Transfer-Encoding: quoted-printable
Steve,
I haven't seen a photo showing your board and component layout but may =
guess is that you have "Double Reflow". I hate the name the "Double =
Reflow" name IBM Austin coined in their Nepcon 1994 presentation but it =
has sort of stuck. Check out the following two references:
Hallmark, Clay et.al., Nepcon West 1994 "Double Reflow: Degrading Fine =
Pitch Joints In The Wave Soldering Process
Wenger, George et. al., SMI 1995 "Double Reflow: The Stress Fracture =
Reliability Problem of the 90's"
Regards,
George
George M. Wenger (908)-546-4531 [log in to unmask]
Distinguished Member Technical Staff
Celiant Corporation, FMA Lab, 40 Technology Drive, NJ 07059
-----Original Message-----
From: Cyker, Howard A (Howie) [mailto:[log in to unmask]]
Sent: Tuesday, April 23, 2002 11:09 AM
To: [log in to unmask]
Subject: Re: [TN] Secondary reflow over wave...
Steve,
We have also seen this before. The cause was secondary reflow in most
cases, and required "tweaking" of the wave profile. If that's not
successful, then you may require a selective wave fixture, however that =
may
not be possible due to your board layout.
You said that ". . . every pad has a via, they alternate . . ." Are =
you
saying you have VIP (via in pad)? If yes, what size are the vias, and =
are
you also seeing solder being scavenged through the vias?
Howard A. Cyker
Lucent Technologies
New Product Engineering
Email [log in to unmask]
Phone 978-960-2964
-----Original Message-----
From: Jorge Santana [mailto:[log in to unmask]]
Sent: Tuesday, April 23, 2002 10:35 AM
To: [log in to unmask]
Subject: Re: [TN] Secondary reflow over wave...
Steve
We have seen this on a SOIC that has coplanarity issue on the leads =
and
the problem was caught at wave solder when the part reflowed at top side =
of
the board leaving one open junction at the lead.
I have seen this also at BGA and we used Kapton tape to mask.
Thanks
Jorge Santana
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of [log in to unmask]
Sent: Monday, April 22, 2002 8:07 PM
To: [log in to unmask]
Subject: [TN] Secondary reflow over wave...
Hi All!
Got a situation here that I think is secondary reflow...
Have a board here that has some J-leaded DRAM that in functional test, =
they
can get the board to pass test by putting some pressure on top of some =
of
the
40-pin J-leaded DRAM's that are causing them to fail...
Out of SMT things look fine, but I have observed some boards that have
failed, show an unusual solder joint appearance after wave. The board is
"swiss-cheesed" with vias, and none of them are tented. Every pad has a =
via,
they alternate, some have .050" traces to the pad, some have .020" =
traces to
the pad.
Where we're seeing problems is where there is a bank of them (like a =
grid of
2 by 8 of them layed-out side by side).
I'm thinking secondary reflow because of the open vias...or could be CTE
mis-match between the part and the board. It's a .062" FR4 board, with
fairly
large 40-pin SOJ's, could be experiencing some hellacious mismatch, no? =
The
gull-wing parts we don't see the problem, even though the via placement =
is
the same standard as with the J-leaded parts...J-leads aren't as =
compliant?
Gonna hook-up the mole tomorrow, attaching it to one of the J-leaded =
parts
to
learn what it is seeing...will tell me a lot...
Just wondering if anybody else has run into this before...
-Steve Gregory-
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in
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Technet NOMAIL
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ext.5315
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Technet NOMAIL
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http://listserv.ipc.org/archives
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ext.5315
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Date: Tue, 23 Apr 2002 10:24:39 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
David Douthit <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: David Douthit <[log in to unmask]>
Subject: Re: Shorts in PLCC Sockets
X-To: Andre Leclair <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii; x-mac-type="54455854";
x-mac-creator="4D4F5353"
Content-Transfer-Encoding: 7bit
Andre,
If the flux gets in there so will the solder!
David A. Douthit
Manager
LoCan LLC
Andre Leclair wrote:
> We have recently run across a situation which has baffled us. On the PCB
> in question there are 4 Wave soldered PLCC sockets. 1 of these is being
> reported as having solder shorts underneath. On the returned units we x-
> rayed the sockets ( can't see under) and found shorts on 1 socket location
> only. The shorts were consistanly on the same pin area for all the sockets
> were the shorts were found. We removed a socket only to find the board
> very clean underneath...no shorts..
> The socket has a bottom retainer to hold all the pins in place.. This was
> pried off and to our surprise there was the short.. inside the connector.
> The amount of solder was enough to surround 3 pins in 2 seperate areas.
> The hole around the pins in the plastic base is no more then 0.002".
>
> Does any one have any idea how solder could have gotten up inside the
> connector ( consistantly in the same location)? Or has any one seen this
> before?
>
> We have run this assembly several times in the past with no difficulty.
>
> ---------------------------------------------------------------------------------
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> ---------------------------------------------------------------------------------
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Date: Tue, 23 Apr 2002 10:19:34 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
JaMi Smith <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: JaMi Smith <[log in to unmask]>
Subject: Re: 20 Mhz crystal start-up woes
MIME-Version: 1.0
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Jason and the group,
Ditto on this and all of the other previous responses, I concur.
But ...
You have not explained exactly what type of crystal you are using (data
book calls for parallel cut crystal on page 49), nor have you explained
exactly how it is hooked up.
It also appears from a cursory perusal of that same page that the
oscillator "mode" needs to be pre-programmed by setting bits FOSC0 and
FOSC1 to correspond to HS mode in order to operate at that speed.
Not knowing much about PIC's, I cannot offer more, but it appears that
there are ample design questions that may not have been properly
addressed, and you may need to start by handing the engineer a datasheet
opened to page 49 or thereabouts.
It is very common to damage or break a crystal. It is even more common
to attempt to make the wrong one work in an improperly designed circuit.
JaMi Smith=20
* * *
=20
-----Original Message-----
From: Brian Ellis [mailto:[log in to unmask]]=20
Sent: Tuesday, April 23, 2002 5:37 AM
To: [log in to unmask]
Subject: Re: [TN] 20 Mhz crystal start-up woes
Jason
Are you using ultrasonic cleaning? This is a sure way of buggering up
quartz crystals.
Brian
Jason wrote:
>
> Has anyone had difficulty with crystal start-up.
> Currently we are having problems with a circuit that uses a PIC16C711-
> 201/P, 2 @ 22pF load caps and a 20 Mhz AT crystal. The configuration
is for
> fundamental operation.
>
> We are using a high temp screen (85 deg C storage before functional
check)
> to try and weed out problems but have still found modules not
functional at
> the production plant.
> Sleepy crystals have been discussed but we have experimented with
three
> different manufactures of crystals we have ruled this out.
> One of our action items is to redesign and use 10 Mhz, but right now
we
> aren't sure of the root cause of failure so there really isn't a
guarantee
> that this plan will work.
>
> What are some specific design parameters that could be measured to
arrive
> at the root cause?
>
> Thanks,
> Jason
>
>
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Date: Tue, 23 Apr 2002 13:29:35 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Guy Ramsey <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Guy Ramsey <[log in to unmask]>
Subject: Re: TAIYOYUDEN CERAMIC CAPS
X-To: [log in to unmask]
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="----=_NextPart_000_0003_01C1EACA.E90DE5A0"
This is a multi-part message in MIME format.
------=_NextPart_000_0003_01C1EACA.E90DE5A0
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charset="iso-8859-1"
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We recently have seen a similar condition on resistors 1206 resistors. Nice
looking connections but very high resistance readings. Reflow by hand and
resistance drops to normal. We have not identified the cause yet. I'll keep
you in the loop.
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of
[log in to unmask]
Sent: Tuesday, April 23, 2002 12:11 PM
To: [log in to unmask]
Subject: [TN] TAIYOYUDEN CERAMIC CAPS
Fellow TNers,
Wanted to see if any one else has experienced this.
We are using a 1uF X7R 1206 of this particular cap and using the
recommended reflow profile for the solder paste. The test is to ground one
end of the cap and measure the noise level from the other end through a
330kohm impedance circuit. What we have seen is that after the PCB is
reflowed and tested, the noise level is at some specific amplitude. We can
then re-solder the cap by hand and the noise level will drop an order of
magnitude. The reflow soldering appears to be good - nice fillet, wetting,
structurally sound. We were speculating if perhaps the termination ends of
the cap were disconnecting internally during the reflow (CTE problems) and
that the hand soldering is somehow connecting it back. I have noticed that
the recommended reflow profile of the cap specifies a much shorter liquidous
time than what the paste profile requires. This could also be the problem. I
have not yet been able to speak with the component manufacture to get !
their opinion.
Sorry for the lengthy message and thanks for your feedback,
Danny
------=_NextPart_000_0003_01C1EACA.E90DE5A0
Content-Type: text/html;
charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META content=3D"text/html; charset=3Dwindows-1252" =
http-equiv=3DContent-Type>
<META content=3D"MSHTML 5.00.3105.105" name=3DGENERATOR></HEAD>
<BODY>
<DIV><FONT color=3D#0000ff face=3DArial size=3D2><SPAN =
class=3D193412717-23042002>We=20
recently have seen a similar condition on resistors 1206 resistors. Nice =
looking=20
connections but very high resistance readings. Reflow by hand and =
resistance=20
drops to normal. We have not identified the cause yet. I'll keep you in =
the=20
loop.</SPAN></FONT></DIV>
<BLOCKQUOTE=20
style=3D"BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; PADDING-LEFT: =
5px">
<DIV class=3DOutlookMessageHeader><FONT face=3D"Times New Roman"=20
size=3D2>-----Original Message-----<BR><B>From:</B> TechNet=20
[mailto:[log in to unmask]]<B>On Behalf Of</B>=20
[log in to unmask]<BR><B>Sent:</B> Tuesday, April 23, 2002 =
12:11=20
PM<BR><B>To:</B> [log in to unmask]<BR><B>Subject:</B> [TN] TAIYOYUDEN =
CERAMIC=20
CAPS<BR><BR></DIV></FONT><BR><FONT face=3Dsans-serif size=3D2>Fellow =
TNers,</FONT>=20
<BR><BR><FONT face=3Dsans-serif size=3D2>Wanted to see if any one else =
has=20
experienced this.</FONT> <BR><FONT face=3Dsans-serif size=3D2>We are =
using a 1uF=20
X7R 1206 of this particular cap and using the recommended reflow =
profile for=20
the solder paste. The test is to ground one end of the cap and measure =
the=20
noise level from the other end through a 330kohm impedance circuit. =
What we=20
have seen is that after the PCB is reflowed and tested, the noise =
level is at=20
some specific amplitude. We can then re-solder the cap by hand and the =
noise=20
level will drop an order of magnitude. The reflow soldering appears to =
be good=20
- nice fillet, wetting, structurally sound. We were speculating if =
perhaps the=20
termination ends of the cap were disconnecting internally during the =
reflow=20
(CTE problems) and that the hand soldering is somehow connecting it =
back. I=20
have noticed that the recommended reflow profile of the cap specifies =
a much=20
shorter liquidous time than what the paste profile requires. This =
could also=20
be the problem. I have not yet been able to speak with the component=20
manufacture to get ! their opinion. </FONT><BR><FONT face=3Dsans-serif =
size=3D2>Sorry for the lengthy message and thanks for your =
feedback,</FONT>=20
<BR><FONT face=3Dsans-serif =
size=3D2>Danny</FONT></BLOCKQUOTE></BODY></HTML>
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Date: Tue, 23 Apr 2002 10:29:00 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Greg Scott <[log in to unmask]>
Organization: Cray Inc
Subject: Re: uBGA routing
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HI Alan,
Sounds like the only thing you can do is reduce via drill size from .010 to .008.
That would give 5.5mils per side annular ring on .019 pad. With the board being .064 thick that is
only 8:1 aspect ratio.
A good fabrication shop should be able to handle this.
I take it this is an 8 layer board with external foils and micro vias on top only? This should be no
problem for experienced fabrication shop doing this kind of stackup process. It always helps if this
is your tightest drilling tolerance requirements on board that it is located
as close to center of board as possible.
Regards,
Greg Scott
Cray Inc.
Alan Groves wrote:
> Hi Technetters, any help that could be given on following problem would be
> greatly appreciated...
>
> I am currently routing a PCB which has 532 pin uBGAs on it, these have a
> pitch of 0,8mm (31,5 thou). I have followed manufacturer's design guidelines
> in the past but am still receiving complaints from fabricators. I have
> resolved vertically by having a 6 thou microvia drilled thru pad centres to
> layer 2, then routed on layer 2 to a buried via (layers 2-7) of 10 thou
> drill, 19 thou land. The track and gap allowance is 4 thou minimum. I am
> using thermal connection pads of 17 (internal) and 26 (external) thou, and
> isolating pads of 24 thou - all only on buried vias, I cannot increase these
> pad sizes (much) or I could block GND and PWR from getting to destinations.
> Fabricators complain of copper features too close to drill hole, are they
> talking skew, or 'tear out' by that much (8 thou 'ish)?
> The board is 1,6mm thick FR4, 8 conducting layers, no controlled impedance.
>
> Can anyone suggest any tricks or tweaks to sizes that would assist?
>
> Thanks in advance,
>
> Alan Groves,
> Senior PCB Designer CID
> Spectel Head Office, 21 Stillorgan Ind. Park, Stillorgan,
> Co. Dublin. Ireland.
> Phone: 353 907 62803
> Fax: 353 1 2953740
> Email: [log in to unmask]
> Internet: www.spectel.com
>
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> ---------------------------------------------------------------------------------
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Date: Tue, 23 Apr 2002 13:38:06 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Edward S. Wheeler" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Edward S. Wheeler" <[log in to unmask]>
Subject: Re: BGA Microscopes
X-To: [log in to unmask]
In-Reply-To: <[log in to unmask]>
Mime-Version: 1.0
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We tried the ERSA scope, and the OC White scope, etc. and have found a
cheap and easy solution. We use a small beveled mirror on the end of a
handle (glued on) and focus on it with a microscope. With a little
practice, it becomes a great quick and dirty inspection tool that is able
to see the outer and second rows. If you're interested, I can let you know
where we get our mirrors.
Ed
At 11:27 AM 4/23/2002 -0400, you wrote:
>Hello Technetters,
>
>I'm familiar with the ERSA Scope.
>
>Any experience on the ERSA or recommendations on other similar equipment.
>
>I currently have X-ray capability, but would like to peek under the BGA and
>see those balls.
>
>
>Al
>
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Date: Tue, 23 Apr 2002 11:16:24 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Miguel Vallejo <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Miguel Vallejo <[log in to unmask]>
Subject: Re: Shorts in PLCC Sockets
X-To: Andre Leclair <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
base on your description, the following questions come to mind:
1. Could the part have come with the condition?
2. Is there an open area in the PCB, near the socket in question, through
wich solder can over flow and get underneath the socket?
-----Original Message-----
From: Andre Leclair [mailto:[log in to unmask]]
Sent: Tuesday, April 23, 2002 9:09 AM
To: [log in to unmask]
Subject: [TN] Shorts in PLCC Sockets
We have recently run across a situation which has baffled us. On the PCB
in question there are 4 Wave soldered PLCC sockets. 1 of these is being
reported as having solder shorts underneath. On the returned units we x-
rayed the sockets ( can't see under) and found shorts on 1 socket location
only. The shorts were consistanly on the same pin area for all the sockets
were the shorts were found. We removed a socket only to find the board
very clean underneath...no shorts..
The socket has a bottom retainer to hold all the pins in place.. This was
pried off and to our surprise there was the short.. inside the connector.
The amount of solder was enough to surround 3 pins in 2 seperate areas.
The hole around the pins in the plastic base is no more then 0.002".
Does any one have any idea how solder could have gotten up inside the
connector ( consistantly in the same location)? Or has any one seen this
before?
We have run this assembly several times in the past with no difficulty.
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Date: Tue, 23 Apr 2002 13:26:33 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Andre Leclair <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Andre Leclair <[log in to unmask]>
Subject: Re: Shorts in PLCC Sockets
X-To: [log in to unmask]
base on your description, the following questions come to mind:
1. Could the part have come with the condition?
We are investigating with the part manufacture with no results as of yet.
They are
2. Is there an open area in the PCB, near the socket in question, through
wich solder can over flow and get underneath the socket?
There are no holes in the PCB near the socket where solder extra solder
could have migrated under the socket and then under the pin retainer. When
the socket was removed there was now evidance that extra solder had been
between the board and the socket base. For the amount of solder that was
between the base and the main body of the socket there should have been
evidance of solder ( the plastic body marks very easily at 500'F).
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Date: Tue, 23 Apr 2002 12:06:43 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
John Foster <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: John Foster <[log in to unmask]>
Subject: Via Plug
MIME-Version: 1.0
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Hello, I am new to this listserver. I must say that it is very
informative. I wish I had known of it long ago.
I have a question about via plugging. Right now
our board vendor is doing our via plugs with
I guess with a standard epoxy. We are trying
to find a solution that would give us a much
better thermal performance.
We are looking at silver epoxy and this
material from Dupont. Does anyone know of
some material that would give us a really good
thermal performance. We are in a commercial
environment. So the material does not have to
meet industrial specs.
Any input on this matter would be greatly '
appreciated.
Thank You
John Foster
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Date: Tue, 23 Apr 2002 15:14:04 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"McMullen, Kerry" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "McMullen, Kerry" <[log in to unmask]>
Subject: Re: BGA Microscopes
X-To: "[log in to unmask]" <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Hi Al,
Try www.minimicrostencil.com They have a mini-mirror BGA inspection tool.
Works pretty good with a scope. Can look at the first row of balls all
around the BGA. We use it for incoming inspection.
Kerry
-----Original Message-----
From: [log in to unmask] [mailto:[log in to unmask]]
Sent: Tuesday, April 23, 2002 11:28 AM
To: [log in to unmask]
Subject: [TN] BGA Microscopes
Hello Technetters,
I'm familiar with the ERSA Scope.
Any experience on the ERSA or recommendations on other similar equipment.
I currently have X-ray capability, but would like to peek under the BGA and
see those balls.
Al
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Date: Tue, 23 Apr 2002 16:05:39 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Marsico, James" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Marsico, James" <[log in to unmask]>
Subject: PREPREG
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Hello, Technetters:
I'm very naive when it comes to prepreg, so I'll go to the experts. Is
there a list available of prepreg designations (i.e. 2313, 1080, 106, etc.)
with the respective properties? Will a stack-up of the three prepregs
mentioned yield a thickness of .006 inches? Where can I find information on
hot to specify prepreg layers in a PWB?
Thanks in advance,
Jim Marsico
Senior Engineer
Production Engineering
EDO Electronics Systems Group
[log in to unmask] <mailto:[log in to unmask]>
631-595-5879
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Date: Tue, 23 Apr 2002 16:34:48 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Guy Ramsey <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Guy Ramsey <[log in to unmask]>
Subject: Re: Shorts in PLCC Sockets
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
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I have seen this condition caused by over active chipwave and excessive
setting on an omega wave. The omega wave is a vibrating plate in the
solderwave that produces turbulence in the lambda wave (main wave) that is
perpendicular to the normal wave dynamics. The action forces solder up
through the board, bridges form at the heels of the springs that form the
socket contacts.
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Andre Leclair
> Sent: Tuesday, April 23, 2002 2:27 PM
> To: [log in to unmask]
> Subject: Re: [TN] Shorts in PLCC Sockets
>
>
> base on your description, the following questions come to mind:
> 1. Could the part have come with the condition?
> We are investigating with the part manufacture with no results as of yet.
> They are
>
> 2. Is there an open area in the PCB, near the socket in question, through
> wich solder can over flow and get underneath the socket?
>
> There are no holes in the PCB near the socket where solder extra solder
> could have migrated under the socket and then under the pin
> retainer. When
> the socket was removed there was now evidance that extra solder had been
> between the board and the socket base. For the amount of solder that was
> between the base and the main body of the socket there should have been
> evidance of solder ( the plastic body marks very easily at 500'F).
>
> ------------------------------------------------------------------
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Date: Tue, 23 Apr 2002 16:28:16 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"McMullen, Kerry" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "McMullen, Kerry" <[log in to unmask]>
Subject: Re: Via Plug
X-To: John Foster <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Try DuPont CB100.
http://www.dupont.com/mcm/new/viaplug.html
Good Luck!
Kerry
-----Original Message-----
From: John Foster [mailto:[log in to unmask]]
Sent: Tuesday, April 23, 2002 3:07 PM
To: [log in to unmask]
Subject: [TN] Via Plug
Hello, I am new to this listserver. I must say that it is very
informative. I wish I had known of it long ago.
I have a question about via plugging. Right now
our board vendor is doing our via plugs with
I guess with a standard epoxy. We are trying
to find a solution that would give us a much
better thermal performance.
We are looking at silver epoxy and this
material from Dupont. Does anyone know of
some material that would give us a really good
thermal performance. We are in a commercial
environment. So the material does not have to
meet industrial specs.
Any input on this matter would be greatly '
appreciated.
Thank You
John Foster
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Date: Tue, 23 Apr 2002 17:07:36 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
tony steinke <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: tony steinke <[log in to unmask]>
Subject: Re: PREPREG
MIME-Version: 1.0
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James,
Your question seems so simple to answer but someone could actually write a
50
page book about it. Some of the material manufacturers have on their web
site
the thicknesses, resin content, gel time, etc. of all the pregs that they
manufacture.
The problem is that they vary somewhat from manufacturer to manufacturer,
and you may
also get variation from board house to board house. The three mentioned
prepregs in my past
experience would actually be .008-.009. My personal advice would be not to
have specified
prepregs on the print and and stick to overall board tolerance.(unless
controlled impedence
is involved).Leave the stackup to the board manufacturer.
You can contact me offline if you would like.
Regards,
Tony Steinke
[log in to unmask]
----- Original Message -----
From: "Marsico, James" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Tuesday, April 23, 2002 1:05 PM
Subject: [TN] PREPREG
> Hello, Technetters:
>
> I'm very naive when it comes to prepreg, so I'll go to the experts. Is
> there a list available of prepreg designations (i.e. 2313, 1080, 106,
etc.)
> with the respective properties? Will a stack-up of the three prepregs
> mentioned yield a thickness of .006 inches? Where can I find information
on
> hot to specify prepreg layers in a PWB?
>
> Thanks in advance,
>
> Jim Marsico
> Senior Engineer
> Production Engineering
> EDO Electronics Systems Group
> [log in to unmask] <mailto:[log in to unmask]>
> 631-595-5879
>
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Date: Tue, 23 Apr 2002 17:20:52 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Torres, Roberto" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Torres, Roberto" <[log in to unmask]>
Subject: Microscopes
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Hi All;
Does anyone know an inexpensive why to adapt a microscope to take
digital pictures of parts of assemblies PCB's.
Regards
Bob Torres
-----Original Message-----
From: McMullen, Kerry [mailto:[log in to unmask]]
Sent: Tuesday, April 23, 2002 12:14 PM
To: [log in to unmask]
Subject: Re: [TN] BGA Microscopes
Hi Al,
Try www.minimicrostencil.com They have a mini-mirror BGA inspection tool.
Works pretty good with a scope. Can look at the first row of balls all
around the BGA. We use it for incoming inspection.
Kerry
-----Original Message-----
From: [log in to unmask] [mailto:[log in to unmask]]
Sent: Tuesday, April 23, 2002 11:28 AM
To: [log in to unmask]
Subject: [TN] BGA Microscopes
Hello Technetters,
I'm familiar with the ERSA Scope.
Any experience on the ERSA or recommendations on other similar equipment.
I currently have X-ray capability, but would like to peek under the BGA and
see those balls.
Al
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Date: Tue, 23 Apr 2002 17:48:49 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Looking for used oven in Canada
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Hi all,
I'm looking for a used cure oven (batch) or a reflow oven with board
clearance of 3". It would be used for curing conformal coating.
Anyone, anyone???
Peter Crain
Manufacturing Engineering Technologist
Substation Automation Solutions
General Electric Canada Inc.
2728 Hopewell Place N.E., Calgary, Alberta T1Y 7J7 CANADA
Tel: 403.214.4560 Dialcomm: 8.498.4560, Fax: 403.214.4776
Website: www.gepower.com/geharrisenergy/
NOTICE: The information contained in this e-mail is privileged, confidential
and intended solely for the use of the addressee named above. If the reader
of this e-mail is not the intended recipient, you are hereby notified that
any dissemination, distribution or copying of this e-mail is strictly
prohibited. If you have received this e-mail in error, please notify me
immediately by telephone (collect) at (1) 403.214.4400 and destroy this
e-mail as well as any copy. Thank you.
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Date: Tue, 23 Apr 2002 17:48:23 EDT
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Microscopes
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="part1_bc.256daa77.29f730a7_boundary"
--part1_bc.256daa77.29f730a7_boundary
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
Hi Bob!
I have a FUJIFILM MX-600ZOOM digital camera and I focus whatever I want a
picture of under the microscope, take the rubber eye-cup off one of the
microscope lenses,
put the lense of the camera up against the microscope lense, look at the LCD
in the back of the camera to make sure the camera is seeing what I want a
picture of, then snap! I got the picture! Can't get much cheaper than that...
Go to my page at: http://www.stevezeva.homestead.com and look at the pictures
called Via N Pad...I took the pictures the way I just described, not too
shabby, huh?
-Steve Gregory-
> Hi All;
>
> Does anyone know an inexpensive why to adapt a microscope to take
> digital pictures of parts of assemblies PCB's.
>
> Regards
> Bob Torres
>
--part1_bc.256daa77.29f730a7_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>Hi Bob!
<BR>
<BR>I have a FUJIFILM MX-600ZOOM digital camera and I focus whatever I want a picture of under the microscope, take the rubber eye-cup off one of the microscope lenses,
<BR>put the lense of the camera up against the microscope lense, look at the LCD in the back of the camera to make sure the camera is seeing what I want a picture of, then snap! I got the picture! Can't get much cheaper than that...
<BR>
<BR>Go to my page at: http://www.stevezeva.homestead.com and look at the pictures called Via N Pad...I took the pictures the way I just described, not too shabby, huh?
<BR>
<BR>-Steve Gregory-
<BR>
<BR>
<BR><BLOCKQUOTE TYPE=CITE style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">Hi All;
<BR>
<BR>Does anyone know an inexpensive why to adapt a microscope to take
<BR>digital pictures of parts of assemblies PCB's.
<BR>
<BR>Regards
<BR>Bob Torres
<BR></FONT><FONT COLOR="#000000" SIZE=3 FAMILY="SANSSERIF" FACE="Arial" LANG="0"></BLOCKQUOTE>
<BR></FONT><FONT COLOR="#000000" SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0">
<BR></FONT></HTML>
--part1_bc.256daa77.29f730a7_boundary--
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Date: Wed, 24 Apr 2002 08:37:03 +0930
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Lothar Thole <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Lothar Thole <[log in to unmask]>
Subject: Re: Microscopes
X-To: "Torres, Roberto" <[log in to unmask]>
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit
Bob
I have found it much easier to just buy a Nikon Coolpix 990, which has a
built-in macro lens, and can focus down to 0.5". No microscope needed!
Regards,
Lothar Thole
=======================================================
Lothar Thole
Product Engineering Manager
Vision Fire and Security
14 Park Way
Technology Park
MAWSON LAKES SA 5095
AUSTRALIA.
tel: +61-(0)8-8462-1151 (direct)
tel: +61-(0)8-8462-1000
fax: +61-(0)8-8462-1001
mobile: +61-(0)407-166-600
email: [log in to unmask]
web site: www.vsl.com.au/adpro
=======================================================
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Torres, Roberto
Sent: Wednesday, 24 April 2002 6:51 AM
To: [log in to unmask]
Subject: [TN] Microscopes
Hi All;
Does anyone know an inexpensive why to adapt a microscope to take
digital pictures of parts of assemblies PCB's.
Regards
Bob Torres
-----Original Message-----
From: McMullen, Kerry [mailto:[log in to unmask]]
Sent: Tuesday, April 23, 2002 12:14 PM
To: [log in to unmask]
Subject: Re: [TN] BGA Microscopes
Hi Al,
Try www.minimicrostencil.com They have a mini-mirror BGA inspection tool.
Works pretty good with a scope. Can look at the first row of balls all
around the BGA. We use it for incoming inspection.
Kerry
-----Original Message-----
From: [log in to unmask] [mailto:[log in to unmask]]
Sent: Tuesday, April 23, 2002 11:28 AM
To: [log in to unmask]
Subject: [TN] BGA Microscopes
Hello Technetters,
I'm familiar with the ERSA Scope.
Any experience on the ERSA or recommendations on other similar equipment.
I currently have X-ray capability, but would like to peek under the BGA and
see those balls.
Al
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Date: Tue, 23 Apr 2002 19:39:35 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Torres, Roberto" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Torres, Roberto" <[log in to unmask]>
Subject: Re: Microscopes
X-To: [log in to unmask]
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="----_=_NextPart_001_01C1EB20.2071FB8A"
This message is in MIME format. Since your mail reader does not understand
this format, some or all of this message may not be legible.
------_=_NextPart_001_01C1EB20.2071FB8A
Content-Type: text/plain;
charset="iso-8859-1"
Thanks Steve.
Regards
Bob Torres
-----Original Message-----
From: [log in to unmask] [mailto:[log in to unmask]]
Sent: Tuesday, April 23, 2002 2:48 PM
To: [log in to unmask]
Subject: Re: [TN] Microscopes
Hi Bob!
I have a FUJIFILM MX-600ZOOM digital camera and I focus whatever I want a
picture of under the microscope, take the rubber eye-cup off one of the
microscope lenses,
put the lense of the camera up against the microscope lense, look at the LCD
in the back of the camera to make sure the camera is seeing what I want a
picture of, then snap! I got the picture! Can't get much cheaper than
that...
Go to my page at: http://www.stevezeva.homestead.com and look at the
pictures called Via N Pad...I took the pictures the way I just described,
not too shabby, huh?
-Steve Gregory-
Hi All;
Does anyone know an inexpensive why to adapt a microscope to take
digital pictures of parts of assemblies PCB's.
Regards
Bob Torres
------_=_NextPart_001_01C1EB20.2071FB8A
Content-Type: text/html;
charset="iso-8859-1"
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=iso-8859-1">
<META content="MSHTML 6.00.2712.300" name=GENERATOR></HEAD>
<BODY>
<DIV><FONT face=Arial color=#0000ff size=2></FONT> </DIV>
<DIV><SPAN class=350133923-23042002><FONT face=Arial color=#0000ff size=2>Thanks
Steve.</FONT></SPAN></DIV>
<DIV><SPAN class=350133923-23042002><FONT face=Arial color=#0000ff
size=2></FONT></SPAN> </DIV>
<DIV><SPAN class=350133923-23042002><FONT face=Arial color=#0000ff
size=2>Regards</FONT></SPAN></DIV>
<DIV><SPAN class=350133923-23042002><FONT face=Arial color=#0000ff size=2>Bob
Torres</FONT></SPAN></DIV>
<BLOCKQUOTE>
<DIV class=OutlookMessageHeader dir=ltr align=left><FONT face=Tahoma
size=2>-----Original Message-----<BR><B>From:</B> [log in to unmask]
[mailto:[log in to unmask]]<BR><B>Sent:</B> Tuesday, April 23, 2002 2:48
PM<BR><B>To:</B> [log in to unmask]<BR><B>Subject:</B> Re: [TN]
Microscopes<BR><BR></FONT></DIV><FONT face=arial,helvetica><FONT size=2>Hi
Bob! <BR><BR>I have a FUJIFILM MX-600ZOOM digital camera and I focus whatever
I want a picture of under the microscope, take the rubber eye-cup off one of
the microscope lenses, <BR>put the lense of the camera up against the
microscope lense, look at the LCD in the back of the camera to make sure the
camera is seeing what I want a picture of, then snap! I got the picture! Can't
get much cheaper than that... <BR><BR>Go to my page at:
http://www.stevezeva.homestead.com and look at the pictures called Via N
Pad...I took the pictures the way I just described, not too shabby, huh?
<BR><BR>-Steve Gregory- <BR><BR><BR>
<BLOCKQUOTE
style="PADDING-LEFT: 5px; MARGIN-LEFT: 5px; BORDER-LEFT: #0000ff 2px solid; MARGIN-RIGHT: 0px"
TYPE="CITE">Hi All; <BR><BR>Does anyone know an inexpensive why to adapt a
microscope to take <BR>digital pictures of parts of assemblies PCB's.
<BR><BR>Regards <BR>Bob Torres <BR></FONT><FONT lang=0 face=Arial
color=#000000 size=3 FAMILY="SANSSERIF"></BLOCKQUOTE><BR></FONT><FONT lang=0
face=Arial color=#000000 size=2
FAMILY="SANSSERIF"><BR></BLOCKQUOTE></FONT></FONT></BODY></HTML>
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Date: Tue, 23 Apr 2002 17:25:17 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: PREPREG
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Just one thing to add, if it is controlled impedance, specify what impedance
you want and what tolerance on the impedance and let the supplier select
prepreg to meet the requirement.
----- Original Message -----
Wrom: OYIYZUNNYCGPKYLEJGDGVCJVTLBXFGGMEPYOQKEDO
To: <[log in to unmask]>
Sent: Tuesday, April 23, 2002 5:07 PM
Subject: Re: [TN] PREPREG
> James,
> Your question seems so simple to answer but someone could actually write a
> 50
> page book about it. Some of the material manufacturers have on their web
> site
> the thicknesses, resin content, gel time, etc. of all the pregs that they
> manufacture.
> The problem is that they vary somewhat from manufacturer to manufacturer,
> and you may
> also get variation from board house to board house. The three mentioned
> prepregs in my past
> experience would actually be .008-.009. My personal advice would be not to
> have specified
> prepregs on the print and and stick to overall board tolerance.(unless
> controlled impedence
> is involved).Leave the stackup to the board manufacturer.
> You can contact me offline if you would like.
> Regards,
> Tony Steinke
> [log in to unmask]
>
> ----- Original Message -----
> Wrom: TWFAOBUZXUWLSZLKBRNVWWCUFPEGAUTFJMVRESKPNKM
> To: <[log in to unmask]>
> Sent: Tuesday, April 23, 2002 1:05 PM
> Subject: [TN] PREPREG
>
>
> > Hello, Technetters:
> >
> > I'm very naive when it comes to prepreg, so I'll go to the experts. Is
> > there a list available of prepreg designations (i.e. 2313, 1080, 106,
> etc.)
> > with the respective properties? Will a stack-up of the three prepregs
> > mentioned yield a thickness of .006 inches? Where can I find
information
> on
> > hot to specify prepreg layers in a PWB?
> >
> > Thanks in advance,
> >
> > Jim Marsico
> > Senior Engineer
> > Production Engineering
> > EDO Electronics Systems Group
> > [log in to unmask] <mailto:[log in to unmask]>
> > 631-595-5879
> >
>
> --------------------------------------------------------------------------
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> > Please visit IPC web site http://www.ipc.org/html/forum.htm for
additional
> > information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700
> ext.5315
>
> --------------------------------------------------------------------------
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>
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>
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Date: Tue, 23 Apr 2002 20:03:37 -0500
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Seth Goodman <[log in to unmask]>
Subject: Re: 20 Mhz crystal start-up woes
X-To: Jason <[log in to unmask]>
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
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Jason,
I don't know about that particular PIC processor, but many processors have a
programmable oscillator start-up delay (fuse selectable). This is to allow
the oscillator to stabilize before allowing the processor to run.
Typically, processors that have this feature have two or three settings.
Shortest delay is usually for RC oscillator (yes, people do use these!),
medium delay for ceramic resonator and longest delay is for crystal. Check
to see if your processor has this option and set the delay to the longest
possible. Crystals have very high-Q and therefore take a long time to
settle down.
Regards,
Seth Goodman
Goodman Associates, LLC
tel 608.833.9933
fax 608.833.9966
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Jason
> Sent: Monday, April 22, 2002 11:24 AM
> To: [log in to unmask]
> Subject: [TN] 20 Mhz crystal start-up woes
>
>
> Has anyone had difficulty with crystal start-up.
> Currently we are having problems with a circuit that uses a PIC16C711-
> 201/P, 2 @ 22pF load caps and a 20 Mhz AT crystal. The
> configuration is for
> fundamental operation.
>
> We are using a high temp screen (85 deg C storage before functional check)
> to try and weed out problems but have still found modules not
> functional at
> the production plant.
> Sleepy crystals have been discussed but we have experimented with three
> different manufactures of crystals we have ruled this out.
> One of our action items is to redesign and use 10 Mhz, but right now we
> aren't sure of the root cause of failure so there really isn't a guarantee
> that this plan will work.
>
> What are some specific design parameters that could be measured to arrive
> at the root cause?
>
> Thanks,
> Jason
>
> ------------------------------------------------------------------
> ---------------
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> ------------------------------------------------------------------
> ---------------
>
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Date: Tue, 23 Apr 2002 20:09:01 -0500
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Seth Goodman <[log in to unmask]>
Subject: Re: TAIYOYUDEN CERAMIC CAPS
X-To: [log in to unmask]
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="----=_NextPart_000_001D_01C1EB02.B5AE8560"
This is a multi-part message in MIME format.
------=_NextPart_000_001D_01C1EB02.B5AE8560
Content-Type: text/plain;
charset="us-ascii"
Content-Transfer-Encoding: 7bit
Hi Dan,
I've seen this same problem many years ago from other manufacturers of
ceramic capacitors as well. The bottom line is that these big ceramics are
not great in low-noise analog filter circuits. Since this application only
represents a small percentage of the total use of these components, the
manufacturers don't consistently check for this problem. This may not be
what you want to hear, but the only long-term solution I found was going to
film caps for this application.
Regards,
Seth Goodman
Goodman Associates, LLC
tel 608.833.9933
fax 608.833.9966
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of
[log in to unmask]
Sent: Tuesday, April 23, 2002 11:10 AM
To: [log in to unmask]
Subject: [TN] TAIYOYUDEN CERAMIC CAPS
Fellow TNers,
Wanted to see if any one else has experienced this.
We are using a 1uF X7R 1206 of this particular cap and using the
recommended reflow profile for the solder paste. The test is to ground one
end of the cap and measure the noise level from the other end through a
330kohm impedance circuit. What we have seen is that after the PCB is
reflowed and tested, the noise level is at some specific amplitude. We can
then re-solder the cap by hand and the noise level will drop an order of
magnitude. The reflow soldering appears to be good - nice fillet, wetting,
structurally sound. We were speculating if perhaps the termination ends of
the cap were disconnecting internally during the reflow (CTE problems) and
that the hand soldering is somehow connecting it back. I have noticed that
the recommended reflow profile of the cap specifies a much shorter liquidous
time than what the paste profile requires. This could also be the problem. I
have not yet been able to speak with the component manufacture to get !
their opinion.
Sorry for the lengthy message and thanks for your feedback,
Danny
------=_NextPart_000_001D_01C1EB02.B5AE8560
Content-Type: text/html;
charset="us-ascii"
Content-Transfer-Encoding: quoted-printable
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META http-equiv=3DContent-Type content=3D"text/html; =
charset=3Dus-ascii">
<META content=3D"MSHTML 6.00.2715.400" name=3DGENERATOR></HEAD>
<BODY>
<DIV><SPAN class=3D058380401-24042002><FONT face=3DArial size=3D2>Hi=20
Dan,</FONT></SPAN></DIV>
<DIV><FONT face=3DArial><FONT size=3D2><SPAN =
class=3D058380401-24042002><FONT=20
face=3DArial size=3D2></FONT></SPAN></FONT></FONT> </DIV>
<DIV><SPAN class=3D058380401-24042002><FONT face=3DArial size=3D2>I've =
seen this same=20
problem many years ago from other manufacturers of ceramic capacitors as =
well. The bottom line is that these big ceramics are not great in=20
low-noise analog filter circuits. Since this application only =
represents a=20
small percentage of the total use of these components, the manufacturers =
don't=20
consistently check for this problem. This may not be what you want =
to=20
hear, but the only long-term solution I found was going to film caps for =
this=20
application.</FONT></SPAN></DIV>
<DIV><SPAN class=3D058380401-24042002> </DIV>
<DIV><FONT face=3DArial size=3D2>Regards,<BR><BR>Seth Goodman<BR>Goodman =
Associates,=20
LLC<BR>tel 608.833.9933<BR>fax 608.833.9966<BR></FONT></DIV>
<DIV></SPAN> </DIV>
<BLOCKQUOTE=20
style=3D"PADDING-LEFT: 5px; MARGIN-LEFT: 5px; BORDER-LEFT: #0000ff 2px =
solid">
<DIV class=3DOutlookMessageHeader dir=3Dltr align=3Dleft><FONT =
face=3DTahoma=20
size=3D2>-----Original Message-----<BR><B>From:</B> TechNet=20
[mailto:[log in to unmask]]<B>On Behalf Of=20
</B>[log in to unmask]<BR><B>Sent:</B> Tuesday, April 23, 2002 =
11:10=20
AM<BR><B>To:</B> [log in to unmask]<BR><B>Subject:</B> [TN] TAIYOYUDEN =
CERAMIC=20
CAPS<BR><BR></FONT></DIV><BR><FONT face=3Dsans-serif size=3D2>Fellow =
TNers,</FONT>=20
<BR><BR><FONT face=3Dsans-serif size=3D2>Wanted to see if any one else =
has=20
experienced this.</FONT> <BR><FONT face=3Dsans-serif size=3D2>We are =
using a 1uF=20
X7R 1206 of this particular cap and using the recommended reflow =
profile for=20
the solder paste. The test is to ground one end of the cap and measure =
the=20
noise level from the other end through a 330kohm impedance circuit. =
What we=20
have seen is that after the PCB is reflowed and tested, the noise =
level is at=20
some specific amplitude. We can then re-solder the cap by hand and the =
noise=20
level will drop an order of magnitude. The reflow soldering appears to =
be good=20
- nice fillet, wetting, structurally sound. We were speculating if =
perhaps the=20
termination ends of the cap were disconnecting internally during the =
reflow=20
(CTE problems) and that the hand soldering is somehow connecting it =
back. I=20
have noticed that the recommended reflow profile of the cap specifies =
a much=20
shorter liquidous time than what the paste profile requires. This =
could also=20
be the problem. I have not yet been able to speak with the component=20
manufacture to get ! their opinion. </FONT><BR><FONT face=3Dsans-serif =
size=3D2>Sorry for the lengthy message and thanks for your =
feedback,</FONT>=20
<BR><FONT face=3Dsans-serif =
size=3D2>Danny</FONT></BLOCKQUOTE></BODY></HTML>
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=========================================================================
Date: Wed, 24 Apr 2002 10:26:24 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: TAIYOYUDEN CERAMIC CAPS
X-To: [log in to unmask]
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
Can't offer an answer, Danny, but may add a bit more fuel to your fire.
I've just had a board returned to me by the Test Engineer, who found two
X7R 0805 caps "missing". By "missing", I mean that the solder joints and
the component end caps were still there, but the ceramic centre portion had
disappeared.
One of several possible suspects that immediately sprang to mind, was this:
There appears to be more solder in the solder joint than is strictly
acceptable, though this board is a development model. I wondered if the
large amount of solder, while contracting when cooling, was pulling the
ends of the caps, allowing the middles to fall out. Anyone got any thoughts
or experiences about this? I have a couple of not-terribly-good pictures I
can show you, if they might help to focus thoughts.
Peter
[log in to unmask] 24/04/2002 12:10 AM
Sent by: TechNet <[log in to unmask]>
Please respond to "TechNet E-Mail Forum."; Please respond to danny.harkins
To: [log in to unmask]
cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST Aero/ST Group)
Subject: [TN] TAIYOYUDEN CERAMIC CAPS
Fellow TNers,
Wanted to see if any one else has experienced this.
We are using a 1uF X7R 1206 of this particular cap and using the
recommended reflow profile for the solder paste. The test is to ground one
end of the cap and measure the noise level from the other end through a
330kohm impedance circuit. What we have seen is that after the PCB is
reflowed and tested, the noise level is at some specific amplitude. We can
then re-solder the cap by hand and the noise level will drop an order of
magnitude. The reflow soldering appears to be good - nice fillet, wetting,
structurally sound. We were speculating if perhaps the termination ends of
the cap were disconnecting internally during the reflow (CTE problems) and
that the hand soldering is somehow connecting it back. I have noticed that
the recommended reflow profile of the cap specifies a much shorter
liquidous time than what the paste profile requires. This could also be the
problem. I have not yet been able to speak with the component manufacture
to get ! their opinion.
Sorry for the lengthy message and thanks for your feedback,
Danny
[This e-mail is confidential and may also be privileged. If you are not the
intended recipient, please delete it and notify us immediately; you should
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Date: Tue, 23 Apr 2002 23:34:42 -0400
Reply-To: Liviu Jurjica <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Liviu Jurjica <[log in to unmask]>
Subject: Re: Microscopes
X-To: "Torres, Roberto" <[log in to unmask]>
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
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Hi Bob,
took this picture ...mictor_rew.jpg... with a Mavica barely hooked to a
microscpe ;-) (sory, missed a reply to the spelling topic, foud it
challenging geetin the mispeling right).
See attachments for picture taken trough the microscope; actually, I had
another shot, better, including solder balls melted to the connector
housing, can't find it right now.
I have another nice shot of Portsmouth, taken with the same Mavica, while
looking trough USS Albacore's periscope..
Anyway, shouldn't be much of a problem getting pictures of parts of
assembled PCB's even if not using adaptors, brackets etc.
for mounting any digital camera to the microscope.
G'nite and good luck in your photographic sessions.
LJ
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Torres, Roberto
Sent: Tuesday, April 23, 2002 5:21 PM
To: [log in to unmask]
Subject: [TN] Microscopes
Hi All;
Does anyone know an inexpensive why to adapt a microscope to take
digital pictures of parts of assemblies PCB's.
Regards
Bob Torres
-----Original Message-----
From: McMullen, Kerry [mailto:[log in to unmask]]
Sent: Tuesday, April 23, 2002 12:14 PM
To: [log in to unmask]
Subject: Re: [TN] BGA Microscopes
Hi Al,
Try www.minimicrostencil.com They have a mini-mirror BGA inspection tool.
Works pretty good with a scope. Can look at the first row of balls all
around the BGA. We use it for incoming inspection.
Kerry
-----Original Message-----
From: [log in to unmask] [mailto:[log in to unmask]]
Sent: Tuesday, April 23, 2002 11:28 AM
To: [log in to unmask]
Subject: [TN] BGA Microscopes
Hello Technetters,
I'm familiar with the ERSA Scope.
Any experience on the ERSA or recommendations on other similar equipment.
I currently have X-ray capability, but would like to peek under the BGA and
see those balls.
Al
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Date: Tue, 23 Apr 2002 23:11:38 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Ken Carlile <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Ken Carlile <[log in to unmask]>
Subject: Freeze Spray Trouble Shooting
We recently received a prototype batch of 4 boards and experienced 4 for 4
failing test. Our techs sprayed down certain chips with Freeze Spray and
the board began working properly, at least for a short period of time. I
have checked prior tech net postings and have found fantastic responses as
to why Freeze Spray can damage a the IC or board, but can anyone explain why
they would begin functioning properly. Being a rookie component engineer I
can fully understand the issues related to freeze spray, but out techs and
design engineers are just going to point the finger since their units work
when sprayed. To further complicate the matter the chips that are being
sprayed are not all the same manufacturer and I can easily rule out a
component failure. Our senior engineer thinks that it may be timing related
since the main circuit being froze is the Altera PLD (20K400E) and related
circuitry.
Can anyone defend the use of Freeze Spray?
Can anyone present a logical failure mechanism?
/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\
The best Freeze Spray argument to date was Werner Engelmaier's:
http://jefry.ipc.org/scripts/wa.exe?A2=ind9907&L=TechNet&D=0&m=23823&P=55370
However this points to failure after spray not the opposite.
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Date: Tue, 23 Apr 2002 22:57:36 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Peter Lee <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Peter Lee <[log in to unmask]>
Subject: PCB Drill press
In-Reply-To: <[log in to unmask]>
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Hello,
Does anyone know of a table-top drill press with precision location for
proto PCB drilling?
I am looking for drilling ~0.020" dia holes with +/- 0.003" max drill
run-out (straightness at drill end) and accuracy in x-y location. The
holes are used to attach thermal-couples for BGA profiling.
Rgds,
Peter
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<p class=3DMsoNormal><font size=3D2 color=3Dnavy face=3DArial><span =
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10.0pt;font-family:Arial;color:navy'>Hello,<o:p></o:p></span></font></p>
<p class=3DMsoNormal><font size=3D2 color=3Dnavy face=3DArial><span =
style=3D'font-size:
10.0pt;font-family:Arial;color:navy'><o:p> </o:p></span></font></p>
<p class=3DMsoNormal><font size=3D2 color=3Dnavy face=3DArial><span =
style=3D'font-size:
10.0pt;font-family:Arial;color:navy'>Does anyone know of a table-top =
drill
press with precision location for proto PCB =
drilling?<o:p></o:p></span></font></p>
<p class=3DMsoNormal><font size=3D2 color=3Dnavy face=3DArial><span =
style=3D'font-size:
10.0pt;font-family:Arial;color:navy'>I am looking for drilling =
~0.020” <span
class=3DSpellE>dia</span> holes with +/- 0.003” max drill run-out
(straightness at drill end) and accuracy in x-y location. The holes are =
used to
attach thermal-couples for BGA profiling.<o:p></o:p></span></font></p>
<p class=3DMsoNormal><font size=3D3 color=3Dnavy face=3D"Times New =
Roman"><span
style=3D'font-size:12.0pt;color:navy'><o:p> </o:p></span></font></p>=
<p class=3DMsoNormal><font size=3D3 color=3Dnavy face=3D"Times New =
Roman"><span
style=3D'font-size:12.0pt;color:navy'><o:p> </o:p></span></font></p>=
<p class=3DMsoNormal><span class=3DSpellE><font size=3D2 color=3Dnavy =
face=3DArial><span
style=3D'font-size:10.0pt;font-family:Arial;color:navy'>Rgds</span></font=
></span><font
size=3D2 color=3Dnavy face=3DArial><span =
style=3D'font-size:10.0pt;font-family:Arial;
color:navy'>,<o:p></o:p></span></font></p>
<p class=3DMsoNormal><font size=3D2 color=3Dnavy face=3DArial><span =
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Date: Wed, 24 Apr 2002 09:58:56 +0100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Geoff Layhe <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Geoff Layhe <[log in to unmask]>
Subject: Re: PREPREG
X-To: "Marsico, James" <[log in to unmask]>
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Jim,
I guess most fabricators would say don't specify prepreg types - unless you
have a real reason for doing so. It's best to specify dielectric spacings
only, even for a controlled impedance board.
Prepregs vary from manufacturer to another, also the finished thickness is
dependant on a number of factors in board fabrication such as bonding
pressure, vacuum and heat up rate.
You can find info on glass styles at www.ppg.com and www.bgf.com
Most of the laminators give pre-preg details on their web sites.
I Have some general info on prepreg if you are interested.
regards
Geoff Layhe
www.lamar-uk.co.uk
-----Original Message-----
From: Marsico, James [mailto:[log in to unmask]]
Sent: 23 April 2002 21:06
To: [log in to unmask]
Subject: [TN] PREPREG
Hello, Technetters:
I'm very naive when it comes to prepreg, so I'll go to the experts. Is
there a list available of prepreg designations (i.e. 2313, 1080, 106, etc.)
with the respective properties? Will a stack-up of the three prepregs
mentioned yield a thickness of .006 inches? Where can I find information on
hot to specify prepreg layers in a PWB?
Thanks in advance,
Jim Marsico
Senior Engineer
Production Engineering
EDO Electronics Systems Group
[log in to unmask] <mailto:[log in to unmask]>
631-595-5879
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Date: Wed, 24 Apr 2002 07:10:02 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Marsico, James" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Marsico, James" <[log in to unmask]>
Subject: Re: Via Plug
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
John, We've looked into the sand thing a while ago, and found that just by
increasing the copper plating in the hole to 2 mils will give you far better
thermal performance than any thermally conductive epoxy for hole fill.
Jim Marsico
Senior Engineer
Production Engineering
EDO Electronics Systems Group
[log in to unmask] <mailto:[log in to unmask]>
631-595-5879
-----Original Message-----
From: John Foster [SMTP:[log in to unmask]]
Sent: Tuesday, April 23, 2002 3:07 PM
To: [log in to unmask]
Subject: [TN] Via Plug
Hello, I am new to this listserver. I must say that it is very
informative. I wish I had known of it long ago.
I have a question about via plugging. Right now
our board vendor is doing our via plugs with
I guess with a standard epoxy. We are trying
to find a solution that would give us a much
better thermal performance.
We are looking at silver epoxy and this
material from Dupont. Does anyone know of
some material that would give us a really good
thermal performance. We are in a commercial
environment. So the material does not have to
meet industrial specs.
Any input on this matter would be greatly '
appreciated.
Thank You
John Foster
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Date: Wed, 24 Apr 2002 07:03:15 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: PREPREG
X-To: [log in to unmask]
I created and have used the following table for years and all my qualified
fabricators indulge me as I use only these glass styles and resin contents
with the rules indicated as no 7628 use but when "sandwiched" between more
resin rich types. Caveats worked out concurrently but when done, my master
drawing notes require, as an example, TDR correlation with X-Sections and
the materials required in the construction on the master drawing.
I have other tables of similar nature and my master drawing notes. Some of
you asked for them and I'm offering them again if you ask off line,
MooMan
TABLE I
Core Chart For Dimensional Stability,
MLB Laminate Integrity, And Impedance Control
REQUIREMENT
PREFERRED NOT PREFERRED
PREG THICKNESS/" GLASS STYLE/% RESIN - SINGLE PLY
0.0020
106 (70%)
0.0025
1080 (65%)
0.0040
2113 (58%)
0.0050
2116 (53%)
0.0070
7628 (43%)
DIELECTRIC THICKNESS/" GLASS STYLE - MULTI PLY
0.005 106, 2113 1080,1080
0.006 1080, 2113 106,106,106
0.007 1080, 2116 7628
0.008 2113, 2116 2113,1080,2113
0.009 2116, 2116 1080,2116,1080
0.010 2116, 2116 1080,2116,1080
0.011 2113, 1080, 2113 106,7628,106
0.012 1080, 7628, 1080 2113,2113,2113
0.013
2113, 7628, 2113 7628,7628
0.014 2113, 7628, 2113 7628,7628
0.015 2113, 7628, 2113
0.016 2113, 7628, 2113 or use 2116,7628,2116
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Date: Wed, 24 Apr 2002 20:03:59 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
[log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: PCB Drill press
X-To: Peter Lee <[log in to unmask]>
MIME-Version: 1.0
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--=_alternative 0041260F48256BA5_=
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dear peter,
just look to FARNELL CATALOGUE 2001 book 2
=20
Ricky M. Javier
RF PCC Process Engineering
Philips Semiconductors Phils., Inc.
Tel. Nos.: (6349) 5430001 to 25 ext. 288
(632) 8445139 ext. 288
Fax Nos.: (632) 8445248/(6349) 5430027
e-mail : [log in to unmask]
Peter Lee <[log in to unmask]>
Sent by: TechNet <[log in to unmask]>
04-24-2002 01:57 PM
Please respond to "TechNet E-Mail Forum."; Please respond to Peter Lee
=20
To: [log in to unmask]
cc: (bcc: Enrique M Javier/CUB/SC/PHILIPS)
Subject: [TN] PCB Drill press
Classification:=20
Hello,
=20
Does anyone know of a table-top drill press with precision location for=20
proto PCB drilling?
I am looking for drilling ~0.020" dia holes with +/- 0.003" max drill=20
run-out (straightness at drill end) and accuracy in x-y location. The=20
holes are used to attach thermal-couples for BGA profiling.
=20
=20
Rgds,
Peter
=20
--=_alternative 0041260F48256BA5_=
Content-Type: text/html; charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
<br><font size=3D2 face=3D"sans-serif">dear peter,</font>
<br>
<br><font size=3D2 face=3D"sans-serif"> just loo=
k to FARNELL CATALOGUE 2001 book 2</font>
<br><font size=3D2 face=3D"sans-serif"> </font>
<br><font size=3D2 face=3D"sans-serif"><br>
<br>
Ricky M. Javier<br>
RF PCC Process Engineering<br>
Philips Semiconductors Phils., Inc.<br>
Tel. Nos.: (6349) 5430001 to 25 ext. 288<br>
(632)=
8445139 ext. 288<br>
Fax Nos.: (632) 8445248/(6349) 5430027<br>
e-mail : [log in to unmask]<br>
<br>
</font>
<br>
<br>
<br>
<table width=3D100%>
<tr valign=3Dtop>
<td>
<td><font size=3D1 face=3D"sans-serif"><b>Peter Lee <[log in to unmask]>=
;</b></font>
<br><font size=3D1 face=3D"sans-serif">Sent by: TechNet <[log in to unmask]
></font>
<p><font size=3D1 face=3D"sans-serif">04-24-2002 01:57 PM</font>
<br><font size=3D1 face=3D"sans-serif">Please respond to "TechNet E-Ma=
il Forum."; Please respond to Peter Lee</font>
<br>
<td><font size=3D1 face=3D"Arial"> </font>
<br><font size=3D1 face=3D"sans-serif"> To: &nbs=
p; [log in to unmask]</font>
<br><font size=3D1 face=3D"sans-serif"> cc: &nbs=
p; (bcc: Enrique M Javier/CUB/SC/PHILIPS)</font>
<br><font size=3D1 face=3D"sans-serif"> Subject:=
[TN] PCB Drill press</font>
<p><font size=3D1 face=3D"sans-serif"> Classific=
ation: </font>
<br></table>
<br>
<br>
<br><font size=3D2 color=3D#000080 face=3D"Arial">Hello,</font>
<p><font size=3D2 color=3D#000080 face=3D"Arial"> </font>
<p><font size=3D2 color=3D#000080 face=3D"Arial">Does anyone know of a tabl=
e-top drill press with precision location for proto PCB drilling?</font>
<p><font size=3D2 color=3D#000080 face=3D"Arial">I am looking for drilling =
~0.020" dia holes with +/- 0.003" max drill run-out (straightness at drill =
end) and accuracy in x-y location. The holes are used to attach thermal-cou=
ples for BGA profiling.</font>
<p><font size=3D3 color=3D#000080 face=3D"Times New Roman"> </font>
<p><font size=3D3 color=3D#000080 face=3D"Times New Roman"> </font>
<p><font size=3D2 color=3D#000080 face=3D"Arial">Rgds,</font>
<p><font size=3D2 color=3D#000080 face=3D"Arial">Peter</font>
<p><font size=3D2 color=3D#000080 face=3D"Arial"> </font>
<p>
<p>
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Date: Wed, 24 Apr 2002 08:16:20 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Rob Legg <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Rob Legg <[log in to unmask]>
Subject: Re: Freeze Spray Trouble Shooting
X-To: Ken Carlile <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
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This is a tool only.
The non-function should be diagnosable to more orders of magnitude of
accuracy than you are stating. if it is timing only.
If the freeze spray trick is repeatable, a competent design engineer should
be able to give you more informational symptoms than just "it goes now".
That's how you'll find your answers using this tool.
RL
RL
----- Original Message -----
From: "Ken Carlile" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Wednesday, April 24, 2002 12:11 AM
Subject: [TN] Freeze Spray Trouble Shooting
> We recently received a prototype batch of 4 boards and experienced 4 for 4
> failing test. Our techs sprayed down certain chips with Freeze Spray and
> the board began working properly, at least for a short period of time. I
> have checked prior tech net postings and have found fantastic responses as
> to why Freeze Spray can damage a the IC or board, but can anyone explain
why
> they would begin functioning properly. Being a rookie component engineer
I
> can fully understand the issues related to freeze spray, but out techs and
> design engineers are just going to point the finger since their units work
> when sprayed. To further complicate the matter the chips that are being
> sprayed are not all the same manufacturer and I can easily rule out a
> component failure. Our senior engineer thinks that it may be timing
related
> since the main circuit being froze is the Altera PLD (20K400E) and related
> circuitry.
>
> Can anyone defend the use of Freeze Spray?
>
> Can anyone present a logical failure mechanism?
>
> /\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\
>
> The best Freeze Spray argument to date was Werner Engelmaier's:
>
http://jefry.ipc.org/scripts/wa.exe?A2=ind9907&L=TechNet&D=0&m=23823&P=55370
>
> However this points to failure after spray not the opposite.
>
> --------------------------------------------------------------------------
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Date: Wed, 24 Apr 2002 08:35:44 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Jeff Ferry <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Jeff Ferry <[log in to unmask]>
Subject: Re: PCB Drill press
X-To: Peter Lee <[log in to unmask]>
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Peter,
Check out Servo Products. They make excellent table top drill presses,
although a bit expensive. We must have a dozen or more on our ship floor
being used every day. Go to: <http://www.servoproductsco.com>
http://www.servoproductsco.com
Jeff Ferry
CEO
Circuit Technology Center, Inc.
http://www.circuittechctr.com <http://www.circuittechctr.com>
[log in to unmask]
978-374-5000
Sign up for our Free E-mail Newsletter at:
http://www.circuittechctr.com/general/free_email.htm
<http://www.circuittechctr.com/general/free_email.htm>
-----Original Message-----
From: Peter Lee [mailto:[log in to unmask]]
Sent: Wednesday, April 24, 2002 1:58 AM
To: [log in to unmask]
Subject: [TN] PCB Drill press
Hello,
Does anyone know of a table-top drill press with precision location for
proto PCB drilling?
I am looking for drilling ~0.020" dia holes with +/- 0.003" max drill
run-out (straightness at drill end) and accuracy in x-y location. The holes
are used to attach thermal-couples for BGA profiling.
Rgds,
Peter
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<DIV><SPAN class=3D310353212-24042002><FONT =
size=3D2>Peter,</FONT></SPAN></DIV>
<DIV><SPAN class=3D310353212-24042002><FONT =
size=3D2></FONT></SPAN> </DIV>
<DIV><SPAN class=3D310353212-24042002><FONT size=3D2>Check out Servo =
Products. They=20
make excellent table top drill presses, although a bit expensive. We =
must have a=20
dozen or more on our ship floor being used every day. Go to: </FONT><A=20
href=3D"http://www.servoproductsco.com"><FONT=20
size=3D2>http://www.servoproductsco.com</FONT></A></SPAN></DIV>
<DIV><SPAN class=3D310353212-24042002><FONT face=3D"Courier New" =
size=3D2><FONT=20
face=3DArial size=3D2></FONT></FONT></SPAN> </DIV>
<DIV><SPAN class=3D310353212-24042002><FONT face=3D"Courier New" =
size=3D2><FONT=20
face=3DArial size=3D2>Jeff Ferry<BR>CEO<BR>Circuit Technology Center, =
Inc.<BR><A=20
href=3D"http://www.circuittechctr.com">http://www.circuittechctr.com</A>=
<BR>[log in to unmask]<BR>978-374-5000<BR><BR>Sign=20
up for our Free E-mail Newsletter at:<BR><A=20
href=3D"http://www.circuittechctr.com/general/free_email.htm">http://www=
.circuittechctr.com/general/free_email.htm</A></FONT><BR></DIV></FONT><=
/SPAN>
<DIV class=3DOutlookMessageHeader dir=3Dltr align=3Dleft><FONT =
face=3DTahoma=20
size=3D2>-----Original Message-----<BR><B>From:</B> Peter Lee=20
[mailto:[log in to unmask]]<BR><B>Sent:</B> Wednesday, April 24, 2002 =
1:58=20
AM<BR><B>To:</B> [log in to unmask]<BR><B>Subject:</B> [TN] PCB Drill=20
press<BR><BR></FONT></DIV>
<DIV class=3DSection1>
<P class=3DMsoNormal><FONT face=3DArial color=3Dnavy size=3D2><SPAN=20
style=3D"FONT-SIZE: 10pt; COLOR: navy; FONT-FAMILY: =
Arial">Hello,<o:p></o:p></SPAN></FONT></P>
<P class=3DMsoNormal><FONT face=3DArial color=3Dnavy size=3D2><SPAN=20
style=3D"FONT-SIZE: 10pt; COLOR: navy; FONT-FAMILY: =
Arial"><o:p> </o:p></SPAN></FONT></P>
<P class=3DMsoNormal><FONT face=3DArial color=3Dnavy size=3D2><SPAN=20
style=3D"FONT-SIZE: 10pt; COLOR: navy; FONT-FAMILY: Arial">Does anyone =
know of a=20
table-top drill press with precision location for proto PCB=20
drilling?<o:p></o:p></SPAN></FONT></P>
<P class=3DMsoNormal><FONT face=3DArial color=3Dnavy size=3D2><SPAN=20
style=3D"FONT-SIZE: 10pt; COLOR: navy; FONT-FAMILY: Arial">I am looking =
for=20
drilling ~0.020" <SPAN class=3DSpellE>dia</SPAN> holes with +/- 0.003" =
max drill=20
run-out (straightness at drill end) and accuracy in x-y location. The =
holes are=20
used to attach thermal-couples for BGA =
profiling.<o:p></o:p></SPAN></FONT></P>
<P class=3DMsoNormal><FONT face=3D"Times New Roman" color=3Dnavy =
size=3D3><SPAN=20
style=3D"FONT-SIZE: 12pt; COLOR: =
navy"><o:p> </o:p></SPAN></FONT></P>
<P class=3DMsoNormal><FONT face=3D"Times New Roman" color=3Dnavy =
size=3D3><SPAN=20
style=3D"FONT-SIZE: 12pt; COLOR: =
navy"><o:p> </o:p></SPAN></FONT></P>
<P class=3DMsoNormal><SPAN class=3DSpellE><FONT face=3DArial =
color=3Dnavy size=3D2><SPAN=20
style=3D"FONT-SIZE: 10pt; COLOR: navy; FONT-FAMILY: =
Arial">Rgds</SPAN></FONT></SPAN><FONT=20
face=3DArial color=3Dnavy size=3D2><SPAN=20
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<P class=3DMsoNormal><FONT face=3DArial color=3Dnavy size=3D2><SPAN=20
style=3D"FONT-SIZE: 10pt; COLOR: navy; FONT-FAMILY: =
Arial"><o:p> </o:p></SPAN></FONT></P></DIV></BODY></HTML>
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=========================================================================
Date: Wed, 24 Apr 2002 08:04:47 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Andre Leclair <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Andre Leclair <[log in to unmask]>
Subject: Re: Shorts in PLCC Sockets
X-To: [log in to unmask]
On Tue, 23 Apr 2002 16:34:48 -0400, Guy Ramsey <[log in to unmask]> wrote:
>I have seen this condition caused by over active chipwave and excessive
>setting on an omega wave. The omega wave is a vibrating plate in the
>solderwave that produces turbulence in the lambda wave (main wave) that is
>perpendicular to the normal wave dynamics. The action forces solder up
>through the board, bridges form at the heels of the springs that form the
>socket contacts.
>
>> -----Original Message-----
>> From: TechNet [mailto:[log in to unmask]]On Behalf Of Andre Leclair
>> Sent: Tuesday, April 23, 2002 2:27 PM
>> To: [log in to unmask]
>> Subject: Re: [TN] Shorts in PLCC Sockets
>>
>>
>> base on your description, the following questions come to mind:
>> 1. Could the part have come with the condition?
>> We are investigating with the part manufacture with no results as of yet.
>> They are
>>
>> 2. Is there an open area in the PCB, near the socket in question,
through
>> wich solder can over flow and get underneath the socket?
>>
>> There are no holes in the PCB near the socket where solder extra solder
>> could have migrated under the socket and then under the pin
>> retainer. When
>> the socket was removed there was now evidance that extra solder had been
>> between the board and the socket base. For the amount of solder that was
>> between the base and the main body of the socket there should have been
>> evidance of solder ( the plastic body marks very easily at 500'F).
>>
>> ------------------------------------------------------------------
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http://listserv.ipc.org/archives
>> Please visit IPC web site http://www.ipc.org/html/forum.htm for
additional
>> information, or contact Keach Sasamori at [log in to unmask] or
>> 847-509-9700 ext.5315
>> ------------------------------------------------------------------
>> ---------------
>>
>
>---------------------------------------------------------------------------
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------
The wave setup used is an Electrovert Ultrapak 445
Flux Lonco 3355-11
Conveyer speed 5.6FPM Airknife on
Lamda 6-9rpm
chip wave 6-9rpm
Omega wave 70%
Could this be the cause? I checked another 12 units and found the exact
same short in the same general area inside the socket but no solder between
the PCB and the base of the socket(44 pin). The other 3 PLCC sockets(32
pin) on the board that are only 2-3 inches away are perfectly fine.
The 2 previous 1000pcs runs had no problems using the above settings.
Any SMT parts near the sockets are at least .150" from the pins and are all
603 or 402 parts.
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=========================================================================
Date: Wed, 24 Apr 2002 08:29:01 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Kathy Kuhlow <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Kathy Kuhlow <[log in to unmask]>
Subject: Re: Microscopes
Mime-Version: 1.0
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This works well for me. I take any microscope (mantis too) and get a =
digital camera. Put the part that you want to photo under the scope then =
take the camera to one of the eye pieces or to one side of a mantis. Be =
patient and make slow movements left and right the camera will be able to =
look through the eye piece. I have been extremely successful using a =
simple digital camera and with a scope that has a wide range I can take =
whatever detail photo I need. =20
I suppose you can also buy something but I haven't been able to justify a =
more pretty set up. =20
Kathy =20
--=_0954FE28.680964D8
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<META content="MSHTML 6.00.2715.400" name=GENERATOR></HEAD>
<BODY style="MARGIN-TOP: 2px; FONT: 10pt MS Sans Serif; MARGIN-LEFT: 2px">
<DIV>This works well for me. I take any microscope (mantis too) and get a
digital camera. Put the part that you want to photo under the scope
then take the camera to one of the eye pieces or to one side of a mantis.
Be patient and make slow movements left and right the camera will be able to
look through the eye piece. I have been extremely successful using a
simple digital camera and with a scope that has a wide range I can take whatever
detail photo I need. </DIV>
<DIV> </DIV>
<DIV>I suppose you can also buy something but I haven't been able to justify a
more pretty set up. </DIV>
<DIV> </DIV>
<DIV>Kathy </DIV></BODY></HTML>
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Date: Wed, 24 Apr 2002 15:58:36 +0200
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Freeze Spray Trouble Shooting
X-To: Ken Carlile <[log in to unmask]>
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
Freezing an IC will modify its physical dimension but also will change its
electrical property.
From what you said I would guess that one of the timing of your design is
very marginal and most probably too slow.
When cooling some of the components the electronics actually goes faster
and, the timing being then correct, your design start to behave correctly.
Your engineer should review the timing of the design and can actually check
on the board what happens to the signals when applying the freeze spray.
But be carefull that probing on some signal will also change their
timing...
It may also well be that the timing problem is inside the PLD, to solve
that one the engineer got to redo some simulation with min and max timing.
Now freeze spray can also induce other circuitry to work. For example, an
analog circuit could start working only when cooled down because it was too
hot under normal ambient condition. Too hot because the design or assembly
is incorrect and the component is actually used outside its maximum
temperature rating...
The best way to find which component is faulty, is to use a slim tube and
spray directly on each component, making sure not to freeze the adjacent
one.
The component that will show the most effect on the fonctionnality is
likely to be the one you should look at.
Hope this helps,
Jean-Luc Lehmann
We recently received a prototype batch of 4 boards and experienced 4 for 4
failing test. Our techs sprayed down certain chips with Freeze Spray and
the board began working properly, at least for a short period of time. I
have checked prior tech net postings and have found fantastic responses as
to why Freeze Spray can damage a the IC or board, but can anyone explain
why
they would begin functioning properly. Being a rookie component engineer I
can fully understand the issues related to freeze spray, but out techs and
design engineers are just going to point the finger since their units work
when sprayed. To further complicate the matter the chips that are being
sprayed are not all the same manufacturer and I can easily rule out a
component failure. Our senior engineer thinks that it may be timing
related
since the main circuit being froze is the Altera PLD (20K400E) and related
circuitry.
Can anyone defend the use of Freeze Spray?
Can anyone present a logical failure mechanism?
/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\
The best Freeze Spray argument to date was Werner Engelmaier's:
http://jefry.ipc.org/scripts/wa.exe?A2=ind9907&L=TechNet&D=0&m=23823&P=55370
However this points to failure after spray not the opposite.
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=========================================================================
Date: Wed, 24 Apr 2002 14:54:47 +0100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Eric Christison <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Eric Christison <[log in to unmask]>
Organization: STMicroelectronics
Subject: Re: Freeze Spray Trouble Shooting
X-To: [log in to unmask]
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Sounds to me like a marginal design.
The devices heat up and some property eg frequency, capacitance starts to drift. You freeze it and the
parameter moves the other way and comes back into spec. The components slowly warm up again and the
board ceases to function.
Find out what's temperature dependent on those components and therein lies your answer.
Regards,
[log in to unmask] wrote:
> This is a tool only.
>
> The non-function should be diagnosable to more orders of magnitude of
> accuracy than you are stating. if it is timing only.
>
> If the freeze spray trick is repeatable, a competent design engineer should
> be able to give you more informational symptoms than just "it goes now".
> That's how you'll find your answers using this tool.
>
> RL
>
> RL
> ----- Original Message -----
> From: "Ken Carlile" <[log in to unmask]>
> To: <[log in to unmask]>
> Sent: Wednesday, April 24, 2002 12:11 AM
> Subject: [TN] Freeze Spray Trouble Shooting
>
> > We recently received a prototype batch of 4 boards and experienced 4 for 4
> > failing test. Our techs sprayed down certain chips with Freeze Spray and
> > the board began working properly, at least for a short period of time. I
> > have checked prior tech net postings and have found fantastic responses as
> > to why Freeze Spray can damage a the IC or board, but can anyone explain
> why
> > they would begin functioning properly. Being a rookie component engineer
> I
> > can fully understand the issues related to freeze spray, but out techs and
> > design engineers are just going to point the finger since their units work
> > when sprayed. To further complicate the matter the chips that are being
> > sprayed are not all the same manufacturer and I can easily rule out a
> > component failure. Our senior engineer thinks that it may be timing
> related
> > since the main circuit being froze is the Altera PLD (20K400E) and related
> > circuitry.
> >
> > Can anyone defend the use of Freeze Spray?
> >
> > Can anyone present a logical failure mechanism?
> >
> > /\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\
> >
> > The best Freeze Spray argument to date was Werner Engelmaier's:
> >
> http://jefry.ipc.org/scripts/wa.exe?A2=ind9907&L=TechNet&D=0&m=23823&P=55370
> >
> > However this points to failure after spray not the opposite.
> >
> > --------------------------------------------------------------------------
> -------
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> ext.5315
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> >
>
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> ---------------------------------------------------------------------------------
--
Eric Christison
Mechanical Engineer
STMicroelectronics
33 Pinkhill
Edinburgh
EH12 7BF
Tel: (0)131 336 6165
Fax: (0)131 336 6001
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<html>
Sounds to me like a marginal design.
<p>The devices heat up and some property eg frequency, capacitance starts
to drift. You freeze it and the parameter moves the other way and comes
back into spec. The components slowly warm up again and the board ceases
to function.
<p>Find out what's temperature dependent on those components and therein
lies your answer.
<p>Regards,
<br>
<br>
<p>[log in to unmask] wrote:
<blockquote TYPE=CITE>This is a tool only.
<p>The non-function should be diagnosable to more orders of magnitude of
<br>accuracy than you are stating. if it is timing only.
<p>If the freeze spray trick is repeatable, a competent design engineer
should
<br>be able to give you more informational symptoms than just "it goes
now".
<br>That's how you'll find your answers using this tool.
<p>RL
<p>RL
<br>----- Original Message -----
<br>From: "Ken Carlile" <[log in to unmask]>
<br>To: <[log in to unmask]>
<br>Sent: Wednesday, April 24, 2002 12:11 AM
<br>Subject: [TN] Freeze Spray Trouble Shooting
<p>> We recently received a prototype batch of 4 boards and experienced
4 for 4
<br>> failing test. Our techs sprayed down certain chips with Freeze
Spray and
<br>> the board began working properly, at least for a short period of
time. I
<br>> have checked prior tech net postings and have found fantastic responses
as
<br>> to why Freeze Spray can damage a the IC or board, but can anyone
explain
<br>why
<br>> they would begin functioning properly. Being a rookie component
engineer
<br>I
<br>> can fully understand the issues related to freeze spray, but out
techs and
<br>> design engineers are just going to point the finger since their units
work
<br>> when sprayed. To further complicate the matter the chips that
are being
<br>> sprayed are not all the same manufacturer and I can easily rule out
a
<br>> component failure. Our senior engineer thinks that it may be
timing
<br>related
<br>> since the main circuit being froze is the Altera PLD (20K400E) and
related
<br>> circuitry.
<br>>
<br>> Can anyone defend the use of Freeze Spray?
<br>>
<br>> Can anyone present a logical failure mechanism?
<br>>
<br>> /\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\
<br>>
<br>> The best Freeze Spray argument to date was Werner Engelmaier's:
<br>>
<br><a href="http://jefry.ipc.org/scripts/wa.exe?A2=ind9907&L=TechNet&D=0&m=23823&P=55370">http://jefry.ipc.org/scripts/wa.exe?A2=ind9907&L=TechNet&D=0&m=23823&P=55370</a>
<br>>
<br>> However this points to failure after spray not the opposite.
<br>>
<br>> --------------------------------------------------------------------------
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1.8d
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text in
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<br>SET Technet NOMAIL
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<br>> Search the archives of previous posts at: <a href="http://listserv.ipc.org/archives">http://listserv.ipc.org/archives</a>
<br>> Please visit IPC web site <a href="http://www.ipc.org/html/forum.htm">http://www.ipc.org/html/forum.htm</a>
for additional
<br>> information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700
<br>ext.5315
<br>> --------------------------------------------------------------------------
<br>-------
<br>>
<p>---------------------------------------------------------------------------------
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<br>Please visit IPC web site <a href="http://www.ipc.org/html/forum.htm">http://www.ipc.org/html/forum.htm</a>
for additional
<br>information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700
ext.5315
<br>---------------------------------------------------------------------------------</blockquote>
<p>--
<br>Eric Christison
<br>Mechanical Engineer
<br>STMicroelectronics
<br>33 Pinkhill
<br>Edinburgh
<br>EH12 7BF
<p>Tel: (0)131 336 6165
<br>Fax: (0)131 336 6001
<br> </html>
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=========================================================================
Date: Wed, 24 Apr 2002 10:06:29 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
David Fish <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: David Fish <[log in to unmask]>
Subject: Re: Bar Code Standards
X-To: "Randy Bock Sr." <[log in to unmask]>
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For background look at: "The Bar Code Book" Roger C. Palmer, Helmers
Publishing, 4e, 2001 [0911261133] amazon.com, SMTA, publisher, etc
----- Original Message -----
From: "Randy Bock Sr." <[log in to unmask]>
To: <[log in to unmask]>
Sent: Tuesday, April 23, 2002 4:37 AM
Subject: Re: [TN] Bar Code Standards
> We use bar codes on our boards and have allot of trouble with defining
some
> sort of specification for it. Info will help, thanks..
>
>
> ----- Original Message -----
> From: Jack Bryant <[log in to unmask]>
> To: <[log in to unmask]>
> Sent: Monday, April 22, 2002 8:49 PM
> Subject: Re: [TN] Bar Code Standards
>
>
> > David,
> >
> > Within the general IPC guideline and generally speaking, "human
readable"
> > and "barcode", assembly no., date code, unique serial no. and CM
> identifier
> > will usually suffice the basic needs in a small footprint. Having worked
> for
> > a CM designing barcode labels for assembly processes, customer products,
> and
> > internal procedures the labels are personal to each customer with
creative
> > ways of building intelligence into the limited barcode encrypted data.
> Don't
> > know of a standard barcode format either. Some of the common barcodes
I've
> > seen would be the UPC code with check digit commonly seen on consumer
> > products, code 39, and code 128 to name a few, code 128 being the most
> > flexible. However, now with the introduction of the 2D barcode labels
> short
> > stories can be encrypted into barcodes that are only 1" wide and 1" long
> and
> > hold complete paragraphs of data never before considered as part of
> > sub-assembly labeling information. Barcode labels don't have to be just
> > black and white lines anymore.
> >
> > AJB
> >
> >
> >
> >
> > ----- Original Message -----
> > From: "Bernard, David" <[log in to unmask]>
> > To: <[log in to unmask]>
> > Sent: Monday, April 22, 2002 4:54 AM
> > Subject: [TN] Bar Code Standards
> >
> >
> > > Dear Technetters,
> > >
> > > Can anybody tell me if there are any recommended standards for the
> > > suggested data content within bar codes used on boards?
> > >
> > > Thank you,
> > >
> > > David
> > >
> > > David Bernard
> > >
> > > Dage Holdings Plc
> > > Rabans Lane
> > > Aylesbury
> > > Buckinghamshire
> > > HP19 8RG
> > > United Kingdom
> > >
> > > Tel: 01296 317860 - Direct
> > > Tel: 01296 317800
> > > Fax: 01296 435408
> > > E: [log in to unmask]
> > > W: www.dage-group.com
> > >
> > >
> > >
> > > intY (www.inty.com) has automatically scanned this email using Sophos
> > Anti-Virus
> > >
> >
>
> --------------------------------------------------------------------------
> > -------
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> > > Please visit IPC web site http://www.ipc.org/html/forum.htm for
> additional
> > > information, or contact Keach Sasamori at [log in to unmask] or
847-509-9700
> > ext.5315
> >
>
> --------------------------------------------------------------------------
> > -------
> > >
> >
>
> --------------------------------------------------------------------------
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>
> --------------------------------------------------------------------------
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> >
>
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Date: Wed, 24 Apr 2002 07:22:32 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Carl VanWormer <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Carl VanWormer <[log in to unmask]>
Subject: Re: Freeze Spray Trouble Shooting
X-To: Ken Carlile <[log in to unmask]>
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As to the cause of your problems, I vote for timing problems, with a close
second guess at system noise caused by impedance mismatch on long control
signal lines.
I'm Carl and I'm a Freeze Spray user . . .
Now that I've got that off my chest, I'd like to say that I seldom wreck
stuff, and can usually find thermal mechanical intermittents and
(particularly) timing problems. Frozen parts seem to have faster transition
edges. A long time ago, I was able to make our 4 MHz Z-80 processor system
work at 7.8 MHz by freezing the processor, EPROM, and RAM chips (with a
variable oscillator for testing). Recently, I've found that I could fix (or
cause to fail) a new design by squirting the Altera (EPLD) or processor.
The culprit was "timing" and a poorly designed (overloaded) set of control
and bus lines. The difference in timing between the Altera latching in the
correct and incorrect data was seen to be about 1/2 nano-second. By
selective heating (and/or cooling) of the various chips, I could "adjust"
the timing to make the device work or fail. Of course, we had to fix the
timing problem, but my first line of discovery is (often) Freeze Spray.
When I've run out of the stuff, I grab the "Dust-Off" can and run it in
"inverted" mode to get the Freeze Spray effect.
p.s. After reading items in this forum about BGAs and circuit cooler, I've
vowed to never squirt the BGA packages. There is waaaaaaay too much chance
of wrecking something there, since there are no leads to absorb the flex
caused by differential thermal expansions.
Carl Van Wormer
Cipher Systems
1815 NW 169th Place, Suite 5010
Beaverton, OR 97006
Phone (503)-617-7447 Fax (503)-617-6550
-----Original Message-----
From: Ken Carlile [mailto:[log in to unmask]]
Sent: Tuesday, April 23, 2002 9:12 PM
To: [log in to unmask]
Subject: [TN] Freeze Spray Trouble Shooting
We recently received a prototype batch of 4 boards and experienced 4 for 4
failing test. Our techs sprayed down certain chips with Freeze Spray and
the board began working properly, at least for a short period of time. I
have checked prior tech net postings and have found fantastic responses as
to why Freeze Spray can damage a the IC or board, but can anyone explain why
they would begin functioning properly. Being a rookie component engineer I
can fully understand the issues related to freeze spray, but out techs and
design engineers are just going to point the finger since their units work
when sprayed. To further complicate the matter the chips that are being
sprayed are not all the same manufacturer and I can easily rule out a
component failure. Our senior engineer thinks that it may be timing related
since the main circuit being froze is the Altera PLD (20K400E) and related
circuitry.
Can anyone defend the use of Freeze Spray?
Can anyone present a logical failure mechanism?
/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\
The best Freeze Spray argument to date was Werner Engelmaier's:
http://jefry.ipc.org/scripts/wa.exe?A2=ind9907&L=TechNet&D=0&m=23823&P=55370
However this points to failure after spray not the opposite.
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Date: Wed, 24 Apr 2002 09:31:51 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Charles Caswell <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Charles Caswell <[log in to unmask]>
Subject: Re: Microscopes
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This has been mentioned before but the Intel microscope for about $60 =
works. Just need a computer with USB. I haven't used it here at work but =
I have tried it at home. Magnification may be too high, or feild of view =
limited though. Depends on what you want.
Charles Caswell
Process Lead, PCB
Frontier Electronic Systems
-----Original Message-----
From: Torres, Roberto [mailto:[log in to unmask]]
Sent: Tuesday, April 23, 2002 4:21 PM
To: [log in to unmask]
Subject: [TN] Microscopes
Hi All;
Does anyone know an inexpensive why to adapt a microscope to take
digital pictures of parts of assemblies PCB's.
Regards
Bob Torres
-----Original Message-----
From: McMullen, Kerry [mailto:[log in to unmask]]
Sent: Tuesday, April 23, 2002 12:14 PM
To: [log in to unmask]
Subject: Re: [TN] BGA Microscopes
Hi Al,
Try www.minimicrostencil.com They have a mini-mirror BGA inspection =
tool.
Works pretty good with a scope. Can look at the first row of balls all
around the BGA. We use it for incoming inspection.
Kerry
-----Original Message-----
From: [log in to unmask] [mailto:[log in to unmask]]
Sent: Tuesday, April 23, 2002 11:28 AM
To: [log in to unmask]
Subject: [TN] BGA Microscopes
Hello Technetters,
I'm familiar with the ERSA Scope.
Any experience on the ERSA or recommendations on other similar =
equipment.
I currently have X-ray capability, but would like to peek under the BGA =
and
see those balls.
Al
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Date: Wed, 24 Apr 2002 10:31:12 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Edward S. Wheeler" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Edward S. Wheeler" <[log in to unmask]>
Subject: Contract House Placement Costs
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Hello everybody. We were starting to look at sending out some contract
work, and we were wondering if any of you guys using CMs had a ballpark
figure on cost per placement and / or cost per joint on surface mount
assemblies. I would just like to make sure that a place we are looking at
is not particularly over the top.
Thanks.
Ed
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Date: Wed, 24 Apr 2002 10:33:21 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Marsico, James" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Marsico, James" <[log in to unmask]>
Subject: TEMP EXTREME
MIME-Version: 1.0
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Hello Technet:
I think I may have asked this question a while ago (or something similar)
but couldn't find anything in the archives. I have a surface mount assembly
that gets installed into a top assembly housing, with covers. The test guys
want to subject this assembly to 125 degrees C for 112 hours. Assuming that
all of the components are rated for this temperature, is there anything else
that says this isn't a good idea? I'm thinking about the solder joints,
maybe decreased reliability due to excessive grain growth? How about
acrylic conformal coating? The PWB is polyimide, so this shouldn't be an
issue. Anything else?
Thanks again...
Jim Marsico
Senior Engineer
Production Engineering
EDO Electronics Systems Group
[log in to unmask] <mailto:[log in to unmask]>
631-595-5879
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Date: Wed, 24 Apr 2002 11:25:44 EDT
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Manual printing tables...
MIME-Version: 1.0
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boundary="part1_150.cd7db49.29f82878_boundary"
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Hi All,
I'm looking for an inexpensive manual printing table to use for the one'sies
two'sies that we do here, and as a last ditch back-up when our DEK goes down.
I used one called a Palomar printing table when I was out in California, and
it did a really good job.
Could use any sized frame, nice precise hinge, had X/Y micrometers to fine
tune registration... could do 20-mil pitch all day long.
Are there any others out there?
-Steve Gregory-
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<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>Hi All,
<BR>
<BR>I'm looking for an inexpensive manual printing table to use for the one'sies two'sies that we do here, and as a last ditch back-up when our DEK goes down. I used one called a Palomar printing table when I was out in California, and it did a really good job.
<BR>
<BR>Could use any sized frame, nice precise hinge, had X/Y micrometers to fine tune registration... could do 20-mil pitch all day long.
<BR>
<BR>Are there any others out there?
<BR>
<BR>-Steve Gregory-</FONT></HTML>
--part1_150.cd7db49.29f82878_boundary--
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Date: Wed, 24 Apr 2002 11:32:08 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
bonilla_d <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: bonilla_d <[log in to unmask]>
Subject: Re: Contract House Placement Costs
X-To: "Edward S. Wheeler" <[log in to unmask]>
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
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Hi Ed:
>From my point of view, it is very hard to define a cost per placement based
on a ball park figure. We are a contract Manufacturer in Puerto Rico with
two other sites in Ireland and Dominican Republic. It means that direct
labor and indirect labor costs and tax exemptions are different for each
site.
David Bonilla
Sr. Process Engineer
Manufacturing Technology Services
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Edward S. Wheeler
Sent: Wednesday, April 24, 2002 10:31 AM
To: [log in to unmask]
Subject: [TN] Contract House Placement Costs
Hello everybody. We were starting to look at sending out some contract
work, and we were wondering if any of you guys using CMs had a ballpark
figure on cost per placement and / or cost per joint on surface mount
assemblies. I would just like to make sure that a place we are looking at
is not particularly over the top.
Thanks.
Ed
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Date: Wed, 24 Apr 2002 12:12:36 EDT
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Contract House Placement Costs
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Hi Ed,
Not trying to avoid the question, but it is pretty tough to come up with a
cost per placement, or cost per solder joint figure....it all depends on the
assembly.
For instance we build a board here that has maybe 100 parts on it that costs
10 times as much to build as another board that has 900 parts on it...
The difference between the two is that the 100 part board requires that we
cut, form, and pre-tin all the leaded SMT devices (including two 352-pin
CQFP's), print paste, dispense adhesive so as to cover 70% of the area
beneath each part, place the parts and reflow, then bond the whole thing to
an aluminum heatsink. While the 900 part assembly is entirely auto-inserted
and then wave soldered...that's it.
Most places will bid the work depending on standard times it takes to do each
operation, or as close to the actuals as possible. We aren't afraid to share
those times with a customer if they think the price is too high. We'll add a
little more when faced with very complex assemblies (many BGA's, etc.) to
cover the risks one experiences when building these types of assemblies.
The other factor is the quantities of completed asemblies that you want. It
takes the same amount of time to set-up a surface mount line whether you
build 1 or a 1000,
so if you build in low quantities, the price is going to higher than larger
quantities.
But there really isn't a pat answer as to pricing by component count, or
solder joint count...
-Steve Gregory-
> Hello everybody. We were starting to look at sending out some contract
> work, and we were wondering if any of you guys using CMs had a ballpark
> figure on cost per placement and / or cost per joint on surface mount
> assemblies. I would just like to make sure that a place we are looking at
> is not particularly over the top.
>
> Thanks.
>
> Ed
>
--part1_152.cdb3892.29f83374_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>Hi Ed,
<BR>
<BR>Not trying to avoid the question, but it is pretty tough to come up with a cost per placement, or cost per solder joint figure....it all depends on the assembly.
<BR>
<BR>For instance we build a board here that has maybe 100 parts on it that costs 10 times as much to build as another board that has 900 parts on it...
<BR>
<BR>The difference between the two is that the 100 part board requires that we cut, form, and pre-tin all the leaded SMT devices (including two 352-pin CQFP's), print paste, dispense adhesive so as to cover 70% of the area beneath each part, place the parts and reflow, then bond the whole thing to an aluminum heatsink. While the 900 part assembly is entirely auto-inserted and then wave soldered...that's it.
<BR>
<BR>Most places will bid the work depending on standard times it takes to do each operation, or as close to the actuals as possible. We aren't afraid to share those times with a customer if they think the price is too high. We'll add a little more when faced with very complex assemblies (many BGA's, etc.) to cover the risks one experiences when building these types of assemblies.
<BR>
<BR>The other factor is the quantities of completed asemblies that you want. It takes the same amount of time to set-up a surface mount line whether you build 1 or a 1000,
<BR>so if you build in low quantities, the price is going to higher than larger quantities.
<BR>
<BR>But there really isn't a pat answer as to pricing by component count, or solder joint count...
<BR>
<BR>-Steve Gregory-
<BR>
<BR>
<BR><BLOCKQUOTE TYPE=CITE style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">Hello everybody. We were starting to look at sending out some contract
<BR>work, and we were wondering if any of you guys using CMs had a ballpark
<BR>figure on cost per placement and / or cost per joint on surface mount
<BR>assemblies. I would just like to make sure that a place we are looking at
<BR>is not particularly over the top.
<BR>
<BR>Thanks.
<BR>
<BR>Ed
<BR></FONT><FONT COLOR="#000000" SIZE=3 FAMILY="SANSSERIF" FACE="Arial" LANG="0"></BLOCKQUOTE>
<BR></FONT><FONT COLOR="#000000" SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0">
<BR></FONT></HTML>
--part1_152.cdb3892.29f83374_boundary--
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Date: Wed, 24 Apr 2002 12:25:04 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Randy Bock Sr." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Randy Bock Sr." <[log in to unmask]>
Subject: Re: Bar Code Standards
X-To: David Fish <[log in to unmask]>
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Thank you..
----- Original Message -----
From: David Fish <[log in to unmask]>
To: <[log in to unmask]>
Sent: Wednesday, April 24, 2002 1:06 PM
Subject: Re: [TN] Bar Code Standards
> For background look at: "The Bar Code Book" Roger C. Palmer, Helmers
> Publishing, 4e, 2001 [0911261133] amazon.com, SMTA, publisher, etc
>
>
> ----- Original Message -----
> From: "Randy Bock Sr." <[log in to unmask]>
> To: <[log in to unmask]>
> Sent: Tuesday, April 23, 2002 4:37 AM
> Subject: Re: [TN] Bar Code Standards
>
>
> > We use bar codes on our boards and have allot of trouble with defining
> some
> > sort of specification for it. Info will help, thanks..
> >
> >
> > ----- Original Message -----
> > From: Jack Bryant <[log in to unmask]>
> > To: <[log in to unmask]>
> > Sent: Monday, April 22, 2002 8:49 PM
> > Subject: Re: [TN] Bar Code Standards
> >
> >
> > > David,
> > >
> > > Within the general IPC guideline and generally speaking, "human
> readable"
> > > and "barcode", assembly no., date code, unique serial no. and CM
> > identifier
> > > will usually suffice the basic needs in a small footprint. Having
worked
> > for
> > > a CM designing barcode labels for assembly processes, customer
products,
> > and
> > > internal procedures the labels are personal to each customer with
> creative
> > > ways of building intelligence into the limited barcode encrypted data.
> > Don't
> > > know of a standard barcode format either. Some of the common barcodes
> I've
> > > seen would be the UPC code with check digit commonly seen on consumer
> > > products, code 39, and code 128 to name a few, code 128 being the most
> > > flexible. However, now with the introduction of the 2D barcode labels
> > short
> > > stories can be encrypted into barcodes that are only 1" wide and 1"
long
> > and
> > > hold complete paragraphs of data never before considered as part of
> > > sub-assembly labeling information. Barcode labels don't have to be
just
> > > black and white lines anymore.
> > >
> > > AJB
> > >
> > >
> > >
> > >
> > > ----- Original Message -----
> > > From: "Bernard, David" <[log in to unmask]>
> > > To: <[log in to unmask]>
> > > Sent: Monday, April 22, 2002 4:54 AM
> > > Subject: [TN] Bar Code Standards
> > >
> > >
> > > > Dear Technetters,
> > > >
> > > > Can anybody tell me if there are any recommended standards for the
> > > > suggested data content within bar codes used on boards?
> > > >
> > > > Thank you,
> > > >
> > > > David
> > > >
> > > > David Bernard
> > > >
> > > > Dage Holdings Plc
> > > > Rabans Lane
> > > > Aylesbury
> > > > Buckinghamshire
> > > > HP19 8RG
> > > > United Kingdom
> > > >
> > > > Tel: 01296 317860 - Direct
> > > > Tel: 01296 317800
> > > > Fax: 01296 435408
> > > > E: [log in to unmask]
> > > > W: www.dage-group.com
> > > >
> > > >
> > > >
> > > > intY (www.inty.com) has automatically scanned this email using
Sophos
> > > Anti-Virus
> > > >
> > >
> >
>
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Date: Wed, 24 Apr 2002 09:33:48 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
David Douthit <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: David Douthit <[log in to unmask]>
Subject: Re: TEMP EXTREME
X-To: "Marsico, James" <[log in to unmask]>
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--------------F67343D8763C540629CB3923
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James,
How about acrylic conformal coating?
You are so far above the Tg of acrylics that the coating can "flow", melt, evaporate, or all the above!
(Not to mention letting contaminants reach the surface!)
David A. Douthit
Manager
LoCan LLC
"Marsico, James" wrote:
> Hello Technet:
>
> I think I may have asked this question a while ago (or something similar)
> but couldn't find anything in the archives. I have a surface mount assembly
> that gets installed into a top assembly housing, with covers. The test guys
> want to subject this assembly to 125 degrees C for 112 hours. Assuming that
> all of the components are rated for this temperature, is there anything else
> that says this isn't a good idea? I'm thinking about the solder joints,
> maybe decreased reliability due to excessive grain growth? How about
> acrylic conformal coating? The PWB is polyimide, so this shouldn't be an
> issue. Anything else?
>
> Thanks again...
>
> Jim Marsico
> Senior Engineer
> Production Engineering
> EDO Electronics Systems Group
> [log in to unmask] <mailto:[log in to unmask]>
> 631-595-5879
>
> ---------------------------------------------------------------------------------
> Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
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> Please visit IPC web site http://www.ipc.org/html/forum.htm for additional
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> ---------------------------------------------------------------------------------
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<!doctype html public "-//w3c//dtd html 4.0 transitional//en">
<html>
James,
<p><i>How about acrylic conformal coating?</i>
<br>You are so far above the Tg of acrylics that the coating can "flow",
melt, evaporate, or all the above!
<br>(Not to mention letting contaminants reach the surface!)
<p>David A. Douthit
<br>Manager
<br>LoCan LLC
<br>
<p>"Marsico, James" wrote:
<blockquote TYPE=CITE>Hello Technet:
<p>I think I may have asked this question a while ago (or something similar)
<br>but couldn't find anything in the archives. I have a surface
mount assembly
<br>that gets installed into a top assembly housing, with covers.
The test guys
<br>want to subject this assembly to 125 degrees C for 112 hours.
Assuming that
<br>all of the components are rated for this temperature, is there anything
else
<br>that says this isn't a good idea? I'm thinking about the solder
joints,
<br>maybe decreased reliability due to excessive grain growth? How
about
<br>acrylic conformal coating? The PWB is polyimide, so this shouldn't
be an
<br>issue. Anything else?
<p>Thanks again...
<p>Jim Marsico
<br>Senior Engineer
<br>Production Engineering
<br>EDO Electronics Systems Group
<br>[log in to unmask] <<a href="mailto:[log in to unmask]">mailto:[log in to unmask]</a>>
<br>631-595-5879
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for additional
<br>information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700
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Date: Wed, 24 Apr 2002 09:26:49 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Forselles, Tom" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Forselles, Tom" <[log in to unmask]>
Subject: Insulation in the crimp contact area
MIME-Version: 1.0
Content-Type: text/plain; charset="ISO-8859-1"
I am trying to find an IPC reference standard for a situatuation I believe
is a problem. I have some 24AWG wires coming from a cooling fan assembly
where the wires are terminated with crimped male contacts that slip into a
plastic housing for a typical pin-and-socket arrangement. The outer part of
the crimp looks good where the wire is nicely crimped around the wire
insulation, but the inner part of the crimp appears marginal in that there
is consistently at least some insulation running into the contact area. The
result is a crimp that does not appear to be fully formed around the actual
conductor. Closest IPC reference I found was 610C, 4.2.3.2 for mechanical
assembly, hardware mounting, threaded fasteners - where there is to be "no
insulation in the contact area". Could anyone give me a more specific
standard reference or perhaps educate me if this is an actual problem?
Responses to the list or private e-mail is greatly appreciated. Thank you
in advance.
Tom Forselles
[log in to unmask]
Phone: 805.783.6048
FAX: 805-541-5088
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Date: Wed, 24 Apr 2002 12:38:29 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Torres, Roberto" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Torres, Roberto" <[log in to unmask]>
Subject: Re: Microscopes
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
All;
Thanks for the suggestions on Microscopes and Digital photographs.
The suggestion from Charles was of particular interest. Seems like
most use the method we use here now put the digital camera to the
lens of the microscope and snap away, it is just with this method
we tend to get a lot of telescope images, that is round and black
around the edges.
Again thanks for all the input.
Regards
Bob Torres
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Date: Wed, 24 Apr 2002 11:04:42 -0600
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
[log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Insulation in the crimp contact area
X-To: [log in to unmask]
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Tom,
Try IPC-620 Acceptability for Cables/Wire Harnesses.
Rick Howieson
Delta Group Electronics, Inc.
-----Original Message-----
From: Forselles, Tom [mailto:[log in to unmask]]
Sent: Wednesday, April 24, 2002 10:27 AM
To: [log in to unmask]
Subject: [TN] Insulation in the crimp contact area
I am trying to find an IPC reference standard for a situatuation I believe
is a problem. I have some 24AWG wires coming from a cooling fan assembly
where the wires are terminated with crimped male contacts that slip into a
plastic housing for a typical pin-and-socket arrangement. The outer part of
the crimp looks good where the wire is nicely crimped around the wire
insulation, but the inner part of the crimp appears marginal in that there
is consistently at least some insulation running into the contact area. The
result is a crimp that does not appear to be fully formed around the actual
conductor. Closest IPC reference I found was 610C, 4.2.3.2 for mechanical
assembly, hardware mounting, threaded fasteners - where there is to be "no
insulation in the contact area". Could anyone give me a more specific
standard reference or perhaps educate me if this is an actual problem?
Responses to the list or private e-mail is greatly appreciated. Thank you
in advance.
Tom Forselles
[log in to unmask]
Phone: 805.783.6048
FAX: 805-541-5088
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Date: Wed, 24 Apr 2002 10:15:52 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Dan R. Johnson" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Dan R. Johnson" <[log in to unmask]>
Subject: Re: Manual printing tables...
X-To: [log in to unmask]
MIME-version: 1.0
Content-type: multipart/alternative;
boundary="Boundary_(ID_8cSlTYVq61KLkyy00Wk8sw)"
This is a multi-part message in MIME format.
--Boundary_(ID_8cSlTYVq61KLkyy00Wk8sw)
Content-type: text/plain; charset=iso-8859-1
Content-transfer-encoding: 7BIT
Good Morning Steve,
Elite (714) 895-1911 has been around for years. The best bang for your buck in my opinion. With minimal tooling you can change over the unit in about 5 minutes. They even modified the platen for my print nest at no extra charge. The only thing I don't like is the squeegee that ships with the product, I went to Transition Automation (800) 648-3338 and got a steel squeegee.
If you want a semi auto unit (requires house air) look for a used De-Hart. There isn't much that can go wrong with these units so they are a pretty safe buy used.
Hope this helps,
Dan
--Boundary_(ID_8cSlTYVq61KLkyy00Wk8sw)
Content-type: text/html; charset=iso-8859-1
Content-transfer-encoding: 7BIT
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
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<BODY bgColor=#ffffff>
<DIV><FONT face=Arial size=2>Good Morning Steve,</FONT></DIV>
<DIV><FONT face=Arial size=2>Elite (714) 895-1911 has been around for years. The
best bang for your buck in my opinion. With minimal tooling you can change over
the unit in about 5 minutes. They even modified the platen for my print nest at
no extra charge. The only thing I don't like is the squeegee that ships with the
product, I went to Transition Automation (800) 648-3338 and got a steel
squeegee. </FONT></DIV>
<DIV><FONT face=Arial size=2>If you want a semi auto unit (requires house air)
look for a used De-Hart. There isn't much that can go wrong with these units so
they are a pretty safe buy used.</FONT></DIV>
<DIV><FONT face=Arial size=2>Hope this helps,</FONT></DIV>
<DIV><FONT face=Arial size=2>Dan</FONT></DIV></BODY></HTML>
--Boundary_(ID_8cSlTYVq61KLkyy00Wk8sw)--
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Date: Wed, 24 Apr 2002 13:31:20 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Sauer, Steven T." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Sauer, Steven T." <[log in to unmask]>
Subject: Re: Manual printing tables...
X-To: [log in to unmask]
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Hey Steve,
Check out this link: http://www.eliteprinters.com/
<http://www.eliteprinters.com/>
I have a model 4500 and does as good a job as one can expect for manual
printing. My only problem is getting the folks to apply 1lb of force for
each inch of squeegee length!! Good luck.
Steve Sauer
-----Original Message-----
From: [log in to unmask] [mailto:[log in to unmask]]
I'm looking for an inexpensive manual printing table to use for the
one'sies two'sies that we do here, and as a last ditch back-up when our DEK
goes down.
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Date: Wed, 24 Apr 2002 18:37:59 +0100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Graham Naisbitt <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Graham Naisbitt <[log in to unmask]>
Subject: Re: TEMP EXTREME
X-To: David Douthit <[log in to unmask]>
In-Reply-To: <[log in to unmask]>
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David
Contrary to your view, we have a water based acrylic coating that has
been tested successfully to 200 DegC - that's 392 Deg F.
As to the original question, Jim, I am not sure that the coating will
achieve what you might be looking for, because the coating is not a very
good thermal insulator. So your components will need to be able to work
at the elevated temp - and the coating, such as the one I mention, will
certainly help.
Regards Graham Naisbitt
[log in to unmask]
Concoat ANNOUNCE their acquisition of the former Multicore SPCID
business.
MUST II Solderability Testing Systems -
CM Cleanliness Testing Systems -
Auto-SIR Reliability Testing Systems -
SoldaPro & NEW SoldaPro Wizard Thermal Profilers
For more information please visit our new web site:
www.concoatsystems.com <http://www.concoatsystems.com/>
Concoat Limited
Alasan House, Albany Park
Camberley GU16 7PH - UK
www.concoat.co.uk <http://www.concoat.co.uk/>
Phone: +44 1276 691100
Fax: +44 1276 691227
Mobile: +44 79 6858 2121
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of David Douthit
Sent: Wednesday, April 24, 2002 17:34
To: [log in to unmask]
Subject: Re: [TN] TEMP EXTREME
James,
How about acrylic conformal coating?
You are so far above the Tg of acrylics that the coating can "flow",
melt, evaporate, or all the above!
(Not to mention letting contaminants reach the surface!)
David A. Douthit
Manager
LoCan LLC
"Marsico, James" wrote:
Hello Technet:
I think I may have asked this question a while ago (or something
similar)
but couldn't find anything in the archives. I have a surface mount
assembly
that gets installed into a top assembly housing, with covers. The test
guys
want to subject this assembly to 125 degrees C for 112 hours. Assuming
that
all of the components are rated for this temperature, is there anything
else
that says this isn't a good idea? I'm thinking about the solder joints,
maybe decreased reliability due to excessive grain growth? How about
acrylic conformal coating? The PWB is polyimide, so this shouldn't be
an
issue. Anything else?
Thanks again...
Jim Marsico
Senior Engineer
Production Engineering
EDO Electronics Systems Group
[log in to unmask] <mailto:[log in to unmask]>
631-595-5879
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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META HTTP-EQUIV=3D"Content-Type" CONTENT=3D"text/html; =
charset=3Dus-ascii">
<TITLE>Message</TITLE>
<META content=3D"MSHTML 6.00.2600.0" name=3DGENERATOR></HEAD>
<BODY>
<DIV><SPAN class=3D630153417-24042002><FONT face=3DArial color=3D#0000ff =
size=3D2><STRONG>David</STRONG></FONT></SPAN></DIV>
<DIV><SPAN class=3D630153417-24042002><STRONG><FONT face=3DArial =
color=3D#0000ff=20
size=3D2></FONT></STRONG></SPAN> </DIV>
<DIV><SPAN class=3D630153417-24042002><STRONG><FONT face=3DArial =
color=3D#0000ff=20
size=3D2>Contrary to your view, we have a water based acrylic coating =
that has=20
been tested successfully to 200 DegC - that's 392 Deg=20
F.</FONT></STRONG></SPAN></DIV>
<DIV><STRONG><FONT face=3DArial color=3D#0000ff =
size=3D2></FONT></STRONG> </DIV>
<DIV><STRONG><FONT face=3DArial color=3D#0000ff size=3D2><SPAN=20
class=3D630153417-24042002>As to the original question, Jim, I am not =
sure that=20
the coating will achieve what you might be looking for, because the =
coating is=20
not a very good thermal insulator. So your components will need to be =
able to=20
work at the elevated temp - and the coating, such as the one I mention, =
will=20
certainly help.</SPAN></FONT></STRONG></DIV>
<DIV><STRONG><FONT face=3DArial color=3D#0000ff size=3D2><SPAN=20
class=3D630153417-24042002></SPAN></FONT></STRONG> </DIV>
<DIV><FONT face=3DArial size=3D2><STRONG>Regards Graham=20
Naisbitt</STRONG></FONT></DIV>
<DIV><STRONG><FONT face=3DArial size=3D2></FONT></STRONG> </DIV>
<DIV><FONT face=3DArial size=3D2><STRONG><A=20
href=3D"mailto:[log in to unmask]">[log in to unmask]
uk</A></STRONG></FONT></DIV>
<DIV><STRONG><FONT face=3DArial size=3D2></FONT></STRONG> </DIV>
<DIV><STRONG><FONT face=3DArial size=3D2>Concoat ANNOUNCE their =
acquisition of the=20
former Multicore SPCID business.</FONT></STRONG></DIV>
<DIV><STRONG><FONT face=3DArial size=3D2></FONT></STRONG> </DIV>
<DIV><STRONG><FONT face=3DArial size=3D2>MUST II Solderability Testing =
Systems -=20
</FONT></STRONG></DIV>
<DIV><STRONG><FONT face=3DArial size=3D2>CM Cleanliness Testing Systems =
-=20
</FONT></STRONG></DIV>
<DIV><STRONG><FONT face=3DArial size=3D2>Auto-SIR Reliability Testing =
Systems -=20
</FONT></STRONG></DIV>
<DIV><STRONG><FONT face=3DArial size=3D2>SoldaPro & NEW SoldaPro =
Wizard Thermal=20
Profilers</FONT></STRONG></DIV>
<DIV><STRONG><FONT face=3DArial size=3D2></FONT></STRONG> </DIV>
<DIV><STRONG><FONT face=3DArial size=3D2>For more information please =
visit our new=20
web site: <A=20
href=3D"http://www.concoatsystems.com/">www.concoatsystems.com</A></FONT>=
</STRONG></DIV>
<DIV><STRONG><FONT face=3DArial size=3D2></FONT></STRONG> </DIV>
<DIV><FONT face=3DArial size=3D2><STRONG>Concoat =
Limited</STRONG></FONT></DIV>
<DIV><FONT face=3DArial size=3D2><STRONG>Alasan House, Albany=20
Park</STRONG></FONT></DIV>
<DIV><FONT face=3DArial size=3D2><STRONG>Camberley GU16 7PH -=20
UK</STRONG></FONT></DIV>
<DIV><STRONG><FONT face=3DArial size=3D2></FONT></STRONG> </DIV>
<DIV><FONT face=3DArial size=3D2><STRONG><A=20
href=3D"http://www.concoat.co.uk/">www.concoat.co.uk</A></STRONG></FONT><=
/DIV>
<DIV><STRONG><FONT face=3DArial size=3D2></FONT></STRONG> </DIV>
<DIV><FONT face=3DArial size=3D2><STRONG>Phone: +44 1276=20
691100</STRONG></FONT></DIV>
<DIV><FONT face=3DArial size=3D2><STRONG>Fax: +44 1276 =
691227</STRONG></FONT></DIV>
<DIV><FONT face=3DArial size=3D2><STRONG>Mobile: +44 79 6858=20
2121</STRONG></FONT></DIV>
<BLOCKQUOTE dir=3Dltr=20
style=3D"PADDING-LEFT: 5px; MARGIN-LEFT: 5px; BORDER-LEFT: #0000ff 2px =
solid; MARGIN-RIGHT: 0px">
<DIV></DIV>
<DIV class=3DOutlookMessageHeader lang=3Den-us dir=3Dltr =
align=3Dleft><FONT=20
face=3DTahoma size=3D2>-----Original Message-----<BR><B>From:</B> =
TechNet=20
[mailto:[log in to unmask]] <B>On Behalf Of </B>David =
Douthit<BR><B>Sent:</B>=20
Wednesday, April 24, 2002 17:34<BR><B>To:</B>=20
[log in to unmask]<BR><B>Subject:</B> Re: [TN] TEMP=20
EXTREME<BR><BR></FONT></DIV>James,=20
<P><I>How about acrylic conformal coating?</I> <BR>You are so far =
above the Tg=20
of acrylics that the coating can "flow", melt, evaporate, or all the =
above!=20
<BR>(Not to mention letting contaminants reach the surface!)=20
<P>David A. Douthit <BR>Manager <BR>LoCan LLC <BR> =20
<P>"Marsico, James" wrote:=20
<BLOCKQUOTE TYPE=3D"CITE">Hello Technet:=20
<P>I think I may have asked this question a while ago (or something =
similar)=20
<BR>but couldn't find anything in the archives. I have a =
surface mount=20
assembly <BR>that gets installed into a top assembly housing, with=20
covers. The test guys <BR>want to subject this assembly to 125 =
degrees=20
C for 112 hours. Assuming that <BR>all of the components are =
rated for=20
this temperature, is there anything else <BR>that says this isn't a =
good=20
idea? I'm thinking about the solder joints, <BR>maybe =
decreased=20
reliability due to excessive grain growth? How about =
<BR>acrylic=20
conformal coating? The PWB is polyimide, so this shouldn't be =
an=20
<BR>issue. Anything else?=20
<P>Thanks again...=20
<P>Jim Marsico <BR>Senior Engineer <BR>Production Engineering =
<BR>EDO=20
Electronics Systems Group <BR>[log in to unmask] <<A=20
=
href=3D"mailto:[log in to unmask]">mailto:[log in to unmask]</A>&=
gt;=20
<BR>631-595-5879=20
=
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<BR>Technet Mail List provided as a free service by IPC using =
LISTSERV 1.8d=20
<BR>To unsubscribe, send a message to [log in to unmask] with =
following text=20
in <BR>the BODY (NOT the subject field): SIGNOFF Technet <BR>To =
temporarily=20
halt delivery of Technet send e-mail to [log in to unmask]: SET =
Technet NOMAIL=20
<BR>To receive ONE mailing per day of all the posts: send e-mail to=20
[log in to unmask]: SET Technet Digest <BR>Search the archives of =
previous=20
posts at: <A=20
=
href=3D"http://listserv.ipc.org/archives">http://listserv.ipc.org/archive=
s</A>=20
<BR>Please visit IPC web site <A=20
=
href=3D"http://www.ipc.org/html/forum.htm">http://www.ipc.org/html/forum.=
htm</A>=20
for additional <BR>information, or contact Keach Sasamori at =
[log in to unmask]
or 847-509-9700 ext.5315=20
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Date: Wed, 24 Apr 2002 14:04:37 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Phil Nutting <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Phil Nutting <[log in to unmask]>
Subject: Re: Insulation in the crimp contact area
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
Tom,
This can be found in the new IPC standard IPC/WHMA-A-620, section 5.1.2.
Hope this helps.
Phil Nutting
-----Original Message-----
From: Forselles, Tom [mailto:[log in to unmask]]
Sent: Wednesday, April 24, 2002 12:27 PM
To: [log in to unmask]
Subject: [TN] Insulation in the crimp contact area
I am trying to find an IPC reference standard for a situatuation I =
believe
is a problem. I have some 24AWG wires coming from a cooling fan =
assembly
where the wires are terminated with crimped male contacts that slip into =
a
plastic housing for a typical pin-and-socket arrangement. The outer =
part of
the crimp looks good where the wire is nicely crimped around the wire
insulation, but the inner part of the crimp appears marginal in that =
there
is consistently at least some insulation running into the contact area. =
The
result is a crimp that does not appear to be fully formed around the =
actual
conductor. Closest IPC reference I found was 610C, 4.2.3.2 for =
mechanical
assembly, hardware mounting, threaded fasteners - where there is to be =
"no
insulation in the contact area". Could anyone give me a more specific
standard reference or perhaps educate me if this is an actual problem?
Responses to the list or private e-mail is greatly appreciated. Thank =
you
in advance.
Tom Forselles
[log in to unmask]
Phone: 805.783.6048
FAX: 805-541-5088
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Date: Wed, 24 Apr 2002 14:15:48 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Guy Ramsey <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Guy Ramsey <[log in to unmask]>
Subject: Re: Insulation in the crimp contact area
X-To: "Forselles, Tom" <[log in to unmask]>
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
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You have described a defect condition from IPC-A-620 the new wire and cable
harness acceptability standard.
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Forselles, Tom
> Sent: Wednesday, April 24, 2002 12:27 PM
> To: [log in to unmask]
> Subject: [TN] Insulation in the crimp contact area
>
>
> I am trying to find an IPC reference standard for a situatuation I believe
> is a problem. I have some 24AWG wires coming from a cooling fan assembly
> where the wires are terminated with crimped male contacts that slip into a
> plastic housing for a typical pin-and-socket arrangement. The
> outer part of
> the crimp looks good where the wire is nicely crimped around the wire
> insulation, but the inner part of the crimp appears marginal in that there
> is consistently at least some insulation running into the contact
> area. The
> result is a crimp that does not appear to be fully formed around
> the actual
> conductor. Closest IPC reference I found was 610C, 4.2.3.2 for mechanical
> assembly, hardware mounting, threaded fasteners - where there is to be "no
> insulation in the contact area". Could anyone give me a more specific
> standard reference or perhaps educate me if this is an actual problem?
> Responses to the list or private e-mail is greatly appreciated. Thank you
> in advance.
> Tom Forselles
> [log in to unmask]
> Phone: 805.783.6048
> FAX: 805-541-5088
>
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Date: Wed, 24 Apr 2002 11:29:19 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
John Foster <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: John Foster <[log in to unmask]>
Subject: Re: Via Plug
X-To: "Marsico, James" <[log in to unmask]>
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Thanks Jim
Did you do this extra plating selectively. Or did you just overplate the
whole PCB. Someone else mentioned the dupont product we are trying to
get our vendor to look at it.
Thanks
John Foster
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Marsico, James
Sent: Wednesday, April 24, 2002 4:10 AM
To: [log in to unmask]
Subject: Re: [TN] Via Plug
John, We've looked into the sand thing a while ago, and found that just by
increasing the copper plating in the hole to 2 mils will give you far better
thermal performance than any thermally conductive epoxy for hole fill.
Jim Marsico
Senior Engineer
Production Engineering
EDO Electronics Systems Group
[log in to unmask] <mailto:[log in to unmask]>
631-595-5879
-----Original Message-----
From: John Foster [SMTP:[log in to unmask]]
Sent: Tuesday, April 23, 2002 3:07 PM
To: [log in to unmask]
Subject: [TN] Via Plug
Hello, I am new to this listserver. I must say that it is very
informative. I wish I had known of it long ago.
I have a question about via plugging. Right now
our board vendor is doing our via plugs with
I guess with a standard epoxy. We are trying
to find a solution that would give us a much
better thermal performance.
We are looking at silver epoxy and this
material from Dupont. Does anyone know of
some material that would give us a really good
thermal performance. We are in a commercial
environment. So the material does not have to
meet industrial specs.
Any input on this matter would be greatly '
appreciated.
Thank You
John Foster
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Date: Wed, 24 Apr 2002 14:44:45 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Sauer, Steven T." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Sauer, Steven T." <[log in to unmask]>
Subject: Re: Insulation in the crimp contact area
X-To: "Forselles, Tom" <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Tom,
IPC/WHMA-A-620 Requirements & Acceptance for Cable & Wire Harness Assemblies
is what you're looking for. This document was just released in January
2002.
To answer your question, there should be no insulation in the
wire-to-terminal crimp. Potential causes are improper strip, insufficient
strip length, and misfed wire into terminal. One other suggestion would be
to measure the crimp height per the terminal manufacturer's specification.
Steve Sauer
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Date: Wed, 24 Apr 2002 15:03:50 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Marsico, James" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Marsico, James" <[log in to unmask]>
Subject: Re: Contract House Placement Costs
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Ed, You'll never get any of these CM guys to give you a direct answer
(chuckle). I suggest you go out to a few CMs for quotes and see how they
very. We've found, on occasion, the variation to be quite large.
Jim Marsico
Senior Engineer
Production Engineering
EDO Electronics Systems Group
[log in to unmask] <mailto:[log in to unmask]>
631-595-5879
-----Original Message-----
From: Edward S. Wheeler [SMTP:[log in to unmask]]
Sent: Wednesday, April 24, 2002 10:31 AM
To: [log in to unmask]
Subject: [TN] Contract House Placement Costs
Hello everybody. We were starting to look at sending out some
contract
work, and we were wondering if any of you guys using CMs had a
ballpark
figure on cost per placement and / or cost per joint on surface
mount
assemblies. I would just like to make sure that a place we are
looking at
is not particularly over the top.
Thanks.
Ed
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Date: Wed, 24 Apr 2002 15:15:28 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Guy Ramsey <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Guy Ramsey <[log in to unmask]>
Subject: Re: Manual printing tables...
X-To: [log in to unmask]
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="----=_NextPart_000_0001_01C1EBA2.DE29DF80"
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------=_NextPart_000_0001_01C1EBA2.DE29DF80
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Mancorp does a good job in that area. They have a nice little Swiss made
tool by Essemtec.
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of [log in to unmask]
Sent: Wednesday, April 24, 2002 11:26 AM
To: [log in to unmask]
Subject: [TN] Manual printing tables...
Hi All,
I'm looking for an inexpensive manual printing table to use for the
one'sies two'sies that we do here, and as a last ditch back-up when our DEK
goes down. I used one called a Palomar printing table when I was out in
California, and it did a really good job.
Could use any sized frame, nice precise hinge, had X/Y micrometers to fine
tune registration... could do 20-mil pitch all day long.
Are there any others out there?
-Steve Gregory-
------=_NextPart_000_0001_01C1EBA2.DE29DF80
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<BODY>
<DIV><FONT color=3D#0000ff face=3DArial size=3D2><SPAN=20
class=3D717001319-24042002>Mancorp does a good job in that area. They =
have a nice=20
little Swiss made tool by Essemtec. </SPAN></FONT></DIV>
<BLOCKQUOTE=20
style=3D"BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; PADDING-LEFT: =
5px">
<DIV class=3DOutlookMessageHeader><FONT face=3D"Times New Roman"=20
size=3D2>-----Original Message-----<BR><B>From:</B> TechNet=20
[mailto:[log in to unmask]]<B>On Behalf Of</B> =
[log in to unmask]<BR><B>Sent:</B>=20
Wednesday, April 24, 2002 11:26 AM<BR><B>To:</B>=20
[log in to unmask]<BR><B>Subject:</B> [TN] Manual printing=20
tables...<BR><BR></DIV></FONT><FONT face=3Darial,helvetica><FONT =
size=3D2>Hi All,=20
<BR><BR>I'm looking for an inexpensive manual printing table to use =
for the=20
one'sies two'sies that we do here, and as a last ditch back-up when =
our DEK=20
goes down. I used one called a Palomar printing table when I was out =
in=20
California, and it did a really good job. <BR><BR>Could use any sized =
frame,=20
nice precise hinge, had X/Y micrometers to fine tune registration... =
could do=20
20-mil pitch all day long. <BR><BR>Are there any others out there?=20
<BR><BR>-Steve Gregory-</FONT> </FONT></BLOCKQUOTE></BODY></HTML>
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Date: Wed, 24 Apr 2002 15:09:25 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Kathy Kuhlow <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Kathy Kuhlow <[log in to unmask]>
Subject: Re: Insulation in the crimp contact area
Mime-Version: 1.0
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If your like me and still waiting for a copy of the new standard you can =
try the molex website. I have used this information for years when I have =
done cable training. It is a really good resource for good crimps and how =
to recognize them. Go to this address and then go to that bottom of that =
page and you will see good crimps and how to recognize them. =20
http://www.molex.com/cgi-bin/bv/molex/home_init.jsp?x=3Dy&BV_SessionID=3D@@=
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Date: Wed, 24 Apr 2002 15:53:57 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Becerra Alejandro <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Becerra Alejandro <[log in to unmask]>
Subject: Repair of Circuit with Solder Paste below
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Hello to All,
We have a circuit that requires solder under it because in order to have a
good thermal dissipation.
The circuit is a QFP48. When assembled in the line, the stencil has
apertures in the body of the component in order to apply solder.
We have tried to manually apply the solder with an iron tip, but after
cross-sectioning the repair component we have found that
sometimes the solder is not in contact with the component.
What could be the appropriate procedure to repair this component?
Regards,
Alejandro Becerra
------_=_NextPart_001_01C1EBD2.272992A0
Content-Type: text/html;
charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
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<META HTTP-EQUIV=3D"Content-Type" CONTENT=3D"text/html; =
charset=3Diso-8859-1">
<META NAME=3D"Generator" CONTENT=3D"MS Exchange Server version =
5.5.2653.12">
<TITLE>Repair of Circuit with Solder Paste below</TITLE>
</HEAD>
<BODY>
<P><FONT SIZE=3D2 FACE=3D"Arial">Hello to All,</FONT>
</P>
<P><FONT SIZE=3D2 FACE=3D"Arial">We have a circuit that requires solder =
under it because in order to have a good thermal dissipation.</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">The circuit is a QFP48. When =
assembled in the line, the stencil has apertures in the body of the =
component in order to apply solder.</FONT></P>
<P><FONT SIZE=3D2 FACE=3D"Arial">We have tried to manually apply the =
solder with an iron tip, but after cross-sectioning the repair =
component we have found that </FONT></P>
<P><FONT SIZE=3D2 FACE=3D"Arial">sometimes the solder is not in contact =
with the component.</FONT>
<BR><FONT SIZE=3D2 FACE=3D"Arial">What could be the appropriate =
procedure to repair this component?</FONT>
</P>
<P><FONT SIZE=3D2 FACE=3D"Arial">Regards,</FONT>
</P>
<P><FONT SIZE=3D2 FACE=3D"Arial">Alejandro Becerra</FONT>
</P>
<BR>
</BODY>
</HTML>
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Date: Wed, 24 Apr 2002 16:05:35 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Kathy Kuhlow <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Kathy Kuhlow <[log in to unmask]>
Subject: Re: Contract House Placement Costs
Mime-Version: 1.0
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Steve was right the design and the complexity does play a large part of =
the picture but so does the CM's own capabilities, equipment used, etc. =
will make the variations between house to house enormous. Not to mention =
the management philosophy, labor rates per hour, material purchasing power =
etc. =20
For the CM's you are considering ask what equipment is used, look into the =
per hour placements and the general machine bells and whistles. If you go =
on a tour look at the amount of product in wip (the more there is the more =
overhead you will generally pay for), look for a CM that isn't afraid to =
let you look at the run time and data. If the CM you choose does a good =
DFM process you will know what the standard run time is and then also the =
added charges due to layout/design issues. Don't get in to any CM who =
won't be open about their process and run time with you. Another technique =
I used a lot when I was in the OEM business was to go to the CM on-site =
for a production approval lot. I watched each process, timed it, and also =
recorded all defects that were found. It can be a small lot but it does =
make a questionable CM very honest. =20
Kathy=20
--=_B4E94239.187914AA
Content-Type: text/plain
Content-Disposition: attachment; filename="TEXT.htm"
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META http-equiv=Content-Type content="text/html; charset=iso-8859-1">
<META content="MSHTML 6.00.2715.400" name=GENERATOR></HEAD>
<BODY style="MARGIN-TOP: 2px; FONT: 10pt MS Sans Serif; MARGIN-LEFT: 2px">
<DIV>Steve was right the design and the complexity does play a large part of the
picture but so does the CM's own capabilities, equipment used, etc. will
make the variations between house to house enormous. Not to
mention the management philosophy, labor rates per hour, material purchasing
power etc. </DIV>
<DIV> </DIV>
<DIV>For the CM's you are considering ask what equipment is used, look into the
per hour placements and the general machine bells and whistles. If you go
on a tour look at the amount of product in wip (the more there is the more
overhead you will generally pay for), look for a CM that isn't afraid to let you
look at the run time and data. If the CM you choose does a good DFM
process you will know what the standard run time is and then also the added
charges due to layout/design issues. Don't get in to any CM who won't be
open about their process and run time with you. Another technique I used a
lot when I was in the OEM business was to go to the CM on-site for a production
approval lot. I watched each process, timed it, and also recorded all
defects that were found. It can be a small lot but it does make a
questionable CM very honest. </DIV>
<DIV> </DIV>
<DIV>Kathy </DIV></BODY></HTML>
--=_B4E94239.187914AA--
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Date: Wed, 24 Apr 2002 17:30:34 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Bev Christian <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Bev Christian <[log in to unmask]>
Subject: Re: Freeze Spray Trouble Shooting
MIME-Version: 1.0
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And I would like to point out yet again that most of these materials are
fully fluorinated materials that have incredibly long atmospheric lives and
thus have terribly high global warming potentials. I would recommend using
food grade carbon dioxide instead. You can buy a "gun" to put on the
compressed gas tank to aim the liquid/gas at the component in question.
Sorry I can't remember the name of the company right now, but if you check
the archives under my name for the '96 to '98 time frame you might find it.
And others might chime in to augment my failing memory. ;(
regards,
Bev Christian
Research in Motion.
-----Original Message-----
From: Carl VanWormer [mailto:[log in to unmask]]
Sent: April 24, 2002 10:23 AM
To: [log in to unmask]
Subject: Re: [TN] Freeze Spray Trouble Shooting
As to the cause of your problems, I vote for timing problems, with a close
second guess at system noise caused by impedance mismatch on long control
signal lines.
I'm Carl and I'm a Freeze Spray user . . .
Now that I've got that off my chest, I'd like to say that I seldom wreck
stuff, and can usually find thermal mechanical intermittents and
(particularly) timing problems. Frozen parts seem to have faster transition
edges. A long time ago, I was able to make our 4 MHz Z-80 processor system
work at 7.8 MHz by freezing the processor, EPROM, and RAM chips (with a
variable oscillator for testing). Recently, I've found that I could fix (or
cause to fail) a new design by squirting the Altera (EPLD) or processor.
The culprit was "timing" and a poorly designed (overloaded) set of control
and bus lines. The difference in timing between the Altera latching in the
correct and incorrect data was seen to be about 1/2 nano-second. By
selective heating (and/or cooling) of the various chips, I could "adjust"
the timing to make the device work or fail. Of course, we had to fix the
timing problem, but my first line of discovery is (often) Freeze Spray.
When I've run out of the stuff, I grab the "Dust-Off" can and run it in
"inverted" mode to get the Freeze Spray effect.
p.s. After reading items in this forum about BGAs and circuit cooler, I've
vowed to never squirt the BGA packages. There is waaaaaaay too much chance
of wrecking something there, since there are no leads to absorb the flex
caused by differential thermal expansions.
Carl Van Wormer
Cipher Systems
1815 NW 169th Place, Suite 5010
Beaverton, OR 97006
Phone (503)-617-7447 Fax (503)-617-6550
-----Original Message-----
From: Ken Carlile [mailto:[log in to unmask]]
Sent: Tuesday, April 23, 2002 9:12 PM
To: [log in to unmask]
Subject: [TN] Freeze Spray Trouble Shooting
We recently received a prototype batch of 4 boards and experienced 4 for 4
failing test. Our techs sprayed down certain chips with Freeze Spray and
the board began working properly, at least for a short period of time. I
have checked prior tech net postings and have found fantastic responses as
to why Freeze Spray can damage a the IC or board, but can anyone explain why
they would begin functioning properly. Being a rookie component engineer I
can fully understand the issues related to freeze spray, but out techs and
design engineers are just going to point the finger since their units work
when sprayed. To further complicate the matter the chips that are being
sprayed are not all the same manufacturer and I can easily rule out a
component failure. Our senior engineer thinks that it may be timing related
since the main circuit being froze is the Altera PLD (20K400E) and related
circuitry.
Can anyone defend the use of Freeze Spray?
Can anyone present a logical failure mechanism?
/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\
The best Freeze Spray argument to date was Werner Engelmaier's:
http://jefry.ipc.org/scripts/wa.exe?A2=ind9907&L=TechNet&D=0&m=23823&P=55370
However this points to failure after spray not the opposite.
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Date: Wed, 24 Apr 2002 15:44:48 -0700
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Eddie Rocha <[log in to unmask]>
Subject: Re: Flip-flop panels
X-To: Jac Kroeker <[log in to unmask]>
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
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Flip flopping multilayer bds can get complicated and is not
recommended. It cannot be done if the layer stack-up is not
symmetrical.
thanks,
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Date: Wed, 24 Apr 2002 18:19:39 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
[log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Dave Hillman <[log in to unmask]>
Subject: Re: TEMP EXTREME
X-To: [log in to unmask]
MIME-Version: 1.0
Content-type: text/plain; charset="us-ascii"
Hi Jim! The solder joint microstructure is going to experience pretty
extensive recrystalization under the 112 hours at 125C soak. I haven't a
clue on what the overall impact will be on solder joint reliability but it
is certain you are losing some of the operation life of the assemblies.
Many Class 3 products withstand 2000 hours of thermal cycling from -55C to
+125C failure free. Those assemblies spend a total of 500 hours at the 125C
extreme (assuming 15 minute dwells). However, there is a difference between
thermal cycling and thermal soaking - is your use environment going to be
more thermal cycle or thermal soak?
Dave Hillman
Rockwell Collins
[log in to unmask]
"Marsico, James" <[log in to unmask]>@ipc.org> on 04/24/2002 09:33:21
AM
Please respond to "TechNet E-Mail Forum." <[log in to unmask]>; Please respond
to "Marsico, James" <[log in to unmask]>
Sent by: TechNet <[log in to unmask]>
To: [log in to unmask]
cc:
Subject: [TN] TEMP EXTREME
Hello Technet:
I think I may have asked this question a while ago (or something similar)
but couldn't find anything in the archives. I have a surface mount
assembly
that gets installed into a top assembly housing, with covers. The test
guys
want to subject this assembly to 125 degrees C for 112 hours. Assuming
that
all of the components are rated for this temperature, is there anything
else
that says this isn't a good idea? I'm thinking about the solder joints,
maybe decreased reliability due to excessive grain growth? How about
acrylic conformal coating? The PWB is polyimide, so this shouldn't be an
issue. Anything else?
Thanks again...
Jim Marsico
Senior Engineer
Production Engineering
EDO Electronics Systems Group
[log in to unmask] <mailto:[log in to unmask]>
631-595-5879
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Date: Wed, 24 Apr 2002 17:02:59 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
David Douthit <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: David Douthit <[log in to unmask]>
Subject: Re: Freeze Spray Trouble Shooting
X-To: Bev Christian <[log in to unmask]>
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--------------36EBA99788F6695C947FF15F
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Bev,
Years ago (about 7) there was a company selling hand held Vortex generators that plugged into 100 psi
shop air.
These little jewels put out -40 degree C air as long as there was 100 psi available. It also had to be
dry nonlubed air.
The company was called EXAir. I don't know if they are still around.
David A. Douthit
Manager
LoCan LLC
Bev Christian wrote:
> And I would like to point out yet again that most of these materials are
> fully fluorinated materials that have incredibly long atmospheric lives and
> thus have terribly high global warming potentials. I would recommend using
> food grade carbon dioxide instead. You can buy a "gun" to put on the
> compressed gas tank to aim the liquid/gas at the component in question.
> Sorry I can't remember the name of the company right now, but if you check
> the archives under my name for the '96 to '98 time frame you might find it.
> And others might chime in to augment my failing memory. ;(
>
> regards,
> Bev Christian
> Research in Motion.
>
> -----Original Message-----
> From: Carl VanWormer [mailto:[log in to unmask]]
> Sent: April 24, 2002 10:23 AM
> To: [log in to unmask]
> Subject: Re: [TN] Freeze Spray Trouble Shooting
>
> As to the cause of your problems, I vote for timing problems, with a close
> second guess at system noise caused by impedance mismatch on long control
> signal lines.
>
> I'm Carl and I'm a Freeze Spray user . . .
>
> Now that I've got that off my chest, I'd like to say that I seldom wreck
> stuff, and can usually find thermal mechanical intermittents and
> (particularly) timing problems. Frozen parts seem to have faster transition
> edges. A long time ago, I was able to make our 4 MHz Z-80 processor system
> work at 7.8 MHz by freezing the processor, EPROM, and RAM chips (with a
> variable oscillator for testing). Recently, I've found that I could fix (or
> cause to fail) a new design by squirting the Altera (EPLD) or processor.
> The culprit was "timing" and a poorly designed (overloaded) set of control
> and bus lines. The difference in timing between the Altera latching in the
> correct and incorrect data was seen to be about 1/2 nano-second. By
> selective heating (and/or cooling) of the various chips, I could "adjust"
> the timing to make the device work or fail. Of course, we had to fix the
> timing problem, but my first line of discovery is (often) Freeze Spray.
> When I've run out of the stuff, I grab the "Dust-Off" can and run it in
> "inverted" mode to get the Freeze Spray effect.
>
> p.s. After reading items in this forum about BGAs and circuit cooler, I've
> vowed to never squirt the BGA packages. There is waaaaaaay too much chance
> of wrecking something there, since there are no leads to absorb the flex
> caused by differential thermal expansions.
>
> Carl Van Wormer
> Cipher Systems
> 1815 NW 169th Place, Suite 5010
> Beaverton, OR 97006
> Phone (503)-617-7447 Fax (503)-617-6550
>
> -----Original Message-----
> From: Ken Carlile [mailto:[log in to unmask]]
> Sent: Tuesday, April 23, 2002 9:12 PM
> To: [log in to unmask]
> Subject: [TN] Freeze Spray Trouble Shooting
>
> We recently received a prototype batch of 4 boards and experienced 4 for 4
> failing test. Our techs sprayed down certain chips with Freeze Spray and
> the board began working properly, at least for a short period of time. I
> have checked prior tech net postings and have found fantastic responses as
> to why Freeze Spray can damage a the IC or board, but can anyone explain why
> they would begin functioning properly. Being a rookie component engineer I
> can fully understand the issues related to freeze spray, but out techs and
> design engineers are just going to point the finger since their units work
> when sprayed. To further complicate the matter the chips that are being
> sprayed are not all the same manufacturer and I can easily rule out a
> component failure. Our senior engineer thinks that it may be timing related
> since the main circuit being froze is the Altera PLD (20K400E) and related
> circuitry.
>
> Can anyone defend the use of Freeze Spray?
>
> Can anyone present a logical failure mechanism?
>
> /\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\
>
> The best Freeze Spray argument to date was Werner Engelmaier's:
> http://jefry.ipc.org/scripts/wa.exe?A2=ind9907&L=TechNet&D=0&m=23823&P=55370
>
> However this points to failure after spray not the opposite.
>
> ----------------------------------------------------------------------------
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> [log in to unmask]: SET Technet Digest
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> Please visit IPC web site http://www.ipc.org/html/forum.htm for additional
> information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700
> ext.5315
> ----------------------------------------------------------------------------
> -----
>
> ----------------------------------------------------------------------------
> -----
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>
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Bev,
<p>Years ago (about 7) there was a company selling hand held Vortex generators
that plugged into 100 psi shop air.
<br>These little jewels put out -40 degree C air as long as there was 100
psi available. It also had to be dry nonlubed air.
<p>The company was called EXAir. I don't know if they are still around.
<p>David A. Douthit
<br>Manager
<br>LoCan LLC
<p>Bev Christian wrote:
<blockquote TYPE=CITE>And I would like to point out yet again that most
of these materials are
<br>fully fluorinated materials that have incredibly long atmospheric lives
and
<br>thus have terribly high global warming potentials. I would recommend
using
<br>food grade carbon dioxide instead. You can buy a "gun" to put
on the
<br>compressed gas tank to aim the liquid/gas at the component in question.
<br>Sorry I can't remember the name of the company right now, but if you
check
<br>the archives under my name for the '96 to '98 time frame you might
find it.
<br>And others might chime in to augment my failing memory. ;(
<p>regards,
<br>Bev Christian
<br>Research in Motion.
<p>-----Original Message-----
<br>From: Carl VanWormer [<a href="mailto:[log in to unmask]">mailto:[log in to unmask]</a>]
<br>Sent: April 24, 2002 10:23 AM
<br>To: [log in to unmask]
<br>Subject: Re: [TN] Freeze Spray Trouble Shooting
<p>As to the cause of your problems, I vote for timing problems, with a
close
<br>second guess at system noise caused by impedance mismatch on long control
<br>signal lines.
<p>I'm Carl and I'm a Freeze Spray user . . .
<p>Now that I've got that off my chest, I'd like to say that I seldom wreck
<br>stuff, and can usually find thermal mechanical intermittents and
<br>(particularly) timing problems. Frozen parts seem to have faster transition
<br>edges. A long time ago, I was able to make our 4 MHz Z-80 processor
system
<br>work at 7.8 MHz by freezing the processor, EPROM, and RAM chips (with
a
<br>variable oscillator for testing). Recently, I've found that I
could fix (or
<br>cause to fail) a new design by squirting the Altera (EPLD) or processor.
<br>The culprit was "timing" and a poorly designed (overloaded) set of
control
<br>and bus lines. The difference in timing between the Altera latching
in the
<br>correct and incorrect data was seen to be about 1/2 nano-second.
By
<br>selective heating (and/or cooling) of the various chips, I could "adjust"
<br>the timing to make the device work or fail. Of course, we had
to fix the
<br>timing problem, but my first line of discovery is (often) Freeze Spray.
<br>When I've run out of the stuff, I grab the "Dust-Off" can and run it
in
<br>"inverted" mode to get the Freeze Spray effect.
<p>p.s. After reading items in this forum about BGAs and circuit
cooler, I've
<br>vowed to never squirt the BGA packages. There is waaaaaaay too
much chance
<br>of wrecking something there, since there are no leads to absorb the
flex
<br>caused by differential thermal expansions.
<p>Carl Van Wormer
<br>Cipher Systems
<br>1815 NW 169th Place, Suite 5010
<br>Beaverton, OR 97006
<br>Phone (503)-617-7447 Fax (503)-617-6550
<p>-----Original Message-----
<br>From: Ken Carlile [<a href="mailto:[log in to unmask]">mailto:[log in to unmask]</a>]
<br>Sent: Tuesday, April 23, 2002 9:12 PM
<br>To: [log in to unmask]
<br>Subject: [TN] Freeze Spray Trouble Shooting
<p>We recently received a prototype batch of 4 boards and experienced 4
for 4
<br>failing test. Our techs sprayed down certain chips with Freeze
Spray and
<br>the board began working properly, at least for a short period of time.
I
<br>have checked prior tech net postings and have found fantastic responses
as
<br>to why Freeze Spray can damage a the IC or board, but can anyone explain
why
<br>they would begin functioning properly. Being a rookie component
engineer I
<br>can fully understand the issues related to freeze spray, but out techs
and
<br>design engineers are just going to point the finger since their units
work
<br>when sprayed. To further complicate the matter the chips that
are being
<br>sprayed are not all the same manufacturer and I can easily rule out
a
<br>component failure. Our senior engineer thinks that it may be
timing related
<br>since the main circuit being froze is the Altera PLD (20K400E) and
related
<br>circuitry.
<p>Can anyone defend the use of Freeze Spray?
<p>Can anyone present a logical failure mechanism?
<p>/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\
<p>The best Freeze Spray argument to date was Werner Engelmaier's:
<br><a href="http://jefry.ipc.org/scripts/wa.exe?A2=ind9907&L=TechNet&D=0&m=23823&P=55370">http://jefry.ipc.org/scripts/wa.exe?A2=ind9907&L=TechNet&D=0&m=23823&P=55370</a>
<p>However this points to failure after spray not the opposite.
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Date: Thu, 25 Apr 2002 08:43:21 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: AM79C970AVIW (or not)
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
My thanks to all those who tried to help me find some of AMD's Industial
grade Ethernet Controller AM79C970AVIW. Sadly these animals are apparently
extict, so my next question to you all is, "Does anyone know of a good
up-screening house that would screen commercial parts for acceptability as
Industrial grade?"
All help very greatly appreciated as ever.
Peter
[This e-mail is confidential and may also be privileged. If you are not the
intended recipient, please delete it and notify us immediately; you should
not copy or use it for any purpose, nor disclose its contents to any other
person. Thank you.]
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Date: Wed, 24 Apr 2002 20:44:40 EDT
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Freeze Spray Trouble Shooting
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="part1_97.26a774dc.29f8ab78_boundary"
--part1_97.26a774dc.29f8ab78_boundary
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Hi David!
That's why this list is so valuable! They are still around!
Http://www.exair.com
Thanks!
-Steve Gregory-
> Bev, Years ago (about 7) there was a company selling hand held Vortex
> generators that plugged into 100 psi shop air.
> These little jewels put out -40 degree C air as long as there was 100 psi
> available. It also had to be dry nonlubed air. The company was called
> EXAir. I don't know if they are still around. David A. Douthit
> Manager
> LoCan LLC
>
>
--part1_97.26a774dc.29f8ab78_boundary
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<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>Hi David!<BR>
<BR>
That's why this list is so valuable! They are still around! Http://www.exair.com<BR>
<BR>
Thanks!<BR>
<BR>
-Steve Gregory-<BR>
<BR>
<BR>
<BLOCKQUOTE TYPE=CITE style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">Bev, Years ago (about 7) there was a company selling hand held Vortex generators that plugged into 100 psi shop air. <BR>
These little jewels put out -40 degree C air as long as there was 100 psi available. It also had to be dry nonlubed air. The company was called EXAir. I don't know if they are still around. David A. Douthit <BR>
Manager <BR>
LoCan LLC <BR>
<BR>
</BLOCKQUOTE><BR>
<BR>
</FONT></HTML>
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Date: Wed, 24 Apr 2002 21:02:59 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
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From: Werner Engelmaier <[log in to unmask]>
Subject: Re: TEMP EXTREME
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Hi Jim,
This response comes to you from China.
Why do your "test guys want to subject this assembly to 125Cfor 112 hours?" Is this a test board? If it is, this artificial aging prior to T-cycling is very appropriate and recommended in both IPC-SM-785 and IPC-9701 to prevent artificially optimistic solder joint fatigue results.
Werner Engelmaier
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Date: Wed, 24 Apr 2002 21:44:39 EDT
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Date: Thu, 25 Apr 2002 09:11:40 +0300
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Brian Ellis <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Brian Ellis <[log in to unmask]>
Subject: Re: Microscopes
X-To: "Torres, Roberto" <[log in to unmask]>
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Roberto
Does this matter? If you use a 4.3 or higher Mpixel camera, there are
sufficient pixels left in the centre zone to record what you need to
see, nicht war?
Brian
"Torres, Roberto" wrote:
>
> All;
>
> Thanks for the suggestions on Microscopes and Digital photographs.
> The suggestion from Charles was of particular interest. Seems like
> most use the method we use here now put the digital camera to the
> lens of the microscope and snap away, it is just with this method
> we tend to get a lot of telescope images, that is round and black
> around the edges.
>
> Again thanks for all the input.
>
> Regards
> Bob Torres
>
> ---------------------------------------------------------------------------------
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Date: Thu, 25 Apr 2002 09:29:50 +0200
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Peter Hefti <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Peter Hefti <[log in to unmask]>
Subject: Accelerated test for simulation of storage of PCBs with surface
finish white tin
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Hello TechNet:
We are searching for a method of accelerated aging of PCBs with surface
finish in white tin (chemical tin).
This method should be recognized , in order to simulate the storage of 6
or 12 month under normal conditions.
(85/85/1d or 2d test ??)
After such an accelerated test, the solderability will be tested by the
wetting balance method.
Thank you for your answer
With best regards
Peter Hefti
--=_alternative 00292EB9C1256BA6_=
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<br><font size=2 face="sans-serif">Hello TechNet:</font>
<br>
<br><font size=2 face="sans-serif">We are searching for a method of accelerated aging of PCBs with surface finish in white tin (chemical tin).</font>
<br><font size=2 face="sans-serif">This method should be recognized , in order to simulate the storage of 6 or 12 month under normal conditions.</font>
<br><font size=2 face="sans-serif">(85/85/1d or 2d test ??)</font>
<br><font size=2 face="sans-serif">After such an accelerated test, the solderability will be tested by the wetting balance method.</font>
<br>
<br><font size=2 face="sans-serif">Thank you for your answer</font>
<br>
<br><font size=2 face="sans-serif">With best regards</font>
<br>
<br><font size=2 face="sans-serif">Peter Hefti </font>
--=_alternative 00292EB9C1256BA6_=--
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Date: Thu, 25 Apr 2002 06:31:29 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: ESSENTIAL MLB STUFF
Per off line requests, I've sent nearly 20 essential, to me, MLB
requirements. The package size is about 500k and again is getting a bit
cumbersome to email by myself.
Daan, are you there. If you would be so kind, I'll send you the package and
you can post it on your great site.
MoonMan
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Date: Thu, 25 Apr 2002 08:09:33 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Marsico, James" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Marsico, James" <[log in to unmask]>
Subject: Re: Repair of Circuit with Solder Paste below
MIME-Version: 1.0
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If I understand correctly, you deposit solder paste under the component
during the initial build. After reflow, the paste solidifies and makes
contact with the bottom of the component for heat transfer. Your question
is what to do when replacing the component. How do you replace the solder
bumps under the device.
Is the body of the component ceramic or metal? If ceramic, when you remove
the devise the solder bumps should remain intact, nice and flat. Why not
leave these bumps as is and place the component, contacting the existing
bumps while soldering? If the case is metal, and you disturb the bumps
during removal, how about reapplying solder paste, placing the component and
reflowing it with a hot air terminal? Another option is to change the
drawing to allow the use of a thermal adhesive for rework.
Jim Marsico
Senior Engineer
Production Engineering
EDO Electronics Systems Group
[log in to unmask] <mailto:[log in to unmask]>
631-595-5879
-----Original Message-----
From: Becerra Alejandro [SMTP:[log in to unmask]]
Sent: Wednesday, April 24, 2002 4:54 PM
To: [log in to unmask]
Subject: [TN] Repair of Circuit with Solder Paste below
Hello to All,
We have a circuit that requires solder under it because in order to
have a good thermal dissipation.
The circuit is a QFP48. When assembled in the line, the stencil has
apertures in the body of the component in order to apply solder.
We have tried to manually apply the solder with an iron tip, but
after cross-sectioning the repair component we have found that
sometimes the solder is not in contact with the component.
What could be the appropriate procedure to repair this component?
Regards,
Alejandro Becerra
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Date: Thu, 25 Apr 2002 08:22:00 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Marsico, James" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Marsico, James" <[log in to unmask]>
Subject: Re: TEMP EXTREME
X-To: "[log in to unmask]" <[log in to unmask]>,
"[log in to unmask]" <[log in to unmask]>
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Just to clarify things, the housing that this assembly is installed in is a
two part housing. One side houses the SMT assembly and the other side is a
microelectronic hybrid, which eventually gets hermetically sealed. The
extended burn-in (air) at 125 C is for the hybrid requirements of MIL 883
and 38534. We're actually doing 48 hours pre-seal and 112 hours post seal.
The electrical engineers want to keep the SMT assembly in the housing during
the hybrid burn-in because the whole thing was tested and tuned this way. I
guess their afraid that removing the assembly prior to burn-in then
replacing it might screw up their performance. I just had a gut feeling
that subjecting this board to 125C for a total of 160 hours isn't a good
thing.
Jim Marsico
Senior Engineer
Production Engineering
EDO Electronics Systems Group
[log in to unmask] <mailto:[log in to unmask]>
631-595-5879
-----Original Message-----
From: [log in to unmask]
[SMTP:[log in to unmask]]
Sent: Wednesday, April 24, 2002 7:20 PM
To: [log in to unmask]; [log in to unmask]
Subject: Re: [TN] TEMP EXTREME
Hi Jim! The solder joint microstructure is going to experience
pretty
extensive recrystalization under the 112 hours at 125C soak. I
haven't a
clue on what the overall impact will be on solder joint reliability
but it
is certain you are losing some of the operation life of the
assemblies.
Many Class 3 products withstand 2000 hours of thermal cycling from
-55C to
+125C failure free. Those assemblies spend a total of 500 hours at
the 125C
extreme (assuming 15 minute dwells). However, there is a difference
between
thermal cycling and thermal soaking - is your use environment going
to be
more thermal cycle or thermal soak?
Dave Hillman
Rockwell Collins
[log in to unmask]
"Marsico, James" <[log in to unmask]>@ipc.org> on 04/24/2002
09:33:21
AM
Please respond to "TechNet E-Mail Forum." <[log in to unmask]>; Please
respond
to "Marsico, James" <[log in to unmask]>
Sent by: TechNet <[log in to unmask]>
To: [log in to unmask]
cc:
Subject: [TN] TEMP EXTREME
Hello Technet:
I think I may have asked this question a while ago (or something
similar)
but couldn't find anything in the archives. I have a surface mount
assembly
that gets installed into a top assembly housing, with covers. The
test
guys
want to subject this assembly to 125 degrees C for 112 hours.
Assuming
that
all of the components are rated for this temperature, is there
anything
else
that says this isn't a good idea? I'm thinking about the solder
joints,
maybe decreased reliability due to excessive grain growth? How
about
acrylic conformal coating? The PWB is polyimide, so this shouldn't
be an
issue. Anything else?
Thanks again...
Jim Marsico
Senior Engineer
Production Engineering
EDO Electronics Systems Group
[log in to unmask] <mailto:[log in to unmask]>
631-595-5879
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Date: Thu, 25 Apr 2002 08:11:13 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Becerra Alejandro <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Becerra Alejandro <[log in to unmask]>
Subject: Re: Repair of Circuit with Solder Paste below
X-To: "Marsico, James" <[log in to unmask]>
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We deposit solder paste under the component in order to help for heat
transfer.
The bottom side of the component is made of metal, then when I remove the
component we also remove the solder.
Applying solder paste again in the rework operation is a good idea.
Do you know how can we apply solder paste during rework?
Is it possible to use a mini-stencil? Where can I find a vendor for the
mini-stencil?
Thanks for your help.
Alejandro
-----Original Message-----
From: Marsico, James [mailto:[log in to unmask]]
Sent: Thursday, April 25, 2002 6:10 AM
To: [log in to unmask]
Subject: Re: [TN] Repair of Circuit with Solder Paste below
If I understand correctly, you deposit solder paste under the component
during the initial build. After reflow, the paste solidifies and makes
contact with the bottom of the component for heat transfer. Your question
is what to do when replacing the component. How do you replace the solder
bumps under the device.
Is the body of the component ceramic or metal? If ceramic, when you remove
the devise the solder bumps should remain intact, nice and flat. Why not
leave these bumps as is and place the component, contacting the existing
bumps while soldering? If the case is metal, and you disturb the bumps
during removal, how about reapplying solder paste, placing the component and
reflowing it with a hot air terminal? Another option is to change the
drawing to allow the use of a thermal adhesive for rework.
Jim Marsico
Senior Engineer
Production Engineering
EDO Electronics Systems Group
[log in to unmask] <mailto:[log in to unmask]>
631-595-5879
-----Original Message-----
From: Becerra Alejandro [SMTP:[log in to unmask]]
Sent: Wednesday, April 24, 2002 4:54 PM
To: [log in to unmask]
Subject: [TN] Repair of Circuit with Solder Paste below
Hello to All,
We have a circuit that requires solder under it because in order to
have a good thermal dissipation.
The circuit is a QFP48. When assembled in the line, the stencil has
apertures in the body of the component in order to apply solder.
We have tried to manually apply the solder with an iron tip, but
after cross-sectioning the repair component we have found that
sometimes the solder is not in contact with the component.
What could be the appropriate procedure to repair this component?
Regards,
Alejandro Becerra
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<META HTTP-EQUIV=3D"Content-Type" CONTENT=3D"text/html; =
charset=3Diso-8859-1">
<META NAME=3D"Generator" CONTENT=3D"MS Exchange Server version =
5.5.2653.12">
<TITLE>RE: [TN] Repair of Circuit with Solder Paste below</TITLE>
</HEAD>
<BODY>
<P><FONT SIZE=3D2>We deposit solder paste under the component in order =
to help for heat transfer.</FONT>
<BR><FONT SIZE=3D2>The bottom side of the component is made of metal, =
then when I remove the component we also remove the solder.</FONT>
<BR><FONT SIZE=3D2>Applying solder paste again in the rework operation =
is a good idea.</FONT>
<BR><FONT SIZE=3D2>Do you know how can we apply solder paste during =
rework?</FONT>
<BR><FONT SIZE=3D2>Is it possible to use a mini-stencil? Where can I =
find a vendor for the mini-stencil?</FONT>
</P>
<P><FONT SIZE=3D2>Thanks for your help.</FONT>
</P>
<P><FONT SIZE=3D2>Alejandro</FONT>
</P>
<P><FONT SIZE=3D2>-----Original Message-----</FONT>
<BR><FONT SIZE=3D2>From: Marsico, James [<A =
HREF=3D"mailto:[log in to unmask]">mailto:[log in to unmask]
</A>]</FONT>
<BR><FONT SIZE=3D2>Sent: Thursday, April 25, 2002 6:10 AM</FONT>
<BR><FONT SIZE=3D2>To: [log in to unmask]</FONT>
<BR><FONT SIZE=3D2>Subject: Re: [TN] Repair of Circuit with Solder =
Paste below</FONT>
</P>
<BR>
<P><FONT SIZE=3D2>If I understand correctly, you deposit solder paste =
under the component</FONT>
<BR><FONT SIZE=3D2>during the initial build. After reflow, the =
paste solidifies and makes</FONT>
<BR><FONT SIZE=3D2>contact with the bottom of the component for heat =
transfer. Your question</FONT>
<BR><FONT SIZE=3D2>is what to do when replacing the component. =
How do you replace the solder</FONT>
<BR><FONT SIZE=3D2>bumps under the device.</FONT>
</P>
<P><FONT SIZE=3D2>Is the body of the component ceramic or metal? =
If ceramic, when you remove</FONT>
<BR><FONT SIZE=3D2>the devise the solder bumps should remain intact, =
nice and flat. Why not</FONT>
<BR><FONT SIZE=3D2>leave these bumps as is and place the component, =
contacting the existing</FONT>
<BR><FONT SIZE=3D2>bumps while soldering? If the case is metal, =
and you disturb the bumps</FONT>
<BR><FONT SIZE=3D2>during removal, how about reapplying solder paste, =
placing the component and</FONT>
<BR><FONT SIZE=3D2>reflowing it with a hot air terminal? Another =
option is to change the</FONT>
<BR><FONT SIZE=3D2>drawing to allow the use of a thermal adhesive for =
rework.</FONT>
</P>
<P><FONT SIZE=3D2>Jim Marsico</FONT>
<BR><FONT SIZE=3D2>Senior Engineer</FONT>
<BR><FONT SIZE=3D2>Production Engineering</FONT>
<BR><FONT SIZE=3D2>EDO Electronics Systems Group</FONT>
<BR><FONT SIZE=3D2>[log in to unmask] <<A =
HREF=3D"mailto:[log in to unmask]">mailto:[log in to unmask]</A>=
></FONT>
<BR><FONT SIZE=3D2>631-595-5879</FONT>
</P>
<BR>
<P><FONT SIZE=3D2> =
-----Original Message-----</FONT>
<BR><FONT SIZE=3D2> =
From: Becerra Alejandro [SMTP:[log in to unmask]]</FONT>
<BR><FONT SIZE=3D2> =
Sent: Wednesday, April 24, 2002 4:54 PM</FONT>
<BR><FONT SIZE=3D2> =
To: [log in to unmask]</FONT>
<BR><FONT SIZE=3D2> =
Subject: [TN] Repair of =
Circuit with Solder Paste below</FONT>
</P>
<P><FONT SIZE=3D2> Hello to =
All,</FONT>
</P>
<P><FONT SIZE=3D2> We have a =
circuit that requires solder under it because in order to</FONT>
<BR><FONT SIZE=3D2>have a good thermal dissipation.</FONT>
<BR><FONT SIZE=3D2> The =
circuit is a QFP48. When assembled in the line, the stencil has</FONT>
<BR><FONT SIZE=3D2>apertures in the body of the component in order to =
apply solder.</FONT>
</P>
<P><FONT SIZE=3D2> We have =
tried to manually apply the solder with an iron tip, but</FONT>
<BR><FONT SIZE=3D2>after cross-sectioning the repair component we have =
found that</FONT>
</P>
<P><FONT SIZE=3D2> sometimes =
the solder is not in contact with the component.</FONT>
<BR><FONT SIZE=3D2> What =
could be the appropriate procedure to repair this component?</FONT>
</P>
<P><FONT SIZE=3D2> =
Regards,</FONT>
</P>
<P><FONT SIZE=3D2> Alejandro =
Becerra</FONT>
</P>
<BR>
<BR>
<P><FONT =
SIZE=3D2>---------------------------------------------------------------=
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Date: Thu, 25 Apr 2002 06:32:03 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
peter blokhuis <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: peter blokhuis <[log in to unmask]>
Subject: Looking for laser drill service company.
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Can anyone share the name of a good laser drilling
service company?
Peter Blokhuis
585-254-2988 x243
__________________________________________________
Do You Yahoo!?
Yahoo! Games - play chess, backgammon, pool and more
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Date: Thu, 25 Apr 2002 15:39:49 +0200
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"d. terstegge" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "d. terstegge" <[log in to unmask]>
Subject: Re: ESSENTIAL MLB STUFF
X-To: [log in to unmask]
MIME-Version: 1.0 (Generated by NET-TEL Mailguard SMTP version 4.0.0.22)
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Hi Earl,
I'll be glad to help you. Could you send it to [log in to unmask] ? I'll =
make a link on my website and post a message when the document is online.
Daan Terstegge
SMT Centre
Thales Communications
Unclassified mail
Personal Website: http://www.smtinfo.net
>>> Earl Moon <[log in to unmask]> 04/25 1:31 pm >>>
Per off line requests, I've sent nearly 20 essential, to me, MLB
requirements. The package size is about 500k and again is getting a bit
cumbersome to email by myself.
Daan, are you there. If you would be so kind, I'll send you the package =
and
you can post it on your great site.
MoonMan
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Date: Thu, 25 Apr 2002 09:44:50 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Edward S. Wheeler" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Edward S. Wheeler" <[log in to unmask]>
Subject: Re: Repair of Circuit with Solder Paste below
X-To: Becerra Alejandro <[log in to unmask]>
In-Reply-To: <[log in to unmask]
tce.com>
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<html>
<a href="http://www.minimicrostencil.com/" eudora="autourl">www.minimicrostencil.com</a>.
They can make custom stencils from your gerber files. We use them for all
of our BGA rework and have found them to be a great resource.<br><br>
Ed<br><br>
<br>
At 08:11 AM 4/25/2002 -0500, you wrote:<br><br>
<blockquote type=cite class=cite cite><font size=2>We deposit solder
paste under the component in order to help for heat transfer.</font>
<br>
<font size=2>The bottom side of the component is made of metal, then when
I remove the component we also remove the solder.</font> <br>
<font size=2>Applying solder paste again in the rework operation is a
good idea.</font> <br>
<font size=2>Do you know how can we apply solder paste during
rework?</font> <br>
<font size=2>Is it possible to use a mini-stencil? Where can I find a
vendor for the mini-stencil?</font> <br><br>
<font size=2>Thanks for your help.</font> <br><br>
<font size=2>Alejandro</font> <br><br>
<font size=2>-----Original Message-----</font> <br>
<font size=2>From: Marsico, James
[<a href="mailto:[log in to unmask]">mailto:[log in to unmask]</a>]</font>
<br>
<font size=2>Sent: Thursday, April 25, 2002 6:10 AM</font> <br>
<font size=2>To: [log in to unmask]</font> <br>
<font size=2>Subject: Re: [TN] Repair of Circuit with Solder Paste
below</font> <br><br>
<font size=2>If I understand correctly, you deposit solder paste under
the component</font> <br>
<font size=2>during the initial build. After reflow, the paste
solidifies and makes</font> <br>
<font size=2>contact with the bottom of the component for heat
transfer. Your question</font> <br>
<font size=2>is what to do when replacing the component. How do you
replace the solder</font> <br>
<font size=2>bumps under the device.</font> <br><br>
<font size=2>Is the body of the component ceramic or metal? If
ceramic, when you remove</font> <br>
<font size=2>the devise the solder bumps should remain intact, nice and
flat. Why not</font> <br>
<font size=2>leave these bumps as is and place the component, contacting
the existing</font> <br>
<font size=2>bumps while soldering? If the case is metal, and you
disturb the bumps</font> <br>
<font size=2>during removal, how about reapplying solder paste, placing
the component and</font> <br>
<font size=2>reflowing it with a hot air terminal? Another option
is to change the</font> <br>
<font size=2>drawing to allow the use of a thermal adhesive for
rework.</font> <br><br>
<font size=2>Jim Marsico</font> <br>
<font size=2>Senior Engineer</font> <br>
<font size=2>Production Engineering</font> <br>
<font size=2>EDO Electronics Systems Group</font> <br>
<font size=2>[log in to unmask]
<<a href="mailto:[log in to unmask]">mailto:[log in to unmask]</a>></font>
<br>
<font size=2>631-595-5879</font> <br><br>
<font size=2> -----Original
Message-----</font> <br>
<font size=2> From:
Becerra Alejandro [SMTP:[log in to unmask]]</font> <br>
<font size=2> Sent:
Wednesday, April 24, 2002 4:54 PM</font> <br>
<font size=2>
To: [log in to unmask]</font> <br>
<font size=2>
Subject: [TN] Repair of Circuit
with Solder Paste below</font> <br><br>
<font size=2> Hello to
All,</font> <br><br>
<font size=2> We have a circuit
that requires solder under it because in order to</font> <br>
<font size=2>have a good thermal dissipation.</font> <br>
<font size=2> The circuit is a
QFP48. When assembled in the line, the stencil has</font> <br>
<font size=2>apertures in the body of the component in order to apply
solder.</font> <br><br>
<font size=2> We have tried to
manually apply the solder with an iron tip, but</font> <br>
<font size=2>after cross-sectioning the repair component we have found
that</font> <br><br>
<font size=2> sometimes the
solder is not in contact with the component.</font> <br>
<font size=2> What could be the
appropriate procedure to repair this component?</font> <br><br>
<font size=2> Regards,</font>
<br><br>
<font size=2> Alejandro Becerra</font> <br><br>
<br>
<font size=2>---------------------------------------------------------------------------------</font> <br>
<font size=2>Technet Mail List provided as a free service by IPC using LISTSERV 1.8d</font> <br>
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<font size=2>information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700 ext.5315</font> <br>
<font size=2>---------------------------------------------------------------------------------</font> </blockquote><br>
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Date: Thu, 25 Apr 2002 09:55:27 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Pete Jones <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Pete Jones <[log in to unmask]>
Subject: FAB Question: laminate - 1 ply or 2??
Mime-Version: 1.0
Content-Type: text/plain; format=flowed
Hello all TechNetters,
What is the difference between using 1 ply of laminate or 2 in fab boards?
Is there a REAL concern that 1 ply will not be sufficient electrical
insolation? Or has resins now evolved enough to make it safe to use just one
ply?
I deal mostly, but not exclusively, with the military and would like to make
sure of my statement that 1 ply should be sufficient. Can I get reliable
references anywhere concerning this issue, one way or the other?
Thanks to all participants in this discussion.
Pete
_________________________________________________________________
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Date: Thu, 25 Apr 2002 16:01:45 +0200
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Freeze Spray Trouble Shooting
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Nice equipment but well the original post was about freezing electronic
component, and not to cool down dry machining operations.
For electronic application, the chemical used must be clean and not have
any contaminants in it, otherwise the electronic won't like it.
I see that Exair Vortex include a dust and oil filter but is it clean
enough for electronic parts ?
Another thing is that also it is small compared to a milling machine, the
Vortex is still quite bulky to use in a lab, specially with the hose for
the shop air.
Aother thing to consider is that most freeze spray are specified with low
electrostatic charge, because charge build-up could destroy components.
As for Bev Christian's concern about CFC, there are Freeze Spray without
CFC.
Jean-Luc Lehmann
SteveZeva@AOL
.COM To: [log in to unmask]
Sent by: cc:
TechNet Subject: Re: [TN] Freeze Spray Trouble Shooting
<[log in to unmask]
ORG>
25.04.02
02:44
Please
respond to
"TechNet
E-Mail
Forum.";
Please
respond to
SteveZeva
Hi David!
That's why this list is so valuable! They are still around!
Http://www.exair.com
Thanks!
-Steve Gregory-
Bev, Years ago (about 7) there was a company selling hand held Vortex
generators that plugged into 100 psi shop air.
These little jewels put out -40 degree C air as long as there was 100 psi
available. It also had to be dry nonlubed air. The company was called
EXAir. I don't know if they are still around. David A. Douthit
Manager
LoCan LLC
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Date: Thu, 25 Apr 2002 15:20:46 +0100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Steve Owen <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Steve Owen <[log in to unmask]>
Subject: Re: Repair of Circuit with Solder Paste below
X-To: Becerra Alejandro <[log in to unmask]>
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Alejandro,
We are currently looking into attaching the metal body of a SO8 component to
a pcb. Are you able to tell me whether or not you are using a stepped
stencil or a standard one, in order to acheive the required connection with
the body of the device to the PCB and also and the leg to the PCB ?. At the
moment we are using .006" thick stencils.
Regards
Steve.
-----Original Message-----
From: Becerra Alejandro [mailto:[log in to unmask]]
Sent: 25 April 2002 14:11
To: [log in to unmask]
Subject: Re: [TN] Repair of Circuit with Solder Paste below
We deposit solder paste under the component in order to help for heat
transfer.
The bottom side of the component is made of metal, then when I remove the
component we also remove the solder.
Applying solder paste again in the rework operation is a good idea.
Do you know how can we apply solder paste during rework?
Is it possible to use a mini-stencil? Where can I find a vendor for the
mini-stencil?
Thanks for your help.
Alejandro
-----Original Message-----
From: Marsico, James [ mailto:[log in to unmask]
<mailto:[log in to unmask]> ]
Sent: Thursday, April 25, 2002 6:10 AM
To: [log in to unmask]
Subject: Re: [TN] Repair of Circuit with Solder Paste below
If I understand correctly, you deposit solder paste under the component
during the initial build. After reflow, the paste solidifies and makes
contact with the bottom of the component for heat transfer. Your question
is what to do when replacing the component. How do you replace the solder
bumps under the device.
Is the body of the component ceramic or metal? If ceramic, when you remove
the devise the solder bumps should remain intact, nice and flat. Why not
leave these bumps as is and place the component, contacting the existing
bumps while soldering? If the case is metal, and you disturb the bumps
during removal, how about reapplying solder paste, placing the component and
reflowing it with a hot air terminal? Another option is to change the
drawing to allow the use of a thermal adhesive for rework.
Jim Marsico
Senior Engineer
Production Engineering
EDO Electronics Systems Group
[log in to unmask] < mailto:[log in to unmask]
<mailto:[log in to unmask]> >
631-595-5879
-----Original Message-----
From: Becerra Alejandro [SMTP:[log in to unmask]]
Sent: Wednesday, April 24, 2002 4:54 PM
To: [log in to unmask]
Subject: [TN] Repair of Circuit with Solder Paste below
Hello to All,
We have a circuit that requires solder under it because in order to
have a good thermal dissipation.
The circuit is a QFP48. When assembled in the line, the stencil has
apertures in the body of the component in order to apply solder.
We have tried to manually apply the solder with an iron tip, but
after cross-sectioning the repair component we have found that
sometimes the solder is not in contact with the component.
What could be the appropriate procedure to repair this component?
Regards,
Alejandro Becerra
----------------------------------------------------------------------------
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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=iso-8859-1">
<TITLE>RE: [TN] Repair of Circuit with Solder Paste below</TITLE>
<META content="MSHTML 5.50.4134.600" name=GENERATOR></HEAD>
<BODY>
<DIV><SPAN class=269234913-25042002><FONT face=Arial color=#0000ff
size=2>Alejandro,</FONT></SPAN></DIV>
<DIV><SPAN class=269234913-25042002><FONT face=Arial color=#0000ff
size=2></FONT></SPAN> </DIV>
<DIV><SPAN class=269234913-25042002><FONT face=Arial color=#0000ff size=2>We are
currently looking into attaching the metal body of a SO8 component to a pcb. Are
you able to tell me whether or not you are using a stepped stencil or a standard
one, in order to acheive the required connection with the body of the
device to the PCB and also and the leg to the PCB ?. At
the moment we are using .006" thick stencils.</FONT></SPAN></DIV>
<DIV><SPAN class=269234913-25042002></SPAN> </DIV>
<DIV><SPAN class=269234913-25042002><FONT face=Arial color=#0000ff
size=2>Regards</FONT></SPAN></DIV>
<DIV><SPAN class=269234913-25042002></SPAN> </DIV>
<DIV><SPAN class=269234913-25042002><FONT face=Arial color=#0000ff
size=2>Steve.</FONT> </SPAN></DIV>
<BLOCKQUOTE>
<DIV class=OutlookMessageHeader dir=ltr align=left><FONT face=Tahoma
size=2>-----Original Message-----<BR><B>From:</B> Becerra Alejandro
[mailto:[log in to unmask]]<BR><B>Sent:</B> 25 April 2002 14:11<BR><B>To:</B>
[log in to unmask]<BR><B>Subject:</B> Re: [TN] Repair of Circuit with Solder
Paste below<BR><BR></FONT></DIV>
<P><FONT size=2>We deposit solder paste under the component in order to help
for heat transfer.</FONT> <BR><FONT size=2>The bottom side of the component is
made of metal, then when I remove the component we also remove the
solder.</FONT> <BR><FONT size=2>Applying solder paste again in the rework
operation is a good idea.</FONT> <BR><FONT size=2>Do you know how can we apply
solder paste during rework?</FONT> <BR><FONT size=2>Is it possible to use a
mini-stencil? Where can I find a vendor for the mini-stencil?</FONT> </P>
<P><FONT size=2>Thanks for your help.</FONT> </P>
<P><FONT size=2>Alejandro</FONT> </P>
<P><FONT size=2>-----Original Message-----</FONT> <BR><FONT size=2>From:
Marsico, James [<A
href="mailto:[log in to unmask]">mailto:[log in to unmask]</A>]</FONT>
<BR><FONT size=2>Sent: Thursday, April 25, 2002 6:10 AM</FONT> <BR><FONT
size=2>To: [log in to unmask]</FONT> <BR><FONT size=2>Subject: Re: [TN] Repair of
Circuit with Solder Paste below</FONT> </P><BR>
<P><FONT size=2>If I understand correctly, you deposit solder paste under the
component</FONT> <BR><FONT size=2>during the initial build. After
reflow, the paste solidifies and makes</FONT> <BR><FONT size=2>contact with
the bottom of the component for heat transfer. Your question</FONT>
<BR><FONT size=2>is what to do when replacing the component. How do you
replace the solder</FONT> <BR><FONT size=2>bumps under the device.</FONT> </P>
<P><FONT size=2>Is the body of the component ceramic or metal? If
ceramic, when you remove</FONT> <BR><FONT size=2>the devise the solder bumps
should remain intact, nice and flat. Why not</FONT> <BR><FONT
size=2>leave these bumps as is and place the component, contacting the
existing</FONT> <BR><FONT size=2>bumps while soldering? If the case is
metal, and you disturb the bumps</FONT> <BR><FONT size=2>during removal, how
about reapplying solder paste, placing the component and</FONT> <BR><FONT
size=2>reflowing it with a hot air terminal? Another option is to change
the</FONT> <BR><FONT size=2>drawing to allow the use of a thermal adhesive for
rework.</FONT> </P>
<P><FONT size=2>Jim Marsico</FONT> <BR><FONT size=2>Senior Engineer</FONT>
<BR><FONT size=2>Production Engineering</FONT> <BR><FONT size=2>EDO
Electronics Systems Group</FONT> <BR><FONT size=2>[log in to unmask]
<<A
href="mailto:[log in to unmask]">mailto:[log in to unmask]</A>></FONT>
<BR><FONT size=2>631-595-5879</FONT> </P><BR>
<P><FONT size=2> -----Original
Message-----</FONT> <BR><FONT
size=2> From: Becerra
Alejandro [SMTP:[log in to unmask]]</FONT> <BR><FONT
size=2> Sent: Wednesday,
April 24, 2002 4:54 PM</FONT> <BR><FONT
size=2> To:
[log in to unmask]</FONT> <BR><FONT
size=2>
Subject: [TN] Repair of Circuit with
Solder Paste below</FONT> </P>
<P><FONT size=2> Hello to
All,</FONT> </P>
<P><FONT size=2> We have a circuit
that requires solder under it because in order to</FONT> <BR><FONT size=2>have
a good thermal dissipation.</FONT> <BR><FONT
size=2> The circuit is a QFP48. When
assembled in the line, the stencil has</FONT> <BR><FONT size=2>apertures in
the body of the component in order to apply solder.</FONT> </P>
<P><FONT size=2> We have tried to
manually apply the solder with an iron tip, but</FONT> <BR><FONT size=2>after
cross-sectioning the repair component we have found that</FONT> </P>
<P><FONT size=2> sometimes the
solder is not in contact with the component.</FONT> <BR><FONT
size=2> What could be the
appropriate procedure to repair this component?</FONT> </P>
<P><FONT size=2> Regards,</FONT>
</P>
<P><FONT size=2> Alejandro
Becerra</FONT> </P><BR><BR>
<P><FONT
size=2>---------------------------------------------------------------------------------</FONT>
<BR><FONT size=2>Technet Mail List provided as a free service by IPC using
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Date: Thu, 25 Apr 2002 09:20:01 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Becerra Alejandro <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Becerra Alejandro <[log in to unmask]>
Subject: Re: Repair of Circuit with Solder Paste below
X-To: Steve Owen <[log in to unmask]>
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Steve,
We are using a 0.006" thick stencil (No stepped).
We have not had problems in making contact the body of the component with
the solder.
Alejandro
-----Original Message-----
From: Steve Owen [mailto:[log in to unmask]]
Sent: Thursday, April 25, 2002 8:21 AM
To: TechNet E-Mail Forum.; Becerra Alejandro
Subject: RE: [TN] Repair of Circuit with Solder Paste below
Alejandro,
We are currently looking into attaching the metal body of a SO8 component to
a pcb. Are you able to tell me whether or not you are using a stepped
stencil or a standard one, in order to acheive the required connection with
the body of the device to the PCB and also and the leg to the PCB ?. At the
moment we are using .006" thick stencils.
Regards
Steve.
-----Original Message-----
From: Becerra Alejandro [mailto:[log in to unmask]]
Sent: 25 April 2002 14:11
To: [log in to unmask]
Subject: Re: [TN] Repair of Circuit with Solder Paste below
We deposit solder paste under the component in order to help for heat
transfer.
The bottom side of the component is made of metal, then when I remove the
component we also remove the solder.
Applying solder paste again in the rework operation is a good idea.
Do you know how can we apply solder paste during rework?
Is it possible to use a mini-stencil? Where can I find a vendor for the
mini-stencil?
Thanks for your help.
Alejandro
-----Original Message-----
From: Marsico, James [ mailto:[log in to unmask]
<mailto:[log in to unmask]> ]
Sent: Thursday, April 25, 2002 6:10 AM
To: [log in to unmask]
Subject: Re: [TN] Repair of Circuit with Solder Paste below
If I understand correctly, you deposit solder paste under the component
during the initial build. After reflow, the paste solidifies and makes
contact with the bottom of the component for heat transfer. Your question
is what to do when replacing the component. How do you replace the solder
bumps under the device.
Is the body of the component ceramic or metal? If ceramic, when you remove
the devise the solder bumps should remain intact, nice and flat. Why not
leave these bumps as is and place the component, contacting the existing
bumps while soldering? If the case is metal, and you disturb the bumps
during removal, how about reapplying solder paste, placing the component and
reflowing it with a hot air terminal? Another option is to change the
drawing to allow the use of a thermal adhesive for rework.
Jim Marsico
Senior Engineer
Production Engineering
EDO Electronics Systems Group
[log in to unmask] < mailto:[log in to unmask]
<mailto:[log in to unmask]> >
631-595-5879
-----Original Message-----
From: Becerra Alejandro [SMTP:[log in to unmask]]
Sent: Wednesday, April 24, 2002 4:54 PM
To: [log in to unmask]
Subject: [TN] Repair of Circuit with Solder Paste below
Hello to All,
We have a circuit that requires solder under it because in order to
have a good thermal dissipation.
The circuit is a QFP48. When assembled in the line, the stencil has
apertures in the body of the component in order to apply solder.
We have tried to manually apply the solder with an iron tip, but
after cross-sectioning the repair component we have found that
sometimes the solder is not in contact with the component.
What could be the appropriate procedure to repair this component?
Regards,
Alejandro Becerra
----------------------------------------------------------------------------
-----
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<TITLE>RE: [TN] Repair of Circuit with Solder Paste below</TITLE>
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<BODY>
<DIV><SPAN class=721191714-25042002><FONT face=Arial color=#0000ff
size=2>Steve,</FONT></SPAN></DIV>
<DIV><SPAN class=721191714-25042002><FONT face=Arial color=#0000ff size=2>We are
using a 0.006" thick stencil (No stepped).</FONT></SPAN></DIV>
<DIV><SPAN class=721191714-25042002><FONT face=Arial color=#0000ff size=2>We
have not had problems in making contact the body of the component with the
solder.</FONT></SPAN></DIV>
<DIV><SPAN class=721191714-25042002><FONT face=Arial color=#0000ff
size=2></FONT></SPAN> </DIV>
<DIV><SPAN class=721191714-25042002><FONT face=Arial color=#0000ff
size=2>Alejandro</FONT></SPAN></DIV>
<DIV class=OutlookMessageHeader dir=ltr align=left><FONT face=Tahoma
size=2>-----Original Message-----<BR><B>From:</B> Steve Owen
[mailto:[log in to unmask]]<BR><B>Sent:</B> Thursday, April 25, 2002 8:21
AM<BR><B>To:</B> TechNet E-Mail Forum.; Becerra Alejandro<BR><B>Subject:</B> RE:
[TN] Repair of Circuit with Solder Paste below<BR><BR></FONT></DIV>
<DIV><SPAN class=269234913-25042002><FONT face=Arial color=#0000ff
size=2>Alejandro,</FONT></SPAN></DIV>
<DIV><SPAN class=269234913-25042002><FONT face=Arial color=#0000ff
size=2></FONT></SPAN> </DIV>
<DIV><SPAN class=269234913-25042002><FONT face=Arial color=#0000ff size=2>We are
currently looking into attaching the metal body of a SO8 component to a pcb. Are
you able to tell me whether or not you are using a stepped stencil or a standard
one, in order to acheive the required connection with the body of the
device to the PCB and also and the leg to the PCB ?. At
the moment we are using .006" thick stencils.</FONT></SPAN></DIV>
<DIV><SPAN class=269234913-25042002></SPAN> </DIV>
<DIV><SPAN class=269234913-25042002><FONT face=Arial color=#0000ff
size=2>Regards</FONT></SPAN></DIV>
<DIV><SPAN class=269234913-25042002></SPAN> </DIV>
<DIV><SPAN class=269234913-25042002><FONT face=Arial color=#0000ff
size=2>Steve.</FONT> </SPAN></DIV>
<BLOCKQUOTE>
<DIV class=OutlookMessageHeader dir=ltr align=left><FONT face=Tahoma
size=2>-----Original Message-----<BR><B>From:</B> Becerra Alejandro
[mailto:[log in to unmask]]<BR><B>Sent:</B> 25 April 2002 14:11<BR><B>To:</B>
[log in to unmask]<BR><B>Subject:</B> Re: [TN] Repair of Circuit with Solder
Paste below<BR><BR></FONT></DIV>
<P><FONT size=2>We deposit solder paste under the component in order to help
for heat transfer.</FONT> <BR><FONT size=2>The bottom side of the component is
made of metal, then when I remove the component we also remove the
solder.</FONT> <BR><FONT size=2>Applying solder paste again in the rework
operation is a good idea.</FONT> <BR><FONT size=2>Do you know how can we apply
solder paste during rework?</FONT> <BR><FONT size=2>Is it possible to use a
mini-stencil? Where can I find a vendor for the mini-stencil?</FONT> </P>
<P><FONT size=2>Thanks for your help.</FONT> </P>
<P><FONT size=2>Alejandro</FONT> </P>
<P><FONT size=2>-----Original Message-----</FONT> <BR><FONT size=2>From:
Marsico, James [<A
href="mailto:[log in to unmask]">mailto:[log in to unmask]</A>]</FONT>
<BR><FONT size=2>Sent: Thursday, April 25, 2002 6:10 AM</FONT> <BR><FONT
size=2>To: [log in to unmask]</FONT> <BR><FONT size=2>Subject: Re: [TN] Repair of
Circuit with Solder Paste below</FONT> </P><BR>
<P><FONT size=2>If I understand correctly, you deposit solder paste under the
component</FONT> <BR><FONT size=2>during the initial build. After
reflow, the paste solidifies and makes</FONT> <BR><FONT size=2>contact with
the bottom of the component for heat transfer. Your question</FONT>
<BR><FONT size=2>is what to do when replacing the component. How do you
replace the solder</FONT> <BR><FONT size=2>bumps under the device.</FONT> </P>
<P><FONT size=2>Is the body of the component ceramic or metal? If
ceramic, when you remove</FONT> <BR><FONT size=2>the devise the solder bumps
should remain intact, nice and flat. Why not</FONT> <BR><FONT
size=2>leave these bumps as is and place the component, contacting the
existing</FONT> <BR><FONT size=2>bumps while soldering? If the case is
metal, and you disturb the bumps</FONT> <BR><FONT size=2>during removal, how
about reapplying solder paste, placing the component and</FONT> <BR><FONT
size=2>reflowing it with a hot air terminal? Another option is to change
the</FONT> <BR><FONT size=2>drawing to allow the use of a thermal adhesive for
rework.</FONT> </P>
<P><FONT size=2>Jim Marsico</FONT> <BR><FONT size=2>Senior Engineer</FONT>
<BR><FONT size=2>Production Engineering</FONT> <BR><FONT size=2>EDO
Electronics Systems Group</FONT> <BR><FONT size=2>[log in to unmask]
<<A
href="mailto:[log in to unmask]">mailto:[log in to unmask]</A>></FONT>
<BR><FONT size=2>631-595-5879</FONT> </P><BR>
<P><FONT size=2> -----Original
Message-----</FONT> <BR><FONT
size=2> From: Becerra
Alejandro [SMTP:[log in to unmask]]</FONT> <BR><FONT
size=2> Sent: Wednesday,
April 24, 2002 4:54 PM</FONT> <BR><FONT
size=2> To:
[log in to unmask]</FONT> <BR><FONT
size=2>
Subject: [TN] Repair of Circuit with
Solder Paste below</FONT> </P>
<P><FONT size=2> Hello to
All,</FONT> </P>
<P><FONT size=2> We have a circuit
that requires solder under it because in order to</FONT> <BR><FONT size=2>have
a good thermal dissipation.</FONT> <BR><FONT
size=2> The circuit is a QFP48. When
assembled in the line, the stencil has</FONT> <BR><FONT size=2>apertures in
the body of the component in order to apply solder.</FONT> </P>
<P><FONT size=2> We have tried to
manually apply the solder with an iron tip, but</FONT> <BR><FONT size=2>after
cross-sectioning the repair component we have found that</FONT> </P>
<P><FONT size=2> sometimes the
solder is not in contact with the component.</FONT> <BR><FONT
size=2> What could be the
appropriate procedure to repair this component?</FONT> </P>
<P><FONT size=2> Regards,</FONT>
</P>
<P><FONT size=2> Alejandro
Becerra</FONT> </P><BR><BR>
<P><FONT
size=2>---------------------------------------------------------------------------------</FONT>
<BR><FONT size=2>Technet Mail List provided as a free service by IPC using
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Date: Thu, 25 Apr 2002 07:21:25 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Debbie Goodwin <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Debbie Goodwin <[log in to unmask]>
Subject: Re: Repair of Circuit with Solder Paste below
X-To: Becerra Alejandro <[log in to unmask]>
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Try www.minimicrostencil.com <http://www.minimicrostencil.com> they sell
micro stencils for individual components.
Debbie Goodwin
Account Representative
10867 Portal Dr
Los Alamitos, CA 90720
Phone = (714) 252-0010
Fax = (714) 252-0026
PLEASE NOTE - Effective Immediately New e-mail address is:
[log in to unmask]
__________________________________________________
This message is intended for the use of the individual entity to which it is
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that any dissemination, distribution or copying of this communication is
strictly prohibited. If you have received this communication in error,
please notify us immediately by calling
714.252.0010 or returning the original message to us. Thank You.
-----Original Message-----
From: Becerra Alejandro [mailto:[log in to unmask]]
Sent: Thursday, April 25, 2002 6:11 AM
To: [log in to unmask]
Subject: Re: [TN] Repair of Circuit with Solder Paste below
We deposit solder paste under the component in order to help for heat
transfer.
The bottom side of the component is made of metal, then when I remove the
component we also remove the solder.
Applying solder paste again in the rework operation is a good idea.
Do you know how can we apply solder paste during rework?
Is it possible to use a mini-stencil? Where can I find a vendor for the
mini-stencil?
Thanks for your help.
Alejandro
-----Original Message-----
From: Marsico, James [ mailto:[log in to unmask]
<mailto:[log in to unmask]> ]
Sent: Thursday, April 25, 2002 6:10 AM
To: [log in to unmask]
Subject: Re: [TN] Repair of Circuit with Solder Paste below
If I understand correctly, you deposit solder paste under the component
during the initial build. After reflow, the paste solidifies and makes
contact with the bottom of the component for heat transfer. Your question
is what to do when replacing the component. How do you replace the solder
bumps under the device.
Is the body of the component ceramic or metal? If ceramic, when you remove
the devise the solder bumps should remain intact, nice and flat. Why not
leave these bumps as is and place the component, contacting the existing
bumps while soldering? If the case is metal, and you disturb the bumps
during removal, how about reapplying solder paste, placing the component and
reflowing it with a hot air terminal? Another option is to change the
drawing to allow the use of a thermal adhesive for rework.
Jim Marsico
Senior Engineer
Production Engineering
EDO Electronics Systems Group
[log in to unmask] < mailto:[log in to unmask]
<mailto:[log in to unmask]> >
631-595-5879
-----Original Message-----
From: Becerra Alejandro [SMTP:[log in to unmask]]
Sent: Wednesday, April 24, 2002 4:54 PM
To: [log in to unmask]
Subject: [TN] Repair of Circuit with Solder Paste below
Hello to All,
We have a circuit that requires solder under it because in order to
have a good thermal dissipation.
The circuit is a QFP48. When assembled in the line, the stencil has
apertures in the body of the component in order to apply solder.
We have tried to manually apply the solder with an iron tip, but
after cross-sectioning the repair component we have found that
sometimes the solder is not in contact with the component.
What could be the appropriate procedure to repair this component?
Regards,
Alejandro Becerra
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<TITLE>RE: [TN] Repair of Circuit with Solder Paste below</TITLE>
<META content="MSHTML 5.00.2614.3500" name=GENERATOR></HEAD>
<BODY>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN class=450413314-25042002>Try <A
href="http://www.minimicrostencil.com">www.minimicrostencil.com</A> they sell
micro stencils for individual components.</SPAN></FONT></DIV>
<DIV> </DIV>
<P><FONT face=Arial size=2>Debbie Goodwin</FONT> <BR><FONT face=Arial
size=2>Account Representative</FONT> <BR><FONT face=Arial size=2>10867 Portal
Dr</FONT> <BR><FONT face=Arial size=2>Los Alamitos, CA 90720</FONT> <BR><FONT
face=Arial size=2>Phone = (714) 252-0010 </FONT><BR><FONT face=Arial size=2>Fax
= (714) 252-0026</FONT> <BR><FONT face=Arial size=2>PLEASE NOTE - Effective
Immediately New e-mail address is: [log in to unmask]</FONT>
<BR><FONT face=Arial
size=2>__________________________________________________</FONT> <BR><FONT
face=Arial size=1>This message is intended for the use of the individual entity
to which it is addressed and may contain information that is privileged,
confidential and exempt from disclosure under applicable law. If the
reader of this message is not the intended recipient, or the employee or agent
responsible for delivering the message to the intended recipient, you are hereby
notified that any dissemination, distribution or copying of this communication
is strictly prohibited. If you have received this communication in error,
please notify us immediately by calling </FONT></P>
<P><FONT face=Arial size=1>714.252.0010 or returning the original message to
us. Thank You.</FONT> </P>
<BLOCKQUOTE style="MARGIN-RIGHT: 0px">
<DIV align=left class=OutlookMessageHeader dir=ltr><FONT face=Tahoma
size=2>-----Original Message-----<BR><B>From:</B> Becerra Alejandro
[mailto:[log in to unmask]]<BR><B>Sent:</B> Thursday, April 25, 2002 6:11
AM<BR><B>To:</B> [log in to unmask]<BR><B>Subject:</B> Re: [TN] Repair of Circuit
with Solder Paste below<BR><BR></DIV></FONT>
<P><FONT size=2>We deposit solder paste under the component in order to help
for heat transfer.</FONT> <BR><FONT size=2>The bottom side of the component is
made of metal, then when I remove the component we also remove the
solder.</FONT> <BR><FONT size=2>Applying solder paste again in the rework
operation is a good idea.</FONT> <BR><FONT size=2>Do you know how can we apply
solder paste during rework?</FONT> <BR><FONT size=2>Is it possible to use a
mini-stencil? Where can I find a vendor for the mini-stencil?</FONT> </P>
<P><FONT size=2>Thanks for your help.</FONT> </P>
<P><FONT size=2>Alejandro</FONT> </P>
<P><FONT size=2>-----Original Message-----</FONT> <BR><FONT size=2>From:
Marsico, James [<A
href="mailto:[log in to unmask]">mailto:[log in to unmask]</A>]</FONT>
<BR><FONT size=2>Sent: Thursday, April 25, 2002 6:10 AM</FONT> <BR><FONT
size=2>To: [log in to unmask]</FONT> <BR><FONT size=2>Subject: Re: [TN] Repair of
Circuit with Solder Paste below</FONT> </P><BR>
<P><FONT size=2>If I understand correctly, you deposit solder paste under the
component</FONT> <BR><FONT size=2>during the initial build. After
reflow, the paste solidifies and makes</FONT> <BR><FONT size=2>contact with
the bottom of the component for heat transfer. Your question</FONT>
<BR><FONT size=2>is what to do when replacing the component. How do you
replace the solder</FONT> <BR><FONT size=2>bumps under the device.</FONT> </P>
<P><FONT size=2>Is the body of the component ceramic or metal? If
ceramic, when you remove</FONT> <BR><FONT size=2>the devise the solder bumps
should remain intact, nice and flat. Why not</FONT> <BR><FONT
size=2>leave these bumps as is and place the component, contacting the
existing</FONT> <BR><FONT size=2>bumps while soldering? If the case is
metal, and you disturb the bumps</FONT> <BR><FONT size=2>during removal, how
about reapplying solder paste, placing the component and</FONT> <BR><FONT
size=2>reflowing it with a hot air terminal? Another option is to change
the</FONT> <BR><FONT size=2>drawing to allow the use of a thermal adhesive for
rework.</FONT> </P>
<P><FONT size=2>Jim Marsico</FONT> <BR><FONT size=2>Senior Engineer</FONT>
<BR><FONT size=2>Production Engineering</FONT> <BR><FONT size=2>EDO
Electronics Systems Group</FONT> <BR><FONT size=2>[log in to unmask]
<<A
href="mailto:[log in to unmask]">mailto:[log in to unmask]</A>></FONT>
<BR><FONT size=2>631-595-5879</FONT> </P><BR>
<P><FONT size=2> -----Original
Message-----</FONT> <BR><FONT
size=2> From: Becerra
Alejandro [SMTP:[log in to unmask]]</FONT> <BR><FONT
size=2> Sent: Wednesday,
April 24, 2002 4:54 PM</FONT> <BR><FONT
size=2> To:
[log in to unmask]</FONT> <BR><FONT
size=2>
Subject: [TN] Repair of Circuit with
Solder Paste below</FONT> </P>
<P><FONT size=2> Hello to
All,</FONT> </P>
<P><FONT size=2> We have a circuit
that requires solder under it because in order to</FONT> <BR><FONT size=2>have
a good thermal dissipation.</FONT> <BR><FONT
size=2> The circuit is a QFP48. When
assembled in the line, the stencil has</FONT> <BR><FONT size=2>apertures in
the body of the component in order to apply solder.</FONT> </P>
<P><FONT size=2> We have tried to
manually apply the solder with an iron tip, but</FONT> <BR><FONT size=2>after
cross-sectioning the repair component we have found that</FONT> </P>
<P><FONT size=2> sometimes the
solder is not in contact with the component.</FONT> <BR><FONT
size=2> What could be the
appropriate procedure to repair this component?</FONT> </P>
<P><FONT size=2> Regards,</FONT>
</P>
<P><FONT size=2> Alejandro
Becerra</FONT> </P><BR><BR>
<P><FONT
size=2>---------------------------------------------------------------------------------</FONT>
<BR><FONT size=2>Technet Mail List provided as a free service by IPC using
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Date: Thu, 25 Apr 2002 10:08:04 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Paul Signorelli <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Paul Signorelli <[log in to unmask]>
Subject: Re: Freeze Spray Trouble Shooting
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Don't forget about dendrites (Electro migration)...
Any time your board goes through the dew point with moisture
condensing,
and you have the power applied, you can grow dendrites. They can grow
under BGA's, Connectors ,etc.
That's why chilling (freeze misting) below the dew point out side of a
chamber is so hazardous.
Ref: IPC - TR-476 How to Avoid Metallic Growth Problems on Electronic
Hardware.
Even on a really pure surface the water can become conductive enough to
start a little
electro-chemical plating cell. In low voltage high impedance circuits
it will grow a short (dendrite) and the short will stay there.
Paul Signorelli
Reliability Engineer
Sanmina-SCI Corporation, Plant 12
702 Bandley Dr.
Fountain, CO 80817
eMail address: [log in to unmask]
Phone: 719-382-2352, Fax: 719-382-2520
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Date: Thu, 25 Apr 2002 10:53:54 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Dennis Petrosky <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Dennis Petrosky <[log in to unmask]>
Subject: Philips Signetics SCC 68692 Dual UART
X-cc: Don Furmanski <[log in to unmask]>
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For the Philips Signetics Dual UART, P/N SCC 68692 has anyone seen the
following problems with newer parts. We don't seem to have problems with
older parts, 1994 date code. We have the problems with newer parts 2000
and 2001 parts. We don't know where the date change actually occurred.
The problems don't happen 100% of the time on the new parts. Temperature
seems to affect it. The problem occurrs more often at higher
temperatures.
The problems are:
1. The baud rate is wrong by a factor of 16. If you select 19.2K baud
for example, the part tries for 307K baud.
2. The part drops bits on the output data and requires 3 tries on any
RS232 input to get the correct character. For instance, if you are
pressing a series of 1's on the keyboard, then press 2, it will take 3
presses of 2 before the 2 is actually outputed on the UART. The problem
seems to be in changing bits on the output word from low to high. If a
bit is high and is intended to be high, it will stay high. If a bit is
low and is intended to stay low, it will stay low. If a bit is high and
needs to go low, it will go low on the first key press. If a bit is low
and needs to go high, it will take 3 key presses to go high.
Dennis Petrosky
Circuit Card Manufacturing Engineer
607-763-4745
--=_alternative 0051D64385256BA6_=
Content-Type: text/html; charset="us-ascii"
<br><font size=2 face="sans-serif">For the Philips Signetics Dual UART, P/N SCC 68692 has anyone seen the following problems with newer parts. We don't seem to have problems with older parts, 1994 date code. We have the problems with newer parts 2000 and 2001 parts. We don't know where the date change actually occurred. The problems don't happen 100% of the time on the new parts. Temperature seems to affect it. The problem occurrs more often at higher temperatures.</font>
<br>
<br><font size=2 face="sans-serif">The problems are:</font>
<br><font size=2 face="sans-serif">1. The baud rate is wrong by a factor of 16. If you select 19.2K baud for example, the part tries for 307K baud.</font>
<br>
<br><font size=2 face="sans-serif">2. The part drops bits on the output data and requires 3 tries on any RS232 input to get the correct character. For instance, if you are pressing a series of 1's on the keyboard, then press 2, it will take 3 presses of 2 before the 2 is actually outputed on the UART. The problem seems to be in changing bits on the output word from low to high. If a bit is high and is intended to be high, it will stay high. If a bit is low and is intended to stay low, it will stay low. If a bit is high and needs to go low, it will go low on the first key press. If a bit is low and needs to go high, it will take 3 key presses to go high.</font>
<br>
<br>
<br>
<br><font size=2 face="sans-serif">Dennis Petrosky<br>
Circuit Card Manufacturing Engineer<br>
607-763-4745</font>
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Date: Thu, 25 Apr 2002 11:11:51 EDT
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Phillip Hinton <[log in to unmask]>
Subject: Re: Temperature Extreme
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All,
It is best to look at what the life-environment requiremnt is for the
assembly. In parts of this industry we qualify the solder and assembly by
aging at 200oC for 200 hours and then cycle for 100 cycles -40 to 200oC using
6 hours per cycle ( 2 hours top and 1 hour bottom). This represents the
operating environment that the assembly will experience. Surprisingly, some
of the soft solders do survive, but not Sn63. I would do the pre-cycle aging
if the operating environment is maybe 100oC, but would use 125oC for a 200
hours. The thermal aging induces many of the metallurgical changes that the
assembly may undergo in its lifetime, and shortens the test time need to
qualify a product. (the poor ones fail early and drastically). The thermal
aging oven time is cheap. If operating temperatures are lower, there is no
need to have the higher temperature, I use operating temperature plus 25oC.
No scientific basis, but it has seems to work.
Phil Hinton
--part1_4c.a82a78b.29f976b7_boundary
Content-Type: text/html; charset="US-ASCII"
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<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>All,
<BR>It is best to look at what the life-environment requiremnt is for the assembly. In parts of this industry we qualify the solder and assembly by aging at 200oC for 200 hours and then cycle for 100 cycles -40 to 200oC using 6 hours per cycle ( 2 hours top and 1 hour bottom). This represents the operating environment that the assembly will experience. Surprisingly, some of the soft solders do survive, but not Sn63. I would do the pre-cycle aging if the operating environment is maybe 100oC, but would use 125oC for a 200 hours. The thermal aging induces many of the metallurgical changes that the assembly may undergo in its lifetime, and shortens the test time need to qualify a product. (the poor ones fail early and drastically). The thermal aging oven time is cheap. If operating temperatures are lower, there is no need to have the higher temperature, I use operating temperature plus 25oC. No scientific basis, but it has se!
ems to work.
<BR>
<BR>Phil Hinton
<BR>
<BR> </FONT></HTML>
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Date: Thu, 25 Apr 2002 18:28:13 +0300
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Brian Ellis <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Brian Ellis <[log in to unmask]>
Subject: Re: Freeze Spray Trouble Shooting
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Jean-Luc
Bev's problem is not with CFCs but HFCs and HCFCs. HFCs do not cause
ozone depletion, like CFCs do but they do contribute greatly to climate
change (hundreds of times worse than CO2) and that is a real issue. To
the best of my knowledge, the only ones that are more or less
environmentally benign are the CO2 ones (unless you use propane, and the
resultant fire/explosion hazard ain't that funny), but you are taking a
quantum leap downwards in temperature with consequent thermal shock and
TCE differential. As for your hypothesis about electrostatics, the only
way you can make any gas conduct away a charge is to ionise it.
Otherwise, it is a damn good insulator and all of them are on equal
footing.
Brian
[log in to unmask] wrote:
>
> Nice equipment but well the original post was about freezing electronic
> component, and not to cool down dry machining operations.
>
> For electronic application, the chemical used must be clean and not have
> any contaminants in it, otherwise the electronic won't like it.
> I see that Exair Vortex include a dust and oil filter but is it clean
> enough for electronic parts ?
> Another thing is that also it is small compared to a milling machine, the
> Vortex is still quite bulky to use in a lab, specially with the hose for
> the shop air.
>
> Aother thing to consider is that most freeze spray are specified with low
> electrostatic charge, because charge build-up could destroy components.
>
> As for Bev Christian's concern about CFC, there are Freeze Spray without
> CFC.
>
> Jean-Luc Lehmann
>
> SteveZeva@AOL
> .COM To: [log in to unmask]
> Sent by: cc:
> TechNet Subject: Re: [TN] Freeze Spray Trouble Shooting
> <[log in to unmask]
> ORG>
>
> 25.04.02
> 02:44
> Please
> respond to
> "TechNet
> E-Mail
> Forum.";
> Please
> respond to
> SteveZeva
>
> Hi David!
>
> That's why this list is so valuable! They are still around!
> Http://www.exair.com
>
> Thanks!
>
> -Steve Gregory-
>
> Bev, Years ago (about 7) there was a company selling hand held Vortex
> generators that plugged into 100 psi shop air.
> These little jewels put out -40 degree C air as long as there was 100 psi
> available. It also had to be dry nonlubed air. The company was called
> EXAir. I don't know if they are still around. David A. Douthit
> Manager
> LoCan LLC
>
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Date: Thu, 25 Apr 2002 11:31:34 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Bev Christian <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Bev Christian <[log in to unmask]>
Subject: Re: Freeze Spray Trouble Shooting
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Jean-Luc and other TechNetters,
I just want to point out that I was absolutely NOT talking about CFC's
(chlorofluorocarbons), which of course I know are banned. I am concerned
about fully fluorinated compounds - no chlorine, no hydrogen, just
CF3(CF2)nCF3 and branched chain equivalents. I will shut up if someone can
tell me about cooling sprays that are not based on CF compounds - or on
relatively friendly gases like CO2 and N2.
Bev Christian
Research in Motion
-----Original Message-----
From: [log in to unmask] [mailto:[log in to unmask]]
Sent: April 25, 2002 10:02 AM
To: [log in to unmask]
Subject: Re: [TN] Freeze Spray Trouble Shooting
Nice equipment but well the original post was about freezing electronic
component, and not to cool down dry machining operations.
For electronic application, the chemical used must be clean and not have
any contaminants in it, otherwise the electronic won't like it.
I see that Exair Vortex include a dust and oil filter but is it clean
enough for electronic parts ?
Another thing is that also it is small compared to a milling machine, the
Vortex is still quite bulky to use in a lab, specially with the hose for
the shop air.
Aother thing to consider is that most freeze spray are specified with low
electrostatic charge, because charge build-up could destroy components.
As for Bev Christian's concern about CFC, there are Freeze Spray without
CFC.
Jean-Luc Lehmann
SteveZeva@AOL
.COM To: [log in to unmask]
Sent by: cc:
TechNet Subject: Re: [TN] Freeze Spray
Trouble Shooting
<[log in to unmask]
ORG>
25.04.02
02:44
Please
respond to
"TechNet
E-Mail
Forum.";
Please
respond to
SteveZeva
Hi David!
That's why this list is so valuable! They are still around!
Http://www.exair.com
Thanks!
-Steve Gregory-
Bev, Years ago (about 7) there was a company selling hand held Vortex
generators that plugged into 100 psi shop air.
These little jewels put out -40 degree C air as long as there was 100 psi
available. It also had to be dry nonlubed air. The company was called
EXAir. I don't know if they are still around. David A. Douthit
Manager
LoCan LLC
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Date: Thu, 25 Apr 2002 11:06:33 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Simms, Michael" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Simms, Michael" <[log in to unmask]>
Subject: Wanted: CM auditor
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Hello Technetters.
A local contract manufacturer recently contacted our organization
and requested assistance in finding an auditor familar with
electronic contract manufacturing. The Cm would like an auditor
or consultant to review their organization and help them improve it.
Interested parties are encouraged to contact Mr. Mukesh Vasani
of Creative Hi-Tech Ltd.in Elk Grove Village, Illinois
E mail @ [log in to unmask]
Web: www.creativehitech.com
Thanks for any help T'netters
Mike Simms
Trace Laboratories - Central
(ph.) 847-934-5300
(fax) 847-934-4600M
1150 West Euclid Avenue
Palatine, IL 60067
www.tracelabs.com
Notice: This message is confidential and intended for the private use of
the addressee only.
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Date: Thu, 25 Apr 2002 09:11:08 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
K HERK <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: K HERK <[log in to unmask]>
Subject: BOW/WARP
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Is there a chart for PCB bowing ?
I have a typical value of 0.007"/1" bow, but a
customer wants to know the
bow for the specific case of 1.6mm FR-4. Are there
different "ranges" of
bowing that a PCB is specified at ?
Also, how does temperature affect bowing ? The
customer says that bowing
occurs during solder reflow where the temperatures are
a few 100 degrees
Celsius.
__________________________________________________
Do You Yahoo!?
Yahoo! Games - play chess, backgammon, pool and more
http://games.yahoo.com/
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Date: Thu, 25 Apr 2002 09:28:42 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Bloomquist, Ken" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Bloomquist, Ken" <[log in to unmask]>
Subject: Re: ESSENTIAL MLB STUFF
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Hey MoonMan,
The Electronics Manufacturers Association (EMA), in the Northwest, has a web
site that I'd be happy to post your file on and any others until it gets out
of hand ;-). We support anything that is nonprofit and enriches the world of
electronics manufacturing.
Let me know if we can be of service.
Ken Bloomquist
Secretary, EMA
www.ema-wa.org
-----Original Message-----
From: Earl Moon [mailto:[log in to unmask]]
Sent: Thursday, April 25, 2002 4:31 AM
To: [log in to unmask]
Subject: [TN] ESSENTIAL MLB STUFF
Per off line requests, I've sent nearly 20 essential, to me, MLB
requirements. The package size is about 500k and again is getting a bit
cumbersome to email by myself.
Daan, are you there. If you would be so kind, I'll send you the package and
you can post it on your great site.
MoonMan
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Date: Thu, 25 Apr 2002 12:53:46 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Torres, Roberto" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Torres, Roberto" <[log in to unmask]>
Subject: Re: Microscopes
X-To: Brian Ellis <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Brian;
Well noted, just looks odd on the .jpg files.
Bob
-----Original Message-----
From: Brian Ellis [mailto:[log in to unmask]]
Sent: Wednesday, April 24, 2002 11:12 PM
To: TechNet E-Mail Forum.; Torres, Roberto
Subject: Re: [TN] Microscopes
Roberto
Does this matter? If you use a 4.3 or higher Mpixel camera, there are
sufficient pixels left in the centre zone to record what you need to
see, nicht war?
Brian
"Torres, Roberto" wrote:
>
> All;
>
> Thanks for the suggestions on Microscopes and Digital photographs.
> The suggestion from Charles was of particular interest. Seems like
> most use the method we use here now put the digital camera to the
> lens of the microscope and snap away, it is just with this method
> we tend to get a lot of telescope images, that is round and black
> around the edges.
>
> Again thanks for all the input.
>
> Regards
> Bob Torres
>
>
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Date: Thu, 25 Apr 2002 12:07:27 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Tuan Bui <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Tuan Bui <[log in to unmask]>
Subject: Immersion Gold Vs Immersion Tin for 0201 landpatterns
Hello Technetters,
I'm a new member to this board, and hope some technetters could void their
opinions and advices on this issues.
We are currently dealing with a 0201 SMT process and have some issues with
a HASL 0201 landpatterns. The HASL PCB has non-uniformed finshed surface,
and results in tombstones and solderballs after the reflow process. We then
switch to Immersion gold 0201 landpatterns and the issues of solderballs
and tombstones went away. The average cost different between HASl and
Immersion gold (7-10 micron)is about 6 - 8 % in cost. Another PCB vendor
introduced us to Immersion Tin (white tin) to reduce the additional cost of
Immersion Gold pads (about 2-5 % cost different between HASl and Tin). We
have used Immersion Gold in many of our prototype products and having
really high yeilds, but we have not try the Immersion Tin pad finished and
wonder if they behave like the Immersion Gold. The vendor also mentioned
that the Tin finished will oxidize and have a shelf life of 12 months.
BTW, We are using "No Clean" process with Convection air oven.
Any technetter has experienced in both pads surface finished ( Gold Vs Tin)
is greatly appreciates.
Tuan Bui
Process Dev Eng
Conexant Systems Inc.
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Date: Thu, 25 Apr 2002 13:38:32 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Guy Ramsey <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Guy Ramsey <[log in to unmask]>
Subject: Re: Accelerated test for simulation of storage of PCBs with
surface finish white tin
X-To: Peter Hefti <[log in to unmask]>
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="----=_NextPart_000_0001_01C1EC5E.7E04F6A0"
This is a multi-part message in MIME format.
------=_NextPart_000_0001_01C1EC5E.7E04F6A0
Content-Type: text/plain;
charset="iso-8859-1"
Content-Transfer-Encoding: 7bit
I am not aware of a industry consensus standard for stressing "white tin"
that can be correlated to a 6-12 month shelf life. 85-85-8 seems like a good
start but wetting forces between tin-lead solder and the tin finish are not
the same as forces acting solder to solder. My experience, even with
pristine immersion tin finish the forces are lower and slower. The process
is different because white tin is a combination of tin and organic finish.
I'm sure there are members of this forum that can add to this thread.
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Peter Hefti
Sent: Thursday, April 25, 2002 3:30 AM
To: [log in to unmask]
Subject: [TN] Accelerated test for simulation of storage of PCBs with
surface finish white tin
Hello TechNet:
We are searching for a method of accelerated aging of PCBs with surface
finish in white tin (chemical tin).
This method should be recognized , in order to simulate the storage of 6 or
12 month under normal conditions.
(85/85/1d or 2d test ??)
After such an accelerated test, the solderability will be tested by the
wetting balance method.
Thank you for your answer
With best regards
Peter Hefti
------=_NextPart_000_0001_01C1EC5E.7E04F6A0
Content-Type: text/html;
charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META content=3D"text/html; charset=3Dwindows-1252" =
http-equiv=3DContent-Type>
<META content=3D"MSHTML 5.00.3105.105" name=3DGENERATOR></HEAD>
<BODY>
<DIV><FONT color=3D#0000ff face=3DArial size=3D2><SPAN =
class=3D602182717-25042002>I am=20
not aware of a industry consensus standard for stressing "white tin" =
that can be=20
correlated to a 6-12 month shelf life. 85-85-8 seems like a good start =
but=20
wetting forces between tin-lead solder and the tin finish are not the =
same as=20
forces acting solder to solder. My experience, even with pristine =
immersion tin=20
finish the forces are lower and slower. The process is different because =
white=20
tin is a combination of tin and organic finish.</SPAN></FONT></DIV>
<DIV><SPAN class=3D602182717-25042002></SPAN><FONT face=3D"Times New =
Roman"><FONT=20
size=3D2><SPAN class=3D602182717-25042002><FONT color=3D#0000ff=20
face=3DArial></FONT></SPAN></FONT></FONT> </DIV>
<DIV><FONT face=3D"Times New Roman"><FONT size=3D2><SPAN=20
class=3D602182717-25042002><FONT color=3D#0000ff face=3DArial>I'm sure =
there=20
are members of this forum that can add to this=20
thread. </FONT></SPAN></FONT></FONT></DIV>
<DIV><FONT face=3D"Times New Roman"><FONT size=3D2><SPAN=20
class=3D602182717-25042002></SPAN></FONT></FONT> </DIV>
<DIV><FONT size=3D2><FONT face=3D"Times New Roman"><SPAN=20
class=3D602182717-25042002> </SPAN>-----Original =
Message-----<BR><B>From:</B>=20
TechNet [mailto:[log in to unmask]]<B>On Behalf Of</B> Peter =
Hefti<BR><B>Sent:</B>=20
Thursday, April 25, 2002 3:30 AM<BR><B>To:</B>=20
[log in to unmask]<BR><B>Subject:</B> [TN] Accelerated test for simulation =
of=20
storage of PCBs with surface finish white tin<FONT color=3D#0000ff=20
face=3DArial><SPAN=20
class=3D602182717-25042002> </SPAN></FONT></FONT></FONT></DIV>
<DIV><FONT size=3D2><FONT face=3D"Times New Roman"><FONT color=3D#0000ff =
face=3DArial><SPAN =
class=3D602182717-25042002> </SPAN></FONT></FONT><BR><FONT=20
face=3Dsans-serif>Hello TechNet:</FONT></FONT> <BR><BR><FONT =
face=3Dsans-serif=20
size=3D2>We are searching for a method of accelerated aging of PCBs with =
surface=20
finish in white tin (chemical tin).</FONT> <BR><FONT =
face=3Dsans-serif=20
size=3D2>This method should be recognized , in order to simulate the =
storage of 6=20
or 12 month under normal conditions.</FONT> <BR><FONT face=3Dsans-serif=20
size=3D2>(85/85/1d or 2d test ??)</FONT> <BR><FONT =
face=3Dsans-serif=20
size=3D2>After such an accelerated test, the solderability will be =
tested by the=20
wetting balance method.</FONT> <BR><BR><FONT face=3Dsans-serif =
size=3D2>Thank you=20
for your answer</FONT> <BR><BR><FONT face=3Dsans-serif size=3D2>With =
best=20
regards</FONT> <BR><BR><FONT face=3Dsans-serif size=3D2>Peter Hefti=20
</FONT></DIV></BODY></HTML>
------=_NextPart_000_0001_01C1EC5E.7E04F6A0--
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Date: Thu, 25 Apr 2002 10:47:06 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
K HERK <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: K HERK <[log in to unmask]>
Subject: bow/warp
X-To: Tuan Bui <[log in to unmask]>
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Is there a chart for PCB bowing ?
I have a typical value of 0.007"/1" bow, but a
customer wants to know the
bow for the specific case of 1.6mm FR-4. Are there
different "ranges" of
bowing that a PCB is specified at ?
Also, how does temperature affect bowing ? The
customer says that bowing
occurs during solder reflow where the temperatures are
a few 100 degrees
Celsius.
__________________________________________________
Do You Yahoo!?
Yahoo! Games - play chess, backgammon, pool and more
http://games.yahoo.com/
---------------------------------------------------------------------------------
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=========================================================================
Date: Thu, 25 Apr 2002 19:47:43 +0200
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"D.Terstegge" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "D.Terstegge" <[log in to unmask]>
Subject: Re: ESSENTIAL MLB STUFF
X-To: Earl Moon <[log in to unmask]>
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="----=_NextPart_000_010C_01C1EC92.10C96920"
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I uploaded the document to my website. It can be accesed from =
http://www.smtinfo.net/startpage.html in the "design for manufacturing" =
section, look for "Essential MLB Information From Design Through Proof =
Of Design"
Didn't have the time to read it yet, but on a first scan it looks like a =
must-read !
Daan Terstegge
http://www.smtinfo.net
----- Original Message -----=20
From: Earl Moon=20
To: [log in to unmask]
Sent: Thursday, April 25, 2002 1:31 PM
Subject: [TN] ESSENTIAL MLB STUFF
Per off line requests, I've sent nearly 20 essential, to me, MLB
requirements. The package size is about 500k and again is getting a =
bit
cumbersome to email by myself.
Daan, are you there. If you would be so kind, I'll send you the =
package and
you can post it on your great site.
MoonMan
=
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charset="Windows-1252"
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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META http-equiv=3DContent-Type content=3D"text/html; =
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<BODY bgColor=3D#ffffff>
<DIV>I uploaded the document to my website. It can be accesed =
from <A=20
href=3D"http://www.smtinfo.net/startpage.html">http://www.smtinfo.net/sta=
rtpage.html</A> in=20
the "design for manufacturing" section, look for "<A=20
href=3D"http://www.smtinfo.net/docs/ESSENTIALMLB1.doc">Essential MLB =
Information=20
From Design Through Proof Of Design</A>"</DIV>
<DIV>Didn't have the time to read it yet, but on a first scan it looks =
like a=20
must-read !</DIV>
<DIV> </DIV>
<DIV>Daan Terstegge</DIV>
<DIV><A href=3D"http://www.smtinfo.net">http://www.smtinfo.net</A></DIV>
<DIV> </DIV>
<DIV> </DIV>
<DIV>----- Original Message ----- </DIV>
<BLOCKQUOTE=20
style=3D"PADDING-RIGHT: 0px; PADDING-LEFT: 5px; MARGIN-LEFT: 5px; =
BORDER-LEFT: #000000 2px solid; MARGIN-RIGHT: 0px">
<DIV=20
style=3D"BACKGROUND: #e4e4e4; FONT: 10pt arial; font-color: =
black"><B>From:</B>=20
<A [log in to unmask] href=3D"mailto:[log in to unmask]">Earl =
Moon</A>=20
</DIV>
<DIV style=3D"FONT: 10pt arial"><B>To:</B> <A [log in to unmask]
href=3D"mailto:[log in to unmask]">[log in to unmask]</A> </DIV>
<DIV style=3D"FONT: 10pt arial"><B>Sent:</B> Thursday, April 25, 2002 =
1:31=20
PM</DIV>
<DIV style=3D"FONT: 10pt arial"><B>Subject:</B> [TN] ESSENTIAL MLB =
STUFF</DIV>
<DIV><BR></DIV>Per off line requests, I've sent nearly 20 essential, =
to me,=20
MLB<BR>requirements. The package size is about 500k and again is =
getting=20
a bit<BR>cumbersome to email by myself.<BR><BR>Daan, are you there. If =
you=20
would be so kind, I'll send you the package and<BR>you can post it on =
your=20
great=20
=
site.<BR><BR>MoonMan<BR><BR>---------------------------------------------=
------------------------------------<BR>Technet=20
Mail List provided as a free service by IPC using LISTSERV 1.8d<BR>To=20
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Digest<BR>Search the archives of previous posts at: <A=20
=
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s</A><BR>Please=20
visit IPC web site <A=20
=
href=3D"http://www.ipc.org/html/forum.htm">http://www.ipc.org/html/forum.=
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Date: Thu, 25 Apr 2002 13:48:45 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"WEEKES, MICHAEL HS-SNS" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "WEEKES, MICHAEL HS-SNS" <[log in to unmask]>
Subject: Re: BOW/WARP
X-To: K HERK <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain
IPC 600 page 56 section 2.11 on flatness, but your assembly line/ process
really indicates what's acceptable. Use your least robust machine (the one
that cannot tolerate bow/twist) to determine your REAL requirement. Each
manufacturer (pick/place) recommends a bow/twist max in mm or in. It also
depends on PWB thickness - a 0.030" telecon PWB is much more flimsy than a
0.125" high voltage PWB. In line conveyors hate excessive bow or twist,
especially.
PS. PWBs can be flattened with a soak at warm temps under a weight.
Mike
-----Original Message-----
From: K HERK [mailto:[log in to unmask]]
Sent: Thursday, April 25, 2002 11:11 AM
To: [log in to unmask]
Subject: [TN] BOW/WARP
Is there a chart for PCB bowing ?
I have a typical value of 0.007"/1" bow, but a
customer wants to know the
bow for the specific case of 1.6mm FR-4. Are there
different "ranges" of
bowing that a PCB is specified at ?
Also, how does temperature affect bowing ? The
customer says that bowing
occurs during solder reflow where the temperatures are
a few 100 degrees
Celsius.
__________________________________________________
Do You Yahoo!?
Yahoo! Games - play chess, backgammon, pool and more
http://games.yahoo.com/
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Date: Thu, 25 Apr 2002 13:54:28 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"WEEKES, MICHAEL HS-SNS" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "WEEKES, MICHAEL HS-SNS" <[log in to unmask]>
Subject: Re: Accelerated test for simulation of storage of PCBs with
surface finish white tin
X-To: Peter Hefti <[log in to unmask]>
MIME-Version: 1.0
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for a PCB with vias/thru holes
try 140 F with 95% RH for 96 hrs.
then reflow 3 cycles
wave solder
take a look at flow up thru holes/vias
some believe this represents 8 months of shelf life approx.
(from a Mike Carano IPC workshop) - thanks Mike!
Mike Weekes
-----Original Message-----
From: Peter Hefti [mailto:[log in to unmask]]
Sent: Thursday, April 25, 2002 2:30 AM
To: [log in to unmask]
Subject: [TN] Accelerated test for simulation of storage of PCBs with
surface finish white tin
Hello TechNet:
We are searching for a method of accelerated aging of PCBs with surface
finish in white tin (chemical tin).
This method should be recognized , in order to simulate the storage of 6 or
12 month under normal conditions.
(85/85/1d or 2d test ??)
After such an accelerated test, the solderability will be tested by the
wetting balance method.
Thank you for your answer
With best regards
Peter Hefti
------_=_NextPart_001_01C1EC82.3E851FE0
Content-Type: text/html
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=US-ASCII">
<META content="MSHTML 5.50.4616.200" name=GENERATOR></HEAD>
<BODY>
<DIV><SPAN class=965115117-25042002><FONT face=Arial color=#0000ff size=2>for a
PCB with vias/thru holes</FONT></SPAN></DIV>
<DIV><SPAN class=965115117-25042002><FONT face=Arial color=#0000ff
size=2></FONT></SPAN> </DIV>
<DIV><SPAN class=965115117-25042002><FONT face=Arial color=#0000ff size=2>try
140 F with 95% RH for 96 hrs.</FONT></SPAN></DIV>
<DIV><SPAN class=965115117-25042002><FONT face=Arial color=#0000ff size=2>then
reflow 3 cycles</FONT></SPAN></DIV>
<DIV><SPAN class=965115117-25042002><FONT face=Arial color=#0000ff size=2>wave
solder</FONT></SPAN></DIV>
<DIV><SPAN class=965115117-25042002><FONT face=Arial color=#0000ff size=2>take a
look at flow up thru holes/vias</FONT></SPAN></DIV>
<DIV><SPAN class=965115117-25042002><FONT face=Arial color=#0000ff
size=2></FONT></SPAN> </DIV>
<DIV><SPAN class=965115117-25042002><FONT face=Arial color=#0000ff size=2>some
believe this represents 8 months of shelf life approx.</FONT></SPAN></DIV>
<DIV><SPAN class=965115117-25042002><FONT face=Arial color=#0000ff size=2>(from
a Mike Carano IPC workshop) - thanks Mike!</FONT></SPAN></DIV>
<DIV><SPAN class=965115117-25042002><FONT face=Arial color=#0000ff
size=2></FONT></SPAN> </DIV>
<DIV><SPAN class=965115117-25042002><FONT face=Arial color=#0000ff size=2>Mike
Weekes</FONT></SPAN></DIV>
<BLOCKQUOTE>
<DIV class=OutlookMessageHeader dir=ltr align=left><FONT face=Tahoma
size=2>-----Original Message-----<BR><B>From:</B> Peter Hefti
[mailto:[log in to unmask]]<BR><B>Sent:</B> Thursday, April 25, 2002 2:30
AM<BR><B>To:</B> [log in to unmask]<BR><B>Subject:</B> [TN] Accelerated test for
simulation of storage of PCBs with surface finish white
tin<BR><BR></FONT></DIV><BR><FONT face=sans-serif size=2>Hello TechNet:</FONT>
<BR><BR><FONT face=sans-serif size=2>We are searching for a method of
accelerated aging of PCBs with surface finish in white tin (chemical
tin).</FONT> <BR><FONT face=sans-serif size=2>This method should be
recognized , in order to simulate the storage of 6 or 12 month under normal
conditions.</FONT> <BR><FONT face=sans-serif size=2>(85/85/1d or 2d test
??)</FONT> <BR><FONT face=sans-serif size=2>After such an accelerated test,
the solderability will be tested by the wetting balance method.</FONT>
<BR><BR><FONT face=sans-serif size=2>Thank you for your answer</FONT>
<BR><BR><FONT face=sans-serif size=2>With best regards</FONT> <BR><BR><FONT
face=sans-serif size=2>Peter Hefti </FONT></BLOCKQUOTE></BODY></HTML>
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Date: Thu, 25 Apr 2002 15:09:12 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Steve Kelly <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Steve Kelly <[log in to unmask]>
Subject: test for film residue
MIME-Version: 1.0
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Does anyone know of a test to look for film/stripper residue after copper
stripping. Thanks for the help. Steve Kelly
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Date: Thu, 25 Apr 2002 15:12:44 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"WEEKES, MICHAEL HS-SNS" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "WEEKES, MICHAEL HS-SNS" <[log in to unmask]>
Subject: flex coverlayer min. spacing from any interconnect / via
MIME-Version: 1.0
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request for critique / review:
please review the attached and critique for submittal for next IPC A 600 or
flex spec. rev.:
Mike Weekes
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Content-Type: text/html;
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<DIV><SPAN class=891015818-25042002><FONT face=Arial color=#0000ff
size=2>request for critique / review:</FONT></SPAN></DIV>
<DIV><SPAN class=891015818-25042002><FONT face=Arial color=#0000ff
size=2></FONT></SPAN> </DIV>
<DIV><SPAN class=891015818-25042002><FONT face=Arial color=#0000ff size=2>please
review the attached and critique for submittal for next IPC A 600 or flex spec.
rev.:</FONT></SPAN></DIV>
<DIV><SPAN class=891015818-25042002></SPAN> </DIV>
<DIV><SPAN class=891015818-25042002> <FONT face=Arial color=#0000ff
size=2>Mike Weekes</FONT></SPAN></DIV></BODY></HTML>
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Date: Thu, 25 Apr 2002 15:04:58 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Ken Carlile <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Ken Carlile <[log in to unmask]>
Subject: Failure rate to Package Size
We are currently looking to minimize board space by switching from 0805 and
0603 parts to either 0402 or 0201 where applicable. I have read responses
from the archive indicating pro's and con's, but I was wondering from a
production standpoint if there is any factual data for the increase in
solderability issues resulting from reduced packaging. Are there any QA
types out there with this rework data? I would have to believe brindging
and tombstoning increase.
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Date: Thu, 25 Apr 2002 18:33:43 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
[log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Dave Hillman <[log in to unmask]>
Subject: Re: Accelerated test for simulation of storage of PCBs with
surface finish white tin
X-To: [log in to unmask]
MIME-Version: 1.0
Content-type: text/plain; charset=iso-8859-1
Content-transfer-encoding: quoted-printable
Hi Peter! Let me redefine a misconception - if you are truly going to "=
age"
a pwb sample then the aging method would produce either the same oxide
conditions, the same intermetallic conditions or the combination of
oxide/intermetallic conditions that the pwb sample would have after sit=
ting
in storage for X amount of time. Unfortunately surface finish oxidation=
doesn't behave well in accelerated conditioning - typically you
force/produce oxide thicknesses/species which are not present under nor=
mal
storage conditions. Intermetallic growth is better behaved and there ha=
ve
been some good data published showing those relationships. I recommend =
you
look at two conditioning methods: the use of humidity and the use of
temperature. Tin surface finishes tend to degrade quickly under humid
conditions in terms oxide growth. The use of temperature will highlight=
intermetallic growth problems. Now what recipes to use? Many investigat=
ions
have used 85C/85% RH as their humidity parameters for oxide growth - yo=
u
get to pick the time. Many investigations use either 125C for 8 hours o=
r
150C for 16 hours as their temperature parameters for intermetallic gro=
wth.
Instead of expecting to "age" the surface finish, looking at your
conditioning as attempting to determine the "robustness" of the surface=
finish for a set of conditions (you will be much happier in the long ru=
n).
You will have to decide just how "robust" you want the coating. For
example, are acceptable wetting balance values after 48 hours of 85/85
exposure robust enough for your manufacturing process to have high yiel=
ds?
Only you can determine that. The IPC Alternative Final Finishes task gr=
oup,
chaired by Denny Fritz of MacDermid, is in the final stages of issuing=
a
report that attempts to answer the question " is there a
time/temperature/humidity conditioning parameter set which can be used =
for
a variety of finishes to predict robustness?" - the JSTD-003 committee
intends to use the Alt Finish committee efforts to revise the current
"steam aging" methodology. Hope this helps.
Dave Hillman
Rockwell Collins
[log in to unmask]
Peter Hefti <[log in to unmask]>@ipc.org> on 04/25/2002 02:29:50 AM
Please respond to "TechNet E-Mail Forum." <[log in to unmask]>; Please res=
pond
to Peter Hefti <[log in to unmask]>
Sent by: TechNet <[log in to unmask]>
To: [log in to unmask]
cc:
Subject: [TN] Accelerated test for simulation of storage of PCBs wit=
h
surface finish white tin
Hello TechNet:
We are searching for a method of accelerated aging of PCBs with surface=
finish in white tin (chemical =A0tin).
This method should be recognized , in order to simulate the storage of =
6 or
12 month under normal conditions.
(85/85/1d or 2d =A0test ??)
After such an accelerated test, the solderability will be tested by the=
wetting balance method.
Thank you for your answer
With best regards
Peter Hefti
=
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Date: Thu, 25 Apr 2002 20:50:54 EDT
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Rudy Sedlak <[log in to unmask]>
Subject: Re: test for film residue
MIME-Version: 1.0
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In a message dated 4.25.02 12:23:23 PM Pacific Daylight Time, [log in to unmask]
writes:
> Does anyone know of a test to look for film/stripper residue after copper
> stripping.
Assume you mean after stripping film from Copper?
Stripper residue is a tough one, and not real likely to be an issue.
Tarnish could be another issue that is very difficult to test for except by
sight. Depending on stripper, this could be significant....the clue is, if
the problem gets worse as the stripper chemistry gets older, it is quite
possibly tarnish...
Film residue is the most likely residue. One way to test that is a good
test, but, can make your test board need rework is to drop on an immersion
plating solution. Two different ones are common. Some people use immersion
Tin to test if the surface is clean. A drop should plate uniformly, and
adherently. Another test is to drop on Silver Nitrate solution...usually use
the stuff that is used for titration in the lab. The surface should
essentially immediately turn black, and it should be adherent.
Another residue problem that can occur, and especially in old stripper
chemistry, is immersion Tin residues....this does not relate to the test
above. Rather, your stripper chemistry can pickup Tin from the oxide on the
plating on outerlayers, and redeposit this on the Copper next to it. The
potential for this problem is magnified tremendously if you strip in a tank,
rather than exclusively in sprays, and can be strongly affected by the
condition of the Tin plating solution. If your Tin electroplating solution
looks very milky, this is disperse Tin oxide, which co-deposits with the Tin
metal, then easily dissolves in certain kinds of stripper chemistry, and
redeposits, sometimes even is sprays, on the adjacent Copper.
The film residues have become an especial problem in recent years, as the new
generation of photoresists, which stick VERY well, require specially
formulated types of stripper chemistry.
I probably have told you more than you want to know, but, in case I haven't,
you can call me to discuss it.
Rudy Sedlak
RD Chemical Company 650-962-8004
--part1_148.d89a811.29f9fe6e_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
<HTML><FONT FACE=arial,helvetica><FONT SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0">In a message dated 4.25.02 12:23:23 PM Pacific Daylight Time, [log in to unmask] writes:<BR>
<BR>
<BR>
<BLOCKQUOTE TYPE=CITE style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">Does anyone know of a test to look for film/stripper residue after copper<BR>
stripping. </BLOCKQUOTE><BR>
<BR>
Assume you mean after stripping film from Copper?<BR>
<BR>
Stripper residue is a tough one, and not real likely to be an issue.<BR>
<BR>
Tarnish could be another issue that is very difficult to test for except by sight. Depending on stripper, this could be significant....the clue is, if the problem gets worse as the stripper chemistry gets older, it is quite possibly tarnish...<BR>
<BR>
Film residue is the most likely residue. One way to test that is a good test, but, can make your test board need rework is to drop on an immersion plating solution. Two different ones are common. Some people use immersion Tin to test if the surface is clean. A drop should plate uniformly, and adherently. Another test is to drop on Silver Nitrate solution...usually use the stuff that is used for titration in the lab. The surface should essentially immediately turn black, and it should be adherent.<BR>
<BR>
Another residue problem that can occur, and especially in old stripper chemistry, is immersion Tin residues....this does not relate to the test above. Rather, your stripper chemistry can pickup Tin from the oxide on the plating on outerlayers, and redeposit this on the Copper next to it. The potential for this problem is magnified tremendously if you strip in a tank, rather than exclusively in sprays, and can be strongly affected by the condition of the Tin plating solution. If your Tin electroplating solution looks very milky, this is disperse Tin oxide, which co-deposits with the Tin metal, then easily dissolves in certain kinds of stripper chemistry, and redeposits, sometimes even is sprays, on the adjacent Copper.<BR>
<BR>
The film residues have become an especial problem in recent years, as the new generation of photoresists, which stick VERY well, require specially formulated types of stripper chemistry.<BR>
<BR>
I probably have told you more than you want to know, but, in case I haven't, you can call me to discuss it.<BR>
<BR>
Rudy Sedlak<BR>
RD Chemical Company 650-962-8004</FONT></HTML>
--part1_148.d89a811.29f9fe6e_boundary--
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Date: Thu, 25 Apr 2002 21:48:26 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Jim Keating <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Jim Keating <[log in to unmask]>
Subject: Re: Looking for laser drill service company.
X-To: peter blokhuis <[log in to unmask]>
X-cc: "Ronald D. Schaeffer" <[log in to unmask]>,
Gabor Kardos <[log in to unmask]>
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Peter,
Please feel free to contact Photomachining at (603) 882-9944. I'm sure that we can be of service.
Regards
Jim Keating
peter blokhuis wrote:
> Can anyone share the name of a good laser drilling
> service company?
>
> Peter Blokhuis
> 585-254-2988 x243
>
> __________________________________________________
> Do You Yahoo!?
> Yahoo! Games - play chess, backgammon, pool and more
> http://games.yahoo.com/
>
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Date: Fri, 26 Apr 2002 12:51:35 +0300
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Brian Ellis <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Brian Ellis <[log in to unmask]>
Subject: Re: Freeze Spray Trouble Shooting
X-To: Bev Christian <[log in to unmask]>
MIME-Version: 1.0
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Bev
I agree PFCs are the worst climate changers (with SF6) that exist. Some
of them are over 10,000 times worse than CO2. As a rule of thumb, 6
freezing cans which contain a PFC gas would have as much effect on
climate change as a medium car over its whole lifetime (horrific
thought). Furthermore, there will still be the contents of two of those
cans in the atmosphere 40-odd generations from now (assuming man lives
for another 40 generations!). However, I think most freezing cans
contain HFC-134a, which is bad enough but not as bad as PFCs. Some may
still contain HCFC-22 which is just as bad AND an ozone depleter, to
boot, but is not phased out under the Montreal Protocol until 2010 (some
countries may phase it out sooner).
Brian
Bev Christian wrote:
>
> Jean-Luc and other TechNetters,
> I just want to point out that I was absolutely NOT talking about CFC's
> (chlorofluorocarbons), which of course I know are banned. I am concerned
> about fully fluorinated compounds - no chlorine, no hydrogen, just
> CF3(CF2)nCF3 and branched chain equivalents. I will shut up if someone can
> tell me about cooling sprays that are not based on CF compounds - or on
> relatively friendly gases like CO2 and N2.
>
> Bev Christian
> Research in Motion
>
> -----Original Message-----
> From: [log in to unmask] [mailto:[log in to unmask]]
> Sent: April 25, 2002 10:02 AM
> To: [log in to unmask]
> Subject: Re: [TN] Freeze Spray Trouble Shooting
>
> Nice equipment but well the original post was about freezing electronic
> component, and not to cool down dry machining operations.
>
> For electronic application, the chemical used must be clean and not have
> any contaminants in it, otherwise the electronic won't like it.
> I see that Exair Vortex include a dust and oil filter but is it clean
> enough for electronic parts ?
> Another thing is that also it is small compared to a milling machine, the
> Vortex is still quite bulky to use in a lab, specially with the hose for
> the shop air.
>
> Aother thing to consider is that most freeze spray are specified with low
> electrostatic charge, because charge build-up could destroy components.
>
> As for Bev Christian's concern about CFC, there are Freeze Spray without
> CFC.
>
> Jean-Luc Lehmann
>
> SteveZeva@AOL
> .COM To: [log in to unmask]
> Sent by: cc:
> TechNet Subject: Re: [TN] Freeze Spray
> Trouble Shooting
> <[log in to unmask]
> ORG>
>
> 25.04.02
> 02:44
> Please
> respond to
> "TechNet
> E-Mail
> Forum.";
> Please
> respond to
> SteveZeva
>
> Hi David!
>
> That's why this list is so valuable! They are still around!
> Http://www.exair.com
>
> Thanks!
>
> -Steve Gregory-
>
> Bev, Years ago (about 7) there was a company selling hand held Vortex
> generators that plugged into 100 psi shop air.
> These little jewels put out -40 degree C air as long as there was 100 psi
> available. It also had to be dry nonlubed air. The company was called
> EXAir. I don't know if they are still around. David A. Douthit
> Manager
> LoCan LLC
>
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Date: Fri, 26 Apr 2002 12:57:43 +0300
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Brian Ellis <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Brian Ellis <[log in to unmask]>
Subject: Re: Microscopes
X-To: "Torres, Roberto" <[log in to unmask]>
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Bob
There are at least ten softwares available which allow you to crop what
you don't wish to see (and otherwise enhance the image). I use Corel
PhotoPaint, part of the Corel Draw! Suite, but there are more expensive
ones, such as PhotoShop which will do exactly the same job. I think
Ulead make a good one, as well and you may even find freebies or
shareware on the 'Net. Cropping and resampling also allow you to reduce
the file size if you wish to send images by e-mail, without any further
compression or other loss of image quality.
Best regards,
Brian
"Torres, Roberto" wrote:
>
> Brian;
>
> Well noted, just looks odd on the .jpg files.
>
> Bob
> -----Original Message-----
> From: Brian Ellis [mailto:[log in to unmask]]
> Sent: Wednesday, April 24, 2002 11:12 PM
> To: TechNet E-Mail Forum.; Torres, Roberto
> Subject: Re: [TN] Microscopes
>
> Roberto
>
> Does this matter? If you use a 4.3 or higher Mpixel camera, there are
> sufficient pixels left in the centre zone to record what you need to
> see, nicht war?
>
> Brian
>
> "Torres, Roberto" wrote:
> >
> > All;
> >
> > Thanks for the suggestions on Microscopes and Digital photographs.
> > The suggestion from Charles was of particular interest. Seems like
> > most use the method we use here now put the digital camera to the
> > lens of the microscope and snap away, it is just with this method
> > we tend to get a lot of telescope images, that is round and black
> > around the edges.
> >
> > Again thanks for all the input.
> >
> > Regards
> > Bob Torres
> >
> >
> ----------------------------------------------------------------------------
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> >
> ----------------------------------------------------------------------------
> -----
>
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Date: Fri, 26 Apr 2002 06:57:05 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Strickland, Mark" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Strickland, Mark" <[log in to unmask]>
Subject: Re: Insulation in the crimp contact area
X-To: "Forselles, Tom" <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Look at IPC-A-620, figure 5-45. If you want confidence, go to the
manufacturers spec for the contact and pull test a sample(s) (with the same
configuration) to be sure the tensile strength meets the manufacturers
recommendations, or alternately you can cross-section a sample to ensure the
strands are deformed and fill the voids.
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Date: Fri, 26 Apr 2002 07:11:41 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: ESSENTIAL MLB STUFF CONTINUED
Folks,
For those interested, I will be updating my article on MLB material
selections and constructions. I've asked Daan if he would post it with my
MLB ESSENTIAL STUFF.
My reason for doing this simply is because too many good folks suffer at the
hands of a lack of concurrence between themselves and their MLB suppliers.
As I've said before, I get most of my simple jobs fixing very costly
mistakes that are easily preventable using DFM/CE. In a way, I'm really
tired of this kind of crap but it's a living.
Anyway, for give me Peter, the following really prompted me to do this. Hope
it helps:
Peter,
High praise in deed from someone I respect highly.
First, I always get involved at the front end with "rookies" needing to
learn the talk so they can walk the walk. So, it all starts with clearly
defined requirements concerning what they must demand of their "qualified"
suppliers (of course, I do the qualification as well).
Master drawing notes, and attendant graphics and tables, not specifications,
are the fundamental, key instruments supporting any contract for PCB's.
Then, acceptance specifications, as IPC 600F - whatever class required, are
the next requirement clearly indicating what the board shop must look for,
as a function of master drawing requirements, and the methods used to
determine whether drawing requirements are met. X-sectioning is one very
important key for me and all I do and Section 7.0, in my notes, clearly call
out this requirement and its deliverables. All this applies with rookies
when I have to go in to fix a mess, which is most oftent the case these
days.
Concerning glass styles, you may have read one of my articles clearly
indicating the importance of this critical area. The tables I sent are not
revolutionary. They, along with whatever material matrix I need at the time,
ensure only specified materials and constructions are used to ensure
dimensional stability, bond strength, laminate integrity, and electrical
performance requirements are met - exactly as I specify. If you don't have
this article, I'll get it to you.
As I qualify my suppliers, I have a concurrent relationship established as a
function of the master drawing FIRST. If a supplier has a problem with
anything on the master drawing, we discuss it. If resolution is not
forthcoming, in my favor, that supplier is not qualified. This includes my
dictating what glass styles and resin contents are required in each
dielectric thickness as well as all the rest of the master drawin notes and
graphics. Simply, with even the most qualified shops with no discredit to
them, there must be no room for misinterpretation when high reliability/cost
MLB's are concerned. I demand concurrence, and always get it, from our first
conversations concerning a new design.
With all the foregoing, I never tell or dictate to a supplier how to manage
its processes though I, as part of the qualification process, know exactly
what is required in accordance with the master drawing. When it comes to
line widths, the supplier and myself know what is required as a function of
impedance, as one example, as well as other factors such as image, etch,
etc.. The latitude I allow concernis minor adjustments we both agree on
before starting the fab process. I allow little lattitude concerning
materials and constructions, but trace width may vary to meet a requirement
though other compromises may be made as well as long as we are both clear
and the requirement shows up in writing on the master drawing for that
particular board.
One of my most highly qualified board shops appeared to be having a
solderability issue as his x'd out boards wouldn't/couldn't meet my solder
wetting requirement. The "good" boards worked fine. Non wetting, it turns
out, was the reason for xing out the defective boards.
The master drawing notes you now attempt correcting some horrific issues on
some incredibly bad designs at the most rooky of companies. I had to do
something underneath the BGA's to prevent solder bridging from wave
soldering operations. This is a temporary fix until we go to blind vias on
this board. However, the notes clearly indicated what must be done as worked
out concurrently between the shop and myself. For the reasons you stated, I
am an anti tenter. I will use whatever path or process necessary to prevent
using tenting and there are many alternatives - usually.
The difference between core and foil lamination comes down to additional
layers/costs, and a much more favorable process for most all suppliers. It
is much easier and less costly to foil laminate as certain process
management issues are resolved as is surfact quality with fewer pits and
dents, as examples. The key is process management. If someone has never done
foil lamination, don't expect them to be capable of doing anything but core
processing.
Quality conformance test circuitry, and the coupons comprising it, are a key
element in my scheme of things. I cannot function without knowing what is in
the Z axiis where 90% of the board is hidden without x-sectional analysis in
accordance with IPC 6012 qualification requirements and 650 test methods
indicated therein. I insist on photomicrographs before and after thermal
stress. I correlate, again, all findings with master drawing reqirements
thus ensuring my requirements are met and I can take the board into
production expecting identical results.
There's so much more but so little time. I always enjoy talking with you and
learn much from your postings as well.
Let me know if I can be of more assistance,
Earl
----- Original Message -----
From: <[log in to unmask]>
To: "Earl Moon" <[log in to unmask]>
Sent: Thursday, April 25, 2002 5:34 PM
Subject: Re: [TN] PREPREG
> Hi, Earl,
>
> Very many thanks indeed for the copy of you MLB Fab spec, although it is
> for class 2 boards, where mine are class 3. I am happy to see that much of
> my own fab spec reflects what you have built up for yours, although mine
> still lacks some of the detail you have included.
>
> I know little about glass styles or their properties, so have never dared
> to mention requirements in my specs. How important is it to specify glass
> styles that may not be used (e.g. 7628) - i.e. can that not be left to the
> good sense of the fabricaor? What is te problem with7628? Is it a low
resin
> glass, or is there something else that makes it unsuitable for certain
> aplications?
>
> Sorry to bug you with questions, but I would love to have greater insight
> to some of this stuff. How different is a Cu-Core-Cu construction from a
> foil laminated construction in terms of the end nett result? I specify the
> former, but am aware that at least one fab house actually makes the boards
> with foil lamination, at least for some layers. Should I be worried about
> this? The boards seem to have performed OK.
>
> You specify the same specs for different aspects throughout your spec,
> whereas I specify the specs to be complied with at the beginning of my
> spec, unless otherwise stated elsewhere in the spec. Have you found it
> necessary to re-state the specs for each aspect, or do you do so just to
be
> absolutely certain they're adhered to? Or are there options within the
> specs you specify for those aspects, and you're stating your requirement
or
> preference?
>
> I have never stated what the trace widths and spacings should be, allowing
> the Gerber data to speak for itself. Should I be stating them in writing
as
> well?
>
> Aren't etchback and desmear "givens" these days, or should they still be
> stated in Black and White?
>
> I haven't requested test coupons or other proof of compliance apart from a
> C of C, mostly because we have no facilities here for checking them
> ourselves. Only when we have a known fab problem will I ask for these. Nor
> have I thought to specify solderability requirements, and proof thereof.
> (You see, I do have a bit to learn!)
>
> I see you use tenting - I mention this only because of the debates that
> arise on TN frequently about this with regard to contamination entrapment
> and reduced cleaning effectiveness with this method. I have considered
> tenting inadvisable for Class 3 boards, have specifically recommended to
> the design team that it not be used (not that they know to specify it one
> way or the other anyway). In your experience, tenting is obviously not a
> problem, or has particular benefits or you wouldn't be including it in
your
> notes. Can you tell me the rationale behind using or not-using tenting,
> apart from not losing solder down holes and minimising the risk of "double
> reflow" (that phrase so hated by the redoubtable Sir GW)?
>
> Large respect
>
> Peter
>
>
>
> "Earl Moon" <[log in to unmask]> 25/04/2002 08:54 PM
>
> To: DUNCAN Peter/Asst Prin Engr/ST Aero/ST Group@ST
> Domain
> cc:
> Subject: Re: [TN] PREPREG
>
>
>
>
>
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Date: Fri, 26 Apr 2002 09:30:24 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
tony steinke <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: tony steinke <[log in to unmask]>
Subject: Fw: [TN] Immersion Gold Vs Immersion Tin for 0201 landpatterns
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----- Original Message -----
From: "tony steinke" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Friday, April 26, 2002 8:21 AM
Subject: Re: [TN] Immersion Gold Vs Immersion Tin for 0201 landpatterns
> Tuan,
>
> Both processes have their advantages and disadvantages. Both processes
> provide
> a very flat uniformed finish surface. You mention a 12 month shelf life
for
> the Immersion
> Tin, I would say it would be closer to 6-8 months(also the tin does not
> perform well in
> multiple pass assembly) You should check the technet archives and it will
> give you more information
> than you can imagine.
> ----- Original Message -----
> From: "Tuan Bui" <[log in to unmask]>
> To: <[log in to unmask]>
> Sent: Thursday, April 25, 2002 10:07 AM
> Subject: [TN] Immersion Gold Vs Immersion Tin for 0201 landpatterns
>
>
> > Hello Technetters,
> >
> > I'm a new member to this board, and hope some technetters could void
their
> > opinions and advices on this issues.
> >
> > We are currently dealing with a 0201 SMT process and have some issues
with
> > a HASL 0201 landpatterns. The HASL PCB has non-uniformed finshed
surface,
> > and results in tombstones and solderballs after the reflow process. We
> then
> > switch to Immersion gold 0201 landpatterns and the issues of solderballs
> > and tombstones went away. The average cost different between HASl and
> > Immersion gold (7-10 micron)is about 6 - 8 % in cost. Another PCB vendor
> > introduced us to Immersion Tin (white tin) to reduce the additional cost
> of
> > Immersion Gold pads (about 2-5 % cost different between HASl and Tin).
We
> > have used Immersion Gold in many of our prototype products and having
> > really high yeilds, but we have not try the Immersion Tin pad finished
and
> > wonder if they behave like the Immersion Gold. The vendor also mentioned
> > that the Tin finished will oxidize and have a shelf life of 12 months.
> >
> > BTW, We are using "No Clean" process with Convection air oven.
> >
> > Any technetter has experienced in both pads surface finished ( Gold Vs
> Tin)
> > is greatly appreciates.
> >
> > Tuan Bui
> > Process Dev Eng
> > Conexant Systems Inc.
> >
>
> --------------------------------------------------------------------------
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>
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>
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Date: Fri, 26 Apr 2002 07:46:45 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Carl VanWormer <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Carl VanWormer <[log in to unmask]>
Subject: Re: Freeze Spray Trouble Shooting
X-To: Brian Ellis <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
According to the site:
http://www.emsdiasum.com/ems/clean/duster.html
The stuff I'm using claims "100% ozone-safe pressurized duster products".
Since I turn the cans upside down (or refill my quick-freeze cans for a more
convenient spraying position), am I being more gentle to the environment?
If so, we can get down to the real question of "am I wrecking my electronics
systems by using quick-freeze for troubleshooting?"
Carl Van Wormer
Cipher Systems
1815 NW 169th Place, Suite 5010
Beaverton, OR 97006
Phone (503)-617-7447 Fax (503)-617-6550
-----Original Message-----
From: Brian Ellis [mailto:[log in to unmask]]
Sent: Friday, April 26, 2002 2:52 AM
To: [log in to unmask]
Subject: Re: [TN] Freeze Spray Trouble Shooting
Bev
I agree PFCs are the worst climate changers (with SF6) that exist. Some
of them are over 10,000 times worse than CO2. As a rule of thumb, 6
freezing cans which contain a PFC gas would have as much effect on
climate change as a medium car over its whole lifetime (horrific
thought). Furthermore, there will still be the contents of two of those
cans in the atmosphere 40-odd generations from now (assuming man lives
for another 40 generations!). However, I think most freezing cans
contain HFC-134a, which is bad enough but not as bad as PFCs. Some may
still contain HCFC-22 which is just as bad AND an ozone depleter, to
boot, but is not phased out under the Montreal Protocol until 2010 (some
countries may phase it out sooner).
Brian
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Date: Fri, 26 Apr 2002 07:57:35 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
peter lee <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: peter lee <[log in to unmask]>
Subject: 0402 stencil apperture design
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Has anyone used a "D"-shape 0402 land pattern on their
design?
The pad dimensions are 18x19mils (semi-circle on the
other ends) and 16mil spacing between the 2 pads.
What would be the stencil apperture recommendation for
the above design? We've used round pads for 0402s and
15% apperture reduction before.
Rgds,
Peter
__________________________________________________
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Yahoo! Games - play chess, backgammon, pool and more
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Date: Fri, 26 Apr 2002 11:47:24 EDT
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: George Milad <[log in to unmask]>
Subject: Re: Immersion Gold Vs Immersion Tin for 0201 landpatterns
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="part1_4d.1d32fb53.29fad08c_boundary"
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Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
Tuan,
Could you clarify the "Immersion Gold" process that you are using. Is it
Immersion gold over copper or it immersion gold over nickel over copper?
Immersion Tin is a viable alternative for your application. However the
thickness required will much higher than the 7 - 8 uins that you are
presently using for gold, more like 30 - 40 uins. Tin is realtive
inexpensive and can be easily reworked if shelf life becomes an issue.
George Milad
HDI Consulting
Chairman IPC Plating Committee.
--part1_4d.1d32fb53.29fad08c_boundary
Content-Type: text/html; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>Tuan,
<BR>Could you clarify the "Immersion Gold" process that you are using. Is it Immersion gold over copper or it immersion gold over nickel over copper?
<BR>
<BR>Immersion Tin is a viable alternative for your application. However the thickness required will much higher than the 7 - 8 uins that you are presently using for gold, more like 30 - 40 uins. Tin is realtive inexpensive and can be easily reworked if shelf life becomes an issue.
<BR>
<BR>George Milad
<BR>HDI Consulting
<BR>Chairman IPC Plating Committee.
<BR></FONT></HTML>
--part1_4d.1d32fb53.29fad08c_boundary--
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Date: Fri, 26 Apr 2002 10:47:26 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Ted Stern <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Ted Stern <[log in to unmask]>
Subject: Re: test for film residue
X-To: [log in to unmask]
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="------------191063DEE8720AB4DEFFC5E5"
--------------191063DEE8720AB4DEFFC5E5
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit
Steve:
Another potential source of "residue" on copper surfaces during dry
film stripping is absorption of oils - often attributable to antifoam
and/or excess use of antifoam.
Because copper is very oleophilic, minimal contamination may be
problematic (including fingerprints) and can contribute to a variety of
post strip processing problems; incomplete final etching ("copper
spots") being one of the more common defects. The methods suggested by
Rudy would detect this problem.
As a severe (and unusual) example of oil contamination, we once
encountered a customer employing compressed air agitation to dislodge
accumulated dry film particulate in the corners of the dry film stripper
spray sump. The air was introduced when the line was idle to improve
continuous dry film particulate filtration. The customer had been
employing the process for quite some time when random copper spots began
to be observed. If the stripper was replaced, the problem disappeared;
only to reoccur in 1-2 days. To make a long story short, it was
determined (after eliminating anti-foam, checking for tin in the bath
and on panels, addressing copper oxidation, examining rinse water
quality, dry film leaching in the alkaline etch, etc.) a leaking seal in
the air compressor was contaminating the stripper sump with minute
volumes of oil, but enough to contaminate the copper surface and inhibit
alkaline etching.
Regards,
Ted
Rudy Sedlak wrote:
> In a message dated 4.25.02 12:23:23 PM Pacific Daylight Time,
> [log in to unmask] writes:
>
>
>
>> Does anyone know of a test to look for film/stripper residue after
>> copper
>> stripping.
>
> Assume you mean after stripping film from Copper?
>
> Stripper residue is a tough one, and not real likely to be an issue.
>
> Tarnish could be another issue that is very difficult to test for
> except by sight. Depending on stripper, this could be
> significant....the clue is, if the problem gets worse as the stripper
> chemistry gets older, it is quite possibly tarnish...
>
> Film residue is the most likely residue. One way to test that is a
> good test, but, can make your test board need rework is to drop on an
> immersion plating solution. Two different ones are common. Some
> people use immersion Tin to test if the surface is clean. A drop
> should plate uniformly, and adherently. Another test is to drop on
> Silver Nitrate solution...usually use the stuff that is used for
> titration in the lab. The surface should essentially immediately turn
> black, and it should be adherent.
>
> Another residue problem that can occur, and especially in old stripper
> chemistry, is immersion Tin residues....this does not relate to the
> test above. Rather, your stripper chemistry can pickup Tin from the
> oxide on the plating on outerlayers, and redeposit this on the Copper
> next to it. The potential for this problem is magnified tremendously
> if you strip in a tank, rather than exclusively in sprays, and can be
> strongly affected by the condition of the Tin plating solution. If
> your Tin electroplating solution looks very milky, this is disperse
> Tin oxide, which co-deposits with the Tin metal, then easily dissolves
> in certain kinds of stripper chemistry, and redeposits, sometimes
> even is sprays, on the adjacent Copper.
>
> The film residues have become an especial problem in recent years, as
> the new generation of photoresists, which stick VERY well, require
> specially formulated types of stripper chemistry.
>
> I probably have told you more than you want to know, but, in case I
> haven't, you can call me to discuss it.
>
> Rudy Sedlak
> RD Chemical Company 650-962-8004
--------------191063DEE8720AB4DEFFC5E5
Content-Type: text/html; charset=us-ascii
Content-Transfer-Encoding: 7bit
<!doctype html public "-//w3c//dtd html 4.0 transitional//en">
<html>
Steve:
<p>Another potential source of "residue" on copper surfaces during
dry film stripping is absorption of oils - often attributable to antifoam
and/or excess use of antifoam.
<br>Because copper is very oleophilic, minimal contamination may
be problematic (including fingerprints) and can contribute to a variety
of post strip processing problems; incomplete final etching ("copper spots")
being one of the more common defects. The methods suggested by Rudy
would detect this problem.
<p>As a severe (and unusual) example of oil contamination, we once encountered
a customer employing compressed air agitation to dislodge accumulated dry
film particulate in the corners of the dry film stripper spray sump.
The air was introduced when the line was idle to improve continuous
dry film particulate filtration. The customer had been employing
the process for quite some time when random copper spots began to be observed.
If the stripper was replaced, the problem disappeared; only to reoccur
in 1-2 days. To make a long story short, it was determined (after
eliminating anti-foam, checking for tin in the bath and on panels, addressing
copper oxidation, examining rinse water quality, dry film leaching in the
alkaline etch, etc.) a leaking seal in the air compressor was contaminating
the stripper sump with minute volumes of oil, but enough to contaminate
the copper surface and inhibit alkaline etching.
<p>Regards,
<br>Ted
<p>Rudy Sedlak wrote:
<blockquote TYPE=CITE><font face="Arial"><font size=-1>In a message dated
4.25.02 12:23:23 PM Pacific Daylight Time, [log in to unmask] writes:</font></font>
<br>
<br>
<blockquote TYPE=CITE style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px"><font face="Arial"><font size=-1>Does
anyone know of a test to look for film/stripper residue after copper</font></font>
<br><font face="Arial"><font size=-1>stripping.</font></font></blockquote>
<p><font face="Arial"><font size=-1>Assume you mean after stripping film
from Copper?</font></font>
<p><font face="Arial"><font size=-1>Stripper residue is a tough one, and
not real likely to be an issue.</font></font>
<p><font face="Arial"><font size=-1>Tarnish could be another issue that
is very difficult to test for except by sight. Depending on
stripper, this could be significant....the clue is, if the problem gets
worse as the stripper chemistry gets older, it is quite possibly tarnish...</font></font>
<p><font face="Arial"><font size=-1>Film residue is the most likely residue.
One way to test that is a good test, but, can make your test board need
rework is to drop on an immersion plating solution. Two different
ones are common. Some people use immersion Tin to test if the surface
is clean. A drop should plate uniformly, and adherently. Another
test is to drop on Silver Nitrate solution...usually use the stuff that
is used for titration in the lab. The surface should essentially
immediately turn black, and it should be adherent.</font></font>
<p><font face="Arial"><font size=-1>Another residue problem that can occur,
and especially in old stripper chemistry, is immersion Tin residues....this
does not relate to the test above. Rather, your stripper chemistry
can pickup Tin from the oxide on the plating on outerlayers, and redeposit
this on the Copper next to it. The potential for this problem
is magnified tremendously if you strip in a tank, rather than exclusively
in sprays, and can be strongly affected by the condition of the Tin plating
solution. If your Tin electroplating solution looks very milky, this
is disperse Tin oxide, which co-deposits with the Tin metal, then easily
dissolves in certain kinds of stripper chemistry, and redeposits,
sometimes even is sprays, on the adjacent Copper.</font></font>
<p><font face="Arial"><font size=-1>The film residues have become an especial
problem in recent years, as the new generation of photoresists, which stick
VERY well, require specially formulated types of stripper chemistry.</font></font>
<p><font face="Arial"><font size=-1>I probably have told you more than
you want to know, but, in case I haven't, you can call me to discuss it.</font></font>
<p><font face="Arial"><font size=-1>Rudy Sedlak</font></font>
<br><font face="Arial"><font size=-1>RD Chemical Company 650-962-8004</font></font></blockquote>
</html>
--------------191063DEE8720AB4DEFFC5E5--
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Date: Fri, 26 Apr 2002 08:58:11 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Mcmaster, Michael" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Mcmaster, Michael" <[log in to unmask]>
Subject: Re: Via Plug
X-To: John Foster <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain
John
The DuPont CB-100 will increase the amount of heat that can be conducted
through the barrel. My experience with it that most people overestimate
what it can do. I've done calculations that show for a 0.020" drilled hole
with 0.001" copper barrel, adding CB-100 only increases the amount of heat
by less than 5%. The reason is the CB-100 has a thermal conductivity of 5.23
W/mK vs 395 W/mK for copper. Even though CB-100 makes up the majority of
the cross sectional area, it only adds a little to the "thermal" cross
section.
I always recommend that potential users of this technology run the numbers
themselves and balance the potential cost increase with the improved
performance.
> ----------
> From: John Foster[SMTP:[log in to unmask]]
> Reply To: TechNet E-Mail Forum.;John Foster
> Sent: Tuesday, April 23, 2002 12:06 PM
> To: [log in to unmask]
> Subject: [TN] Via Plug
>
> Hello, I am new to this listserver. I must say that it is very
> informative. I wish I had known of it long ago.
>
> I have a question about via plugging. Right now
> our board vendor is doing our via plugs with
> I guess with a standard epoxy. We are trying
> to find a solution that would give us a much
> better thermal performance.
>
> We are looking at silver epoxy and this
> material from Dupont. Does anyone know of
> some material that would give us a really good
> thermal performance. We are in a commercial
> environment. So the material does not have to
> meet industrial specs.
>
> Any input on this matter would be greatly '
> appreciated.
>
> Thank You
>
> John Foster
>
> --------------------------------------------------------------------------
> -------
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Date: Fri, 26 Apr 2002 08:58:34 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Mcmaster, Michael" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Mcmaster, Michael" <[log in to unmask]>
Subject: Re: Removal of Cured Nomenclature Ink
X-To: "Furrow, Robert Gordon (Bob)" <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain
Not chemistry, but light, specifically a laser, would be the best approach
to doing this, especially if the unwanted nomen ink is over copper.
> ----------
> From: Furrow, Robert Gordon (Bob)[SMTP:[log in to unmask]]
> Reply To: TechNet E-Mail Forum.;Furrow, Robert Gordon (Bob)
> Sent: Monday, April 22, 2002 12:44 PM
> To: [log in to unmask]
> Subject: [TN] Removal of Cured Nomenclature Ink
>
> Hi TechNet,
>
> I have been asked what chemical(s) would be required to remove cured
> nomenclature ink (also known as silkscreen) from a bare board without
> damaging the board itself. I am assuming it is an epoxy ink, but I do not
> know the exact formulation. Any input is appreciated. I should know the
> exact formulation of the applied nomenclature ink tomorrow, but thought
> that
> maybe there is a generic answer.
>
> Thanks,
> Robert Furrow
> Printed Wiring Board Engineer
> Supply Chain Networks
> Lucent Technologies
> 978-960-3224 [log in to unmask]
>
> --------------------------------------------------------------------------
> -------
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> --------------------------------------------------------------------------
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>
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Date: Fri, 26 Apr 2002 09:27:30 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
David Douthit <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: David Douthit <[log in to unmask]>
Subject: Re: Freeze Spray Trouble Shooting
X-To: Carl VanWormer <[log in to unmask]>
MIME-Version: 1.0
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Carl,
I quit using "freeze cans" for troubleshooting because they did not work very well particularly on
conformally coating products.
When a "thermal failure" occurs it happens at a particular temperature or during a specific temperature
change. Because polymers
require much more time to change temperatures I discovered that freeze mist would "shoot by" or run
past the thermal failure point.
It would then require a long time to stabilize the circuit and try again. I used the EXair because I
could control
the temperature change by varying the distance from the nozzle to the circuit, had an endless supply of
"cold", air and very little if any
frost/moisture on the circuit. I discovered that 90% of the thermal failures could be "found" by
recreating the thermal conditions at time of failure and gradually "bumping" the temperature around
this point. I seldom had to go more than + 20 degrees C from the estimated thermal fail point to
recreate the failure.
Conformal coatings will "hold" joints in place until a certain thermal point is reached. Usually this
is a "window" because as the coating dimensions change
the joint will "make and break" contact.
Hope this helps!
David A. Douthit
Manager
LoCan LLC
Carl VanWormer wrote:
> According to the site:
> http://www.emsdiasum.com/ems/clean/duster.html
> The stuff I'm using claims "100% ozone-safe pressurized duster products".
>
> Since I turn the cans upside down (or refill my quick-freeze cans for a more
> convenient spraying position), am I being more gentle to the environment?
> If so, we can get down to the real question of "am I wrecking my electronics
> systems by using quick-freeze for troubleshooting?"
>
> Carl Van Wormer
> Cipher Systems
> 1815 NW 169th Place, Suite 5010
> Beaverton, OR 97006
> Phone (503)-617-7447 Fax (503)-617-6550
>
> -----Original Message-----
> From: Brian Ellis [mailto:[log in to unmask]]
> Sent: Friday, April 26, 2002 2:52 AM
> To: [log in to unmask]
> Subject: Re: [TN] Freeze Spray Trouble Shooting
>
> Bev
>
> I agree PFCs are the worst climate changers (with SF6) that exist. Some
> of them are over 10,000 times worse than CO2. As a rule of thumb, 6
> freezing cans which contain a PFC gas would have as much effect on
> climate change as a medium car over its whole lifetime (horrific
> thought). Furthermore, there will still be the contents of two of those
> cans in the atmosphere 40-odd generations from now (assuming man lives
> for another 40 generations!). However, I think most freezing cans
> contain HFC-134a, which is bad enough but not as bad as PFCs. Some may
> still contain HCFC-22 which is just as bad AND an ozone depleter, to
> boot, but is not phased out under the Montreal Protocol until 2010 (some
> countries may phase it out sooner).
>
> Brian
>
> ---------------------------------------------------------------------------------
> Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
> To unsubscribe, send a message to [log in to unmask] with following text in
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<html>
Carl,
<p>I quit using "freeze cans" for troubleshooting because they did not
work very well particularly on conformally coating products.
<p>When a "thermal failure" occurs it happens at a particular temperature
or during a specific temperature change. Because polymers
<br>require much more time to change temperatures I discovered that freeze
mist would "shoot by" or run past the thermal failure point.
<br>It would then require a long time to stabilize the circuit and try
again. I used the EXair because I could control
<br>the temperature change by varying the distance from the nozzle to the
circuit, had an endless supply of "cold", air and very little if any
<br>frost/moisture on the circuit. I discovered that 90% of the thermal
failures could be "found" by recreating the thermal conditions at time
of failure and gradually "bumping" the temperature around this point. I
seldom had to go more than <u>+</u> 20 degrees C from the estimated thermal
fail point to recreate the failure.
<p>Conformal coatings will "hold" joints in place until a certain thermal
point is reached. Usually this is a "window" because as the coating dimensions
change
<br>the joint will "make and break" contact.
<p>Hope this helps!
<p>David A. Douthit
<br>Manager
<br>LoCan LLC
<br>
<p>Carl VanWormer wrote:
<blockquote TYPE=CITE>According to the site:
<br><a href="http://www.emsdiasum.com/ems/clean/duster.html">http://www.emsdiasum.com/ems/clean/duster.html</a>
<br>The stuff I'm using claims "100% ozone-safe pressurized duster products".
<p>Since I turn the cans upside down (or refill my quick-freeze cans for
a more
<br>convenient spraying position), am I being more gentle to the environment?
<br>If so, we can get down to the real question of "am I wrecking my electronics
<br>systems by using quick-freeze for troubleshooting?"
<p>Carl Van Wormer
<br>Cipher Systems
<br>1815 NW 169th Place, Suite 5010
<br>Beaverton, OR 97006
<br>Phone (503)-617-7447 Fax (503)-617-6550
<p>-----Original Message-----
<br>From: Brian Ellis [<a href="mailto:[log in to unmask]">mailto:[log in to unmask]</a>]
<br>Sent: Friday, April 26, 2002 2:52 AM
<br>To: [log in to unmask]
<br>Subject: Re: [TN] Freeze Spray Trouble Shooting
<p>Bev
<p>I agree PFCs are the worst climate changers (with SF6) that exist. Some
<br>of them are over 10,000 times worse than CO2. As a rule of thumb, 6
<br>freezing cans which contain a PFC gas would have as much effect on
<br>climate change as a medium car over its whole lifetime (horrific
<br>thought). Furthermore, there will still be the contents of two of those
<br>cans in the atmosphere 40-odd generations from now (assuming man lives
<br>for another 40 generations!). However, I think most freezing cans
<br>contain HFC-134a, which is bad enough but not as bad as PFCs. Some
may
<br>still contain HCFC-22 which is just as bad AND an ozone depleter, to
<br>boot, but is not phased out under the Montreal Protocol until 2010
(some
<br>countries may phase it out sooner).
<p>Brian
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Date: Fri, 26 Apr 2002 12:21:33 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Bev Christian <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Bev Christian <[log in to unmask]>
Subject: Re: Freeze Spray Trouble Shooting
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Carl,
PFCs and HFC have no chlorine so they are not ozone depleters, but that
doesn't mean they are not global warmers. I do not have the time to look at
your particular material right now. Sorry.
regards,
Bev Christian
Research in Motion
-----Original Message-----
From: Carl VanWormer [mailto:[log in to unmask]]
Sent: April 26, 2002 10:47 AM
To: [log in to unmask]
Subject: Re: [TN] Freeze Spray Trouble Shooting
According to the site:
http://www.emsdiasum.com/ems/clean/duster.html
The stuff I'm using claims "100% ozone-safe pressurized duster products".
Since I turn the cans upside down (or refill my quick-freeze cans for a more
convenient spraying position), am I being more gentle to the environment?
If so, we can get down to the real question of "am I wrecking my electronics
systems by using quick-freeze for troubleshooting?"
Carl Van Wormer
Cipher Systems
1815 NW 169th Place, Suite 5010
Beaverton, OR 97006
Phone (503)-617-7447 Fax (503)-617-6550
-----Original Message-----
From: Brian Ellis [mailto:[log in to unmask]]
Sent: Friday, April 26, 2002 2:52 AM
To: [log in to unmask]
Subject: Re: [TN] Freeze Spray Trouble Shooting
Bev
I agree PFCs are the worst climate changers (with SF6) that exist. Some
of them are over 10,000 times worse than CO2. As a rule of thumb, 6
freezing cans which contain a PFC gas would have as much effect on
climate change as a medium car over its whole lifetime (horrific
thought). Furthermore, there will still be the contents of two of those
cans in the atmosphere 40-odd generations from now (assuming man lives
for another 40 generations!). However, I think most freezing cans
contain HFC-134a, which is bad enough but not as bad as PFCs. Some may
still contain HCFC-22 which is just as bad AND an ozone depleter, to
boot, but is not phased out under the Montreal Protocol until 2010 (some
countries may phase it out sooner).
Brian
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Date: Fri, 26 Apr 2002 11:36:06 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Houston, Terri" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Houston, Terri" <[log in to unmask]>
Subject: Microvias and rigid-flex in one board shop?
Hi folks,
I'm looking for a board shop with actual experience in building a 14+ layer,
rigid-flex board that has microvias in the rigid sections.
It seems the combination of these two features is hard to find at one
supplier, even though I'm only looking for a small quantity of prototypes.
Any suggestions would be greatly appreciated--even self-marketing would be
accepted (off TechNet, please).
Thanks in advance,
Terri
---------------------------------------------------------------------------------
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=========================================================================
Date: Fri, 26 Apr 2002 18:05:27 +0100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Hinners Hans M Civ WRALC/LUGE <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Hinners Hans M Civ WRALC/LUGE <[log in to unmask]>
Subject: Re: test for film residue
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Hi Steve,
You might try looking at the panels under UV light or a water break test.
Hans
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Hans M. Hinners
Electronics Engineer
Warner Robins - Air Logistics Center (WR-ALC/LUGE)
226 Cochran Street
Robins AFB GA 31098-1622
mailto:[log in to unmask] <mailto:[log in to unmask]>
Com: (478) 926 - 5224
Fax: (478) 926 - 4911
DSN Prefix: 468
-----Original Message-----
From: Ted Stern [mailto:[log in to unmask]]
Sent: Friday, April 26, 2002 11:47 AM
To: [log in to unmask]
Subject: Re: [TN] test for film residue
Steve:
Another potential source of "residue" on copper surfaces during dry film
stripping is absorption of oils - often attributable to antifoam and/or
excess use of antifoam.
Because copper is very oleophilic, minimal contamination may be problematic
(including fingerprints) and can contribute to a variety of post strip
processing problems; incomplete final etching ("copper spots") being one of
the more common defects. The methods suggested by Rudy would detect this
problem.
As a severe (and unusual) example of oil contamination, we once encountered
a customer employing compressed air agitation to dislodge accumulated dry
film particulate in the corners of the dry film stripper spray sump. The
air was introduced when the line was idle to improve continuous dry film
particulate filtration. The customer had been employing the process for
quite some time when random copper spots began to be observed. If the
stripper was replaced, the problem disappeared; only to reoccur in 1-2 days.
To make a long story short, it was determined (after eliminating anti-foam,
checking for tin in the bath and on panels, addressing copper oxidation,
examining rinse water quality, dry film leaching in the alkaline etch, etc.)
a leaking seal in the air compressor was contaminating the stripper sump
with minute volumes of oil, but enough to contaminate the copper surface and
inhibit alkaline etching.
Regards,
Ted
Rudy Sedlak wrote:
In a message dated 4.25.02 12:23:23 PM Pacific Daylight Time, [log in to unmask]
writes:
Does anyone know of a test to look for film/stripper residue after copper
stripping.
Assume you mean after stripping film from Copper?
Stripper residue is a tough one, and not real likely to be an issue.
Tarnish could be another issue that is very difficult to test for except by
sight. Depending on stripper, this could be significant....the clue is, if
the problem gets worse as the stripper chemistry gets older, it is quite
possibly tarnish...
Film residue is the most likely residue. One way to test that is a good
test, but, can make your test board need rework is to drop on an immersion
plating solution. Two different ones are common. Some people use immersion
Tin to test if the surface is clean. A drop should plate uniformly, and
adherently. Another test is to drop on Silver Nitrate solution...usually
use the stuff that is used for titration in the lab. The surface should
essentially immediately turn black, and it should be adherent.
Another residue problem that can occur, and especially in old stripper
chemistry, is immersion Tin residues....this does not relate to the test
above. Rather, your stripper chemistry can pickup Tin from the oxide on the
plating on outerlayers, and redeposit this on the Copper next to it. The
potential for this problem is magnified tremendously if you strip in a tank,
rather than exclusively in sprays, and can be strongly affected by the
condition of the Tin plating solution. If your Tin electroplating solution
looks very milky, this is disperse Tin oxide, which co-deposits with the Tin
metal, then easily dissolves in certain kinds of stripper chemistry, and
redeposits, sometimes even is sprays, on the adjacent Copper.
The film residues have become an especial problem in recent years, as the
new generation of photoresists, which stick VERY well, require specially
formulated types of stripper chemistry.
I probably have told you more than you want to know, but, in case I haven't,
you can call me to discuss it.
Rudy Sedlak
RD Chemical Company 650-962-8004
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<BODY>
<DIV><SPAN class=599240317-26042002><FONT color=#0000ff>Hi
Steve,</FONT></SPAN></DIV>
<DIV><SPAN class=599240317-26042002><FONT
color=#0000ff></FONT></SPAN> </DIV>
<DIV><SPAN class=599240317-26042002><FONT color=#0000ff>You might try looking at
the panels under UV light or a water break test.</FONT></SPAN></DIV>
<DIV><SPAN class=599240317-26042002><FONT
color=#0000ff></FONT></SPAN> </DIV>
<DIV><SPAN class=599240317-26042002><FONT color=#0000ff>Hans</FONT></SPAN></DIV>
<DIV><SPAN class=599240317-26042002><FONT color=#0000ff></FONT><BR><FONT
face=Verdana>~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~</FONT> <BR><FONT
face=Verdana>Hans M. Hinners</FONT> <BR><FONT face=Verdana>Electronics
Engineer</FONT> <BR><FONT face=Verdana>Warner Robins - Air Logistics Center
(WR-ALC/LUGE)</FONT> <BR><FONT face=Verdana>226 Cochran Street</FONT> <BR><FONT
face=Verdana>Robins AFB GA 31098-1622</FONT> </DIV>
<DIV>
<P><FONT face=Verdana><A
href="mailto:[log in to unmask]">mailto:[log in to unmask]</A></FONT>
</P>
<P><FONT face=Verdana>Com: (478) 926 - 5224</FONT> <BR><FONT
face=Verdana>Fax: (478) 926 - 4911</FONT> <BR><FONT face=Arial
size=2>DSN Prefix: 468</FONT> </P></SPAN></DIV>
<BLOCKQUOTE dir=ltr style="MARGIN-RIGHT: 0px">
<DIV class=OutlookMessageHeader dir=ltr align=left><FONT face=Tahoma
size=2>-----Original Message-----<BR><B>From:</B> Ted Stern
[mailto:[log in to unmask]]<BR><B>Sent:</B> Friday, April 26, 2002 11:47
AM<BR><B>To:</B> [log in to unmask]<BR><B>Subject:</B> Re: [TN] test for film
residue<BR><BR></FONT></DIV>Steve:
<P>Another potential source of "residue" on copper surfaces during dry
film stripping is absorption of oils - often attributable to antifoam and/or
excess use of antifoam. <BR>Because copper is very oleophilic, minimal
contamination may be problematic (including fingerprints) and can contribute
to a variety of post strip processing problems; incomplete final etching
("copper spots") being one of the more common defects. The methods
suggested by Rudy would detect this problem.
<P>As a severe (and unusual) example of oil contamination, we once encountered
a customer employing compressed air agitation to dislodge accumulated dry film
particulate in the corners of the dry film stripper spray sump. The air
was introduced when the line was idle to improve continuous dry film
particulate filtration. The customer had been employing the
process for quite some time when random copper spots began to be
observed. If the stripper was replaced, the problem disappeared; only to
reoccur in 1-2 days. To make a long story short, it was determined
(after eliminating anti-foam, checking for tin in the bath and on panels,
addressing copper oxidation, examining rinse water quality, dry film leaching
in the alkaline etch, etc.) a leaking seal in the air compressor was
contaminating the stripper sump with minute volumes of oil, but enough to
contaminate the copper surface and inhibit alkaline etching.
<P>Regards, <BR>Ted
<P>Rudy Sedlak wrote:
<BLOCKQUOTE TYPE="CITE"><FONT face=Arial><FONT size=-1>In a message dated
4.25.02 12:23:23 PM Pacific Daylight Time, [log in to unmask]
writes:</FONT></FONT> <BR> <BR>
<BLOCKQUOTE
style="PADDING-LEFT: 5px; MARGIN-LEFT: 5px; BORDER-LEFT: #0000ff 2px solid; MARGIN-RIGHT: 0px"
TYPE="CITE"><FONT face=Arial><FONT size=-1>Does anyone know of a test to
look for film/stripper residue after copper</FONT></FONT> <BR><FONT
face=Arial><FONT size=-1>stripping.</FONT></FONT></BLOCKQUOTE>
<P><FONT face=Arial><FONT size=-1>Assume you mean after stripping film from
Copper?</FONT></FONT>
<P><FONT face=Arial><FONT size=-1>Stripper residue is a tough one, and not
real likely to be an issue.</FONT></FONT>
<P><FONT face=Arial><FONT size=-1>Tarnish could be another issue that is
very difficult to test for except by sight. Depending on
stripper, this could be significant....the clue is, if the problem gets
worse as the stripper chemistry gets older, it is quite possibly
tarnish...</FONT></FONT>
<P><FONT face=Arial><FONT size=-1>Film residue is the most likely
residue. One way to test that is a good test, but, can make your test
board need rework is to drop on an immersion plating solution. Two
different ones are common. Some people use immersion Tin to test if
the surface is clean. A drop should plate uniformly, and
adherently. Another test is to drop on Silver Nitrate
solution...usually use the stuff that is used for titration in the
lab. The surface should essentially immediately turn black, and it
should be adherent.</FONT></FONT>
<P><FONT face=Arial><FONT size=-1>Another residue problem that can occur,
and especially in old stripper chemistry, is immersion Tin residues....this
does not relate to the test above. Rather, your stripper chemistry can
pickup Tin from the oxide on the plating on outerlayers, and redeposit this
on the Copper next to it. The potential for this problem is
magnified tremendously if you strip in a tank, rather than exclusively in
sprays, and can be strongly affected by the condition of the Tin plating
solution. If your Tin electroplating solution looks very milky, this
is disperse Tin oxide, which co-deposits with the Tin metal, then easily
dissolves in certain kinds of stripper chemistry, and redeposits,
sometimes even is sprays, on the adjacent Copper.</FONT></FONT>
<P><FONT face=Arial><FONT size=-1>The film residues have become an especial
problem in recent years, as the new generation of photoresists, which stick
VERY well, require specially formulated types of stripper
chemistry.</FONT></FONT>
<P><FONT face=Arial><FONT size=-1>I probably have told you more than you
want to know, but, in case I haven't, you can call me to discuss
it.</FONT></FONT>
<P><FONT face=Arial><FONT size=-1>Rudy Sedlak</FONT></FONT> <BR><FONT
face=Arial><FONT size=-1>RD Chemical Company
650-962-8004</FONT></FONT></P></BLOCKQUOTE></BLOCKQUOTE></BODY></HTML>
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=========================================================================
Date: Fri, 26 Apr 2002 13:25:40 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Joseph Spicuzza <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Joseph Spicuzza <[log in to unmask]>
Subject: Re: Microvias and rigid-flex in one board shop?
X-To: "Houston, Terri" <[log in to unmask]>
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
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Our shop may be able to fabricate this, but we need more info.
Contact me and I'll forward you to the fab team.
Joseph Spicuzza
Quality Assurance Manager
Advanced Interconnect Products Division
Compunetics, Inc.
PH: 412 858-6166
FX: 412 373-8060
[log in to unmask]
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Houston, Terri
Sent: Friday, April 26, 2002 12:36 PM
To: [log in to unmask]
Subject: [TN] Microvias and rigid-flex in one board shop?
Hi folks,
I'm looking for a board shop with actual experience in building a 14+ layer,
rigid-flex board that has microvias in the rigid sections.
It seems the combination of these two features is hard to find at one
supplier, even though I'm only looking for a small quantity of prototypes.
Any suggestions would be greatly appreciated--even self-marketing would be
accepted (off TechNet, please).
Thanks in advance,
Terri
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Date: Fri, 26 Apr 2002 10:26:56 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
peter lee <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: peter lee <[log in to unmask]>
Subject: Senju sparkle noclean paste
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Does anyone have experience using this paste. I was
told that it is unstable unless running in N2
environment.
Rgds,
Peter
__________________________________________________
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Date: Fri, 26 Apr 2002 10:54:22 -0700
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Ahne Oosterhof <[log in to unmask]>
Subject: Re: 0402 stencil apperture design
X-To: peter lee <[log in to unmask]>
X-cc: Jim <[log in to unmask]>
In-Reply-To: <[log in to unmask]>
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Hi Peter,
At Plexus they have published a rather extensive report on the causes of
tombstoning. It included some remarks on the incidence of solder balls. Both
problem areas are partially caused by pad design on the board and aperture
design in stencils. (Some say the most significant factors for tombstoning
are pick-and-place accuracy and oven temperature profile.)
To minimize tombstoning the report indicates that pad design has a minimal
impact when using 0402-s, but for 0201-s you want to stay close to the
'normal' size for pad design.
To minimize solder balls it is recommended to change stencil apertures to
home plates. My personal preference (and that of some of our customers) is
to change the aperture to an oval, which has the effect of reducing excess
solder in all four corners of the pads. Sometimes in addition the overall
size is reduced by 1 or 2 mil.
An additional advantage is that the OVAL is a Gerber shape improving data
compactness, data sharing and interpretation reliability and it means that
for a single component there are no 'left' and 'right' or 'top' and 'bottom'
apertures (or D-codes).
Have fun,
Ahne.
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of peter lee
Sent: Friday, April 26, 2002 07:58
To: [log in to unmask]
Subject: [TN] 0402 stencil apperture design
Has anyone used a "D"-shape 0402 land pattern on their
design?
The pad dimensions are 18x19mils (semi-circle on the
other ends) and 16mil spacing between the 2 pads.
What would be the stencil apperture recommendation for
the above design? We've used round pads for 0402s and
15% apperture reduction before.
Rgds,
Peter
__________________________________________________
Do You Yahoo!?
Yahoo! Games - play chess, backgammon, pool and more
http://games.yahoo.com/
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Date: Fri, 26 Apr 2002 11:05:08 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Tuan Bui <[log in to unmask]>
Subject: Re: Immersion Gold Vs Immersion Tin for 0201 landpatterns
X-To: [log in to unmask]
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
Hi George,
The Immersion Gold process that the PCB vendor stated that the Immersion
gold (7-10 micron) over nickel over copper. The Immersion Tin process, as
you have mentioned, is about 44 micron. It is good to hear that the
immersion tin process can be easily/inexpensive reworked when its shelf
live expires.
BTW, thanks for your input.
Tuan Bui
Proc Dev Eng
Conexant Systems Inc.
George Milad
<[log in to unmask]> To: [log in to unmask]
Sent by: TechNet cc:
<[log in to unmask]> Subject: Re: [TN] Immersion Gold Vs Immersion Tin for 0201 landpatterns
04/26/2002 08:47
AM
Please respond to
"TechNet E-Mail
Forum."; Please
respond to Gmilad
Tuan,
Could you clarify the "Immersion Gold" process that you are using. Is it
Immersion gold over copper or it immersion gold over nickel over copper?
Immersion Tin is a viable alternative for your application. However the
thickness required will much higher than the 7 - 8 uins that you are
presently using for gold, more like 30 - 40 uins. Tin is realtive
inexpensive and can be easily reworked if shelf life becomes an issue.
George Milad
HDI Consulting
Chairman IPC Plating Committee.
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Date: Fri, 26 Apr 2002 11:41:58 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Phil Bavaro <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Phil Bavaro <[log in to unmask]>
Subject: Re: Senju sparkle noclean paste
X-To: peter lee <[log in to unmask]>
In-Reply-To: <[log in to unmask]>
Mime-Version: 1.0
Content-Type: text/plain; charset="us-ascii"; format=flowed
We have about ten years of experience using Senju solderpaste without any
issues.
You have not stated what specific paste part number you are referring to.
And I am not sure I know what you mean by solderpaste being described as
unstable.
Phil
At 10:26 AM 4/26/2002 -0700, peter lee wrote:
>Does anyone have experience using this paste. I was
>told that it is unstable unless running in N2
>environment.
>
>Rgds,
>Peter
>
>__________________________________________________
>Do You Yahoo!?
>Yahoo! Games - play chess, backgammon, pool and more
>http://games.yahoo.com/
>
>---------------------------------------------------------------------------------
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>the BODY (NOT the subject field): SIGNOFF Technet
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>Please visit IPC web site http://www.ipc.org/html/forum.htm for additional
>information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700
>ext.5315
>---------------------------------------------------------------------------------
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Date: Fri, 26 Apr 2002 15:10:41 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Steve Kelly <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Steve Kelly <[log in to unmask]>
Subject: Re: test for film residue
X-To: Ted Stern <[log in to unmask]>
In-Reply-To: <[log in to unmask]>
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We etch in Ferric chloride so do not use any tin chemistry - however Rudy's
comments are interesting - we do have an immersion tin line so we can easily
do this test. Thanks Steve Kelly
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Ted Stern
Sent: Friday, April 26, 2002 11:47 AM
To: [log in to unmask]
Subject: Re: [TN] test for film residue
Steve:
Another potential source of "residue" on copper surfaces during dry film
stripping is absorption of oils - often attributable to antifoam and/or
excess use of antifoam.
Because copper is very oleophilic, minimal contamination may be
problematic (including fingerprints) and can contribute to a variety of post
strip processing problems; incomplete final etching ("copper spots") being
one of the more common defects. The methods suggested by Rudy would detect
this problem.
As a severe (and unusual) example of oil contamination, we once
encountered a customer employing compressed air agitation to dislodge
accumulated dry film particulate in the corners of the dry film stripper
spray sump. The air was introduced when the line was idle to improve
continuous dry film particulate filtration. The customer had been
employing the process for quite some time when random copper spots began to
be observed. If the stripper was replaced, the problem disappeared; only to
reoccur in 1-2 days. To make a long story short, it was determined (after
eliminating anti-foam, checking for tin in the bath and on panels,
addressing copper oxidation, examining rinse water quality, dry film
leaching in the alkaline etch, etc.) a leaking seal in the air compressor
was contaminating the stripper sump with minute volumes of oil, but enough
to contaminate the copper surface and inhibit alkaline etching.
Regards,
Ted
Rudy Sedlak wrote:
In a message dated 4.25.02 12:23:23 PM Pacific Daylight Time,
[log in to unmask] writes:
Does anyone know of a test to look for film/stripper residue after
copper
stripping.
Assume you mean after stripping film from Copper?
Stripper residue is a tough one, and not real likely to be an issue.
Tarnish could be another issue that is very difficult to test for except
by sight. Depending on stripper, this could be significant....the clue is,
if the problem gets worse as the stripper chemistry gets older, it is quite
possibly tarnish...
Film residue is the most likely residue. One way to test that is a good
test, but, can make your test board need rework is to drop on an immersion
plating solution. Two different ones are common. Some people use immersion
Tin to test if the surface is clean. A drop should plate uniformly, and
adherently. Another test is to drop on Silver Nitrate solution...usually
use the stuff that is used for titration in the lab. The surface should
essentially immediately turn black, and it should be adherent.
Another residue problem that can occur, and especially in old stripper
chemistry, is immersion Tin residues....this does not relate to the test
above. Rather, your stripper chemistry can pickup Tin from the oxide on the
plating on outerlayers, and redeposit this on the Copper next to it. The
potential for this problem is magnified tremendously if you strip in a tank,
rather than exclusively in sprays, and can be strongly affected by the
condition of the Tin plating solution. If your Tin electroplating solution
looks very milky, this is disperse Tin oxide, which co-deposits with the Tin
metal, then easily dissolves in certain kinds of stripper chemistry, and
redeposits, sometimes even is sprays, on the adjacent Copper.
The film residues have become an especial problem in recent years, as
the new generation of photoresists, which stick VERY well, require specially
formulated types of stripper chemistry.
I probably have told you more than you want to know, but, in case I
haven't, you can call me to discuss it.
Rudy Sedlak
RD Chemical Company 650-962-8004
------=_NextPart_000_08F5_01C1ED34.88AD36E0
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charset="us-ascii"
Content-Transfer-Encoding: quoted-printable
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<BODY>
<DIV><FONT color=3D#0000ff face=3DArial size=3D2><SPAN =
class=3D087020919-26042002>We=20
etch in Ferric chloride so do not use any tin chemistry - however Rudy's =
comments are interesting - we do have an immersion tin line so we can =
easily do=20
this test. Thanks Steve Kelly</SPAN></FONT></DIV>
<BLOCKQUOTE style=3D"MARGIN-RIGHT: 0px">
<DIV align=3Dleft class=3DOutlookMessageHeader dir=3Dltr><FONT =
face=3DTahoma=20
size=3D2>-----Original Message-----<BR><B>From:</B> TechNet=20
[mailto:[log in to unmask]]<B>On Behalf Of </B>Ted Stern<BR><B>Sent:</B> =
Friday,=20
April 26, 2002 11:47 AM<BR><B>To:</B> =
[log in to unmask]<BR><B>Subject:</B> Re:=20
[TN] test for film residue<BR><BR></DIV></FONT>Steve:=20
<P>Another potential source of "residue" on copper surfaces =
during dry=20
film stripping is absorption of oils - often attributable to antifoam =
and/or=20
excess use of antifoam. <BR>Because copper is very oleophilic, =
minimal=20
contamination may be problematic (including fingerprints) and can =
contribute=20
to a variety of post strip processing problems; incomplete final =
etching=20
("copper spots") being one of the more common defects. The =
methods=20
suggested by Rudy would detect this problem.=20
<P>As a severe (and unusual) example of oil contamination, we once =
encountered=20
a customer employing compressed air agitation to dislodge accumulated =
dry film=20
particulate in the corners of the dry film stripper spray sump. =
The air=20
was introduced when the line was idle to improve continuous dry =
film=20
particulate filtration. The customer had been employing =
the=20
process for quite some time when random copper spots began to be=20
observed. If the stripper was replaced, the problem disappeared; =
only to=20
reoccur in 1-2 days. To make a long story short, it was =
determined=20
(after eliminating anti-foam, checking for tin in the bath and on =
panels,=20
addressing copper oxidation, examining rinse water quality, dry film =
leaching=20
in the alkaline etch, etc.) a leaking seal in the air compressor was=20
contaminating the stripper sump with minute volumes of oil, but enough =
to=20
contaminate the copper surface and inhibit alkaline etching.=20
<P>Regards, <BR>Ted=20
<P>Rudy Sedlak wrote:=20
<BLOCKQUOTE TYPE=3D"CITE"><FONT face=3DArial><FONT size=3D-1>In a =
message dated=20
4.25.02 12:23:23 PM Pacific Daylight Time, [log in to unmask]
writes:</FONT></FONT> <BR> <BR> =20
<BLOCKQUOTE=20
style=3D"BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; =
MARGIN-RIGHT: 0px; PADDING-LEFT: 5px"=20
TYPE=3D"CITE"><FONT face=3DArial><FONT size=3D-1>Does anyone know of =
a test to=20
look for film/stripper residue after copper</FONT></FONT> =
<BR><FONT=20
face=3DArial><FONT size=3D-1>stripping.</FONT></FONT></BLOCKQUOTE>
<P><FONT face=3DArial><FONT size=3D-1>Assume you mean after =
stripping film from=20
Copper?</FONT></FONT>=20
<P><FONT face=3DArial><FONT size=3D-1>Stripper residue is a tough =
one, and not=20
real likely to be an issue.</FONT></FONT>=20
<P><FONT face=3DArial><FONT size=3D-1>Tarnish could be another issue =
that is=20
very difficult to test for except by sight. Depending on =
stripper, this could be significant....the clue is, if the problem =
gets=20
worse as the stripper chemistry gets older, it is quite possibly=20
tarnish...</FONT></FONT>=20
<P><FONT face=3DArial><FONT size=3D-1>Film residue is the most =
likely=20
residue. One way to test that is a good test, but, can make =
your test=20
board need rework is to drop on an immersion plating solution. =
Two=20
different ones are common. Some people use immersion Tin to =
test if=20
the surface is clean. A drop should plate uniformly, and=20
adherently. Another test is to drop on Silver Nitrate=20
solution...usually use the stuff that is used for titration in the=20
lab. The surface should essentially immediately turn black, =
and it=20
should be adherent.</FONT></FONT>=20
<P><FONT face=3DArial><FONT size=3D-1>Another residue problem that =
can occur,=20
and especially in old stripper chemistry, is immersion Tin =
residues....this=20
does not relate to the test above. Rather, your stripper =
chemistry can=20
pickup Tin from the oxide on the plating on outerlayers, and =
redeposit this=20
on the Copper next to it. The potential for this problem =
is=20
magnified tremendously if you strip in a tank, rather than =
exclusively in=20
sprays, and can be strongly affected by the condition of the Tin =
plating=20
solution. If your Tin electroplating solution looks very =
milky, this=20
is disperse Tin oxide, which co-deposits with the Tin metal, then =
easily=20
dissolves in certain kinds of stripper chemistry, and =
redeposits,=20
sometimes even is sprays, on the adjacent Copper.</FONT></FONT>=20
<P><FONT face=3DArial><FONT size=3D-1>The film residues have become =
an especial=20
problem in recent years, as the new generation of photoresists, =
which stick=20
VERY well, require specially formulated types of stripper=20
chemistry.</FONT></FONT>=20
<P><FONT face=3DArial><FONT size=3D-1>I probably have told you more =
than you=20
want to know, but, in case I haven't, you can call me to discuss=20
it.</FONT></FONT>=20
<P><FONT face=3DArial><FONT size=3D-1>Rudy Sedlak</FONT></FONT> =
<BR><FONT=20
face=3DArial><FONT size=3D-1>RD Chemical Company=20
650-962-8004</FONT></FONT></P></BLOCKQUOTE></BLOCKQUOTE></BODY></HTML>
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Date: Fri, 26 Apr 2002 15:13:56 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Steve Kelly <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Steve Kelly <[log in to unmask]>
Subject: Re: test for film residue
X-To: Hinners Hans M Civ WRALC/LUGE <[log in to unmask]>
In-Reply-To: <[log in to unmask]>
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Water break to us does not seem sensitive enough especially when we are
looking at 50-75 micron lines and spaces - will check out the UV light idea.
Thanks. Steve Kelly
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Hinners Hans M Civ
WRALC/LUGE
Sent: Friday, April 26, 2002 1:05 PM
To: [log in to unmask]
Subject: Re: [TN] test for film residue
Hi Steve,
You might try looking at the panels under UV light or a water break test.
Hans
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Hans M. Hinners
Electronics Engineer
Warner Robins - Air Logistics Center (WR-ALC/LUGE)
226 Cochran Street
Robins AFB GA 31098-1622
mailto:[log in to unmask]
Com: (478) 926 - 5224
Fax: (478) 926 - 4911
DSN Prefix: 468
-----Original Message-----
From: Ted Stern [mailto:[log in to unmask]]
Sent: Friday, April 26, 2002 11:47 AM
To: [log in to unmask]
Subject: Re: [TN] test for film residue
Steve:
Another potential source of "residue" on copper surfaces during dry
film stripping is absorption of oils - often attributable to antifoam and/or
excess use of antifoam.
Because copper is very oleophilic, minimal contamination may be
problematic (including fingerprints) and can contribute to a variety of post
strip processing problems; incomplete final etching ("copper spots") being
one of the more common defects. The methods suggested by Rudy would detect
this problem.
As a severe (and unusual) example of oil contamination, we once
encountered a customer employing compressed air agitation to dislodge
accumulated dry film particulate in the corners of the dry film stripper
spray sump. The air was introduced when the line was idle to improve
continuous dry film particulate filtration. The customer had been
employing the process for quite some time when random copper spots began to
be observed. If the stripper was replaced, the problem disappeared; only to
reoccur in 1-2 days. To make a long story short, it was determined (after
eliminating anti-foam, checking for tin in the bath and on panels,
addressing copper oxidation, examining rinse water quality, dry film
leaching in the alkaline etch, etc.) a leaking seal in the air compressor
was contaminating the stripper sump with minute volumes of oil, but enough
to contaminate the copper surface and inhibit alkaline etching.
Regards,
Ted
Rudy Sedlak wrote:
In a message dated 4.25.02 12:23:23 PM Pacific Daylight Time,
[log in to unmask] writes:
Does anyone know of a test to look for film/stripper residue after
copper
stripping.
Assume you mean after stripping film from Copper?
Stripper residue is a tough one, and not real likely to be an issue.
Tarnish could be another issue that is very difficult to test for
except by sight. Depending on stripper, this could be significant....the
clue is, if the problem gets worse as the stripper chemistry gets older, it
is quite possibly tarnish...
Film residue is the most likely residue. One way to test that is a
good test, but, can make your test board need rework is to drop on an
immersion plating solution. Two different ones are common. Some people use
immersion Tin to test if the surface is clean. A drop should plate
uniformly, and adherently. Another test is to drop on Silver Nitrate
solution...usually use the stuff that is used for titration in the lab. The
surface should essentially immediately turn black, and it should be
adherent.
Another residue problem that can occur, and especially in old stripper
chemistry, is immersion Tin residues....this does not relate to the test
above. Rather, your stripper chemistry can pickup Tin from the oxide on the
plating on outerlayers, and redeposit this on the Copper next to it. The
potential for this problem is magnified tremendously if you strip in a tank,
rather than exclusively in sprays, and can be strongly affected by the
condition of the Tin plating solution. If your Tin electroplating solution
looks very milky, this is disperse Tin oxide, which co-deposits with the Tin
metal, then easily dissolves in certain kinds of stripper chemistry, and
redeposits, sometimes even is sprays, on the adjacent Copper.
The film residues have become an especial problem in recent years, as
the new generation of photoresists, which stick VERY well, require specially
formulated types of stripper chemistry.
I probably have told you more than you want to know, but, in case I
haven't, you can call me to discuss it.
Rudy Sedlak
RD Chemical Company 650-962-8004
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charset=3Diso-8859-1">
<META content=3D"MSHTML 5.00.3315.2870" name=3DGENERATOR></HEAD>
<BODY>
<DIV><FONT color=3D#0000ff face=3DArial size=3D2><SPAN =
class=3D750461219-26042002>Water=20
break to us does not seem sensitive enough especially when we are =
looking at=20
50-75 micron lines and spaces - will check out the UV light idea. =
Thanks. Steve=20
Kelly</SPAN></FONT></DIV>
<BLOCKQUOTE dir=3Dltr style=3D"MARGIN-RIGHT: 0px">
<DIV align=3Dleft class=3DOutlookMessageHeader dir=3Dltr><FONT =
face=3DTahoma=20
size=3D2>-----Original Message-----<BR><B>From:</B> TechNet=20
[mailto:[log in to unmask]]<B>On Behalf Of </B>Hinners Hans M Civ=20
WRALC/LUGE<BR><B>Sent:</B> Friday, April 26, 2002 1:05 =
PM<BR><B>To:</B>=20
[log in to unmask]<BR><B>Subject:</B> Re: [TN] test for film=20
residue<BR><BR></DIV></FONT>
<DIV><SPAN class=3D599240317-26042002><FONT color=3D#0000ff>Hi=20
Steve,</FONT></SPAN></DIV>
<DIV><SPAN class=3D599240317-26042002><FONT=20
color=3D#0000ff></FONT></SPAN> </DIV>
<DIV><SPAN class=3D599240317-26042002><FONT color=3D#0000ff>You might =
try looking=20
at the panels under UV light or a water break =
test.</FONT></SPAN></DIV>
<DIV><SPAN class=3D599240317-26042002><FONT=20
color=3D#0000ff></FONT></SPAN> </DIV>
<DIV><SPAN class=3D599240317-26042002><FONT=20
color=3D#0000ff>Hans</FONT></SPAN></DIV>
<DIV><SPAN class=3D599240317-26042002><FONT =
color=3D#0000ff></FONT><BR><FONT=20
face=3DVerdana>~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~</FONT> =
<BR><FONT=20
face=3DVerdana>Hans M. Hinners</FONT> <BR><FONT =
face=3DVerdana>Electronics=20
Engineer</FONT> <BR><FONT face=3DVerdana>Warner Robins - Air Logistics =
Center=20
(WR-ALC/LUGE)</FONT> <BR><FONT face=3DVerdana>226 Cochran =
Street</FONT>=20
<BR><FONT face=3DVerdana>Robins AFB GA 31098-1622</FONT> </DIV>
<DIV>
<P><FONT face=3DVerdana><A=20
=
href=3D"mailto:[log in to unmask]">mailto:[log in to unmask]
mil</A></FONT>=20
</P>
<P><FONT face=3DVerdana>Com: (478) 926 - 5224</FONT> <BR><FONT=20
face=3DVerdana>Fax: (478) 926 - 4911</FONT> <BR><FONT =
face=3DArial=20
size=3D2>DSN Prefix: 468</FONT> </P></SPAN></DIV>
<BLOCKQUOTE dir=3Dltr style=3D"MARGIN-RIGHT: 0px">
<DIV align=3Dleft class=3DOutlookMessageHeader dir=3Dltr><FONT =
face=3DTahoma=20
size=3D2>-----Original Message-----<BR><B>From:</B> Ted Stern=20
[mailto:[log in to unmask]]<BR><B>Sent:</B> Friday, April 26, 2002 =
11:47=20
AM<BR><B>To:</B> [log in to unmask]<BR><B>Subject:</B> Re: [TN] test =
for film=20
residue<BR><BR></FONT></DIV>Steve:=20
<P>Another potential source of "residue" on copper surfaces =
during dry=20
film stripping is absorption of oils - often attributable to =
antifoam and/or=20
excess use of antifoam. <BR>Because copper is very oleophilic, =
minimal=20
contamination may be problematic (including fingerprints) and can =
contribute=20
to a variety of post strip processing problems; incomplete final =
etching=20
("copper spots") being one of the more common defects. The =
methods=20
suggested by Rudy would detect this problem.=20
<P>As a severe (and unusual) example of oil contamination, we once=20
encountered a customer employing compressed air agitation to =
dislodge=20
accumulated dry film particulate in the corners of the dry film =
stripper=20
spray sump. The air was introduced when the line was =
idle to=20
improve continuous dry film particulate filtration. The =
customer=20
had been employing the process for quite some time when random =
copper spots=20
began to be observed. If the stripper was replaced, the =
problem=20
disappeared; only to reoccur in 1-2 days. To make a long story =
short,=20
it was determined (after eliminating anti-foam, checking for tin in =
the bath=20
and on panels, addressing copper oxidation, examining rinse water =
quality,=20
dry film leaching in the alkaline etch, etc.) a leaking seal in the =
air=20
compressor was contaminating the stripper sump with minute volumes =
of oil,=20
but enough to contaminate the copper surface and inhibit alkaline =
etching.=20
<P>Regards, <BR>Ted=20
<P>Rudy Sedlak wrote:=20
<BLOCKQUOTE TYPE=3D"CITE"><FONT face=3DArial><FONT size=3D-1>In a =
message dated=20
4.25.02 12:23:23 PM Pacific Daylight Time, [log in to unmask]
writes:</FONT></FONT> <BR> <BR> =20
<BLOCKQUOTE=20
style=3D"BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; =
MARGIN-RIGHT: 0px; PADDING-LEFT: 5px"=20
TYPE=3D"CITE"><FONT face=3DArial><FONT size=3D-1>Does anyone know =
of a test to=20
look for film/stripper residue after copper</FONT></FONT> =
<BR><FONT=20
face=3DArial><FONT =
size=3D-1>stripping.</FONT></FONT></BLOCKQUOTE>
<P><FONT face=3DArial><FONT size=3D-1>Assume you mean after =
stripping film=20
from Copper?</FONT></FONT>=20
<P><FONT face=3DArial><FONT size=3D-1>Stripper residue is a tough =
one, and not=20
real likely to be an issue.</FONT></FONT>=20
<P><FONT face=3DArial><FONT size=3D-1>Tarnish could be another =
issue that is=20
very difficult to test for except by sight. Depending =
on=20
stripper, this could be significant....the clue is, if the problem =
gets=20
worse as the stripper chemistry gets older, it is quite possibly=20
tarnish...</FONT></FONT>=20
<P><FONT face=3DArial><FONT size=3D-1>Film residue is the most =
likely=20
residue. One way to test that is a good test, but, can make =
your=20
test board need rework is to drop on an immersion plating =
solution. =20
Two different ones are common. Some people use immersion Tin =
to test=20
if the surface is clean. A drop should plate uniformly, and=20
adherently. Another test is to drop on Silver Nitrate=20
solution...usually use the stuff that is used for titration in the =
lab. The surface should essentially immediately turn black, =
and it=20
should be adherent.</FONT></FONT>=20
<P><FONT face=3DArial><FONT size=3D-1>Another residue problem that =
can occur,=20
and especially in old stripper chemistry, is immersion Tin=20
residues....this does not relate to the test above. Rather, =
your=20
stripper chemistry can pickup Tin from the oxide on the plating on =
outerlayers, and redeposit this on the Copper next to =
it. The=20
potential for this problem is magnified tremendously if you strip =
in a=20
tank, rather than exclusively in sprays, and can be strongly =
affected by=20
the condition of the Tin plating solution. If your Tin=20
electroplating solution looks very milky, this is disperse Tin =
oxide,=20
which co-deposits with the Tin metal, then easily dissolves in =
certain=20
kinds of stripper chemistry, and redeposits, sometimes even =
is=20
sprays, on the adjacent Copper.</FONT></FONT>=20
<P><FONT face=3DArial><FONT size=3D-1>The film residues have =
become an=20
especial problem in recent years, as the new generation of =
photoresists,=20
which stick VERY well, require specially formulated types of =
stripper=20
chemistry.</FONT></FONT>=20
<P><FONT face=3DArial><FONT size=3D-1>I probably have told you =
more than you=20
want to know, but, in case I haven't, you can call me to discuss=20
it.</FONT></FONT>=20
<P><FONT face=3DArial><FONT size=3D-1>Rudy Sedlak</FONT></FONT> =
<BR><FONT=20
face=3DArial><FONT size=3D-1>RD Chemical Company=20
=
650-962-8004</FONT></FONT></P></BLOCKQUOTE></BLOCKQUOTE></BLOCKQUOTE></BO=
DY></HTML>
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Date: Fri, 26 Apr 2002 14:51:28 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Microvias and rigid-flex in one board shop?
X-To: [log in to unmask]
Terri,
Don't mean to barge in like this but in the "good old" days of wine, roses,
and the MX missile system as line was drawn in the sand, or rigid flex as it
was. The MX never flew because it had a total of 79 layers of rigid flex
circuitry. One supporting board had 22 layers and continually failed.
It delaminated in several ways and areas. TMA analysis revealed delamination
way below expectations due to the acrylic adhesive used then. Later, after
the program was scrapped, folks like Marty Jawitz (anyone remember Marty) at
Litton Guidance Systems came up with a requirement limiting all rigid flex
designs to 11 layers.
Have some pretty ugly pictures from that era. Probably you and others have
answers overcoming the adhesive problem, cold flowing at room temperature
(Tg of about 70 or so F.). Sure like to get updated on what those answers
might be.
MoonMan
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Date: Fri, 26 Apr 2002 16:10:03 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Roger Stoops <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Roger Stoops <[log in to unmask]>
Subject: Re: 0402 stencil apperture design
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
If memory serves me right (and it normally does not), there was an article
published some years ago that championed oval pads for 0402s. I want to say
somewhere around '92 or '93. (0201s were probably new at that time to the
masses.) I want to say that it was Motorola(tm) that did the studies, and
oval pads and stencil apertures seemed to solve many manufacturing problems
for them. I'll have to rummage through my files one day and find it.
Can not wait until I get to try my hand at some of that itty-bitty stuff,
jealous of those that do...
Best Regards,
Roger M. Stoops, CID [log in to unmask]
TRIMBLE NAVIGATION LIMITED
Engineering and Construction Division
5475 Kellenburger Rd.
Dayton, OH 45424-1099 USA
Telephone: 937 233 8921 800 538 7800 ext. 288
Facsimile: 937 233 7511
http://www.trimble.com
-----Original Message-----
From: Ahne Oosterhof [mailto:[log in to unmask]]
Sent: Friday, April 26, 2002 1:54 PM
To: [log in to unmask]
Subject: Re: [TN] 0402 stencil aperture design
Hi Peter,
At Plexus they have published a rather extensive report on the causes of
tombstoning. It included some remarks on the incidence of solder balls. Both
problem areas are partially caused by pad design on the board and aperture
design in stencils. (Some say the most significant factors for tombstoning
are pick-and-place accuracy and oven temperature profile.)
To minimize tombstoning the report indicates that pad design has a minimal
impact when using 0402-s, but for 0201-s you want to stay close to the
'normal' size for pad design.
To minimize solder balls it is recommended to change stencil apertures to
home plates. My personal preference (and that of some of our customers) is
to change the aperture to an oval, which has the effect of reducing excess
solder in all four corners of the pads. Sometimes in addition the overall
size is reduced by 1 or 2 mil.
An additional advantage is that the OVAL is a Gerber shape improving data
compactness, data sharing and interpretation reliability and it means that
for a single component there are no 'left' and 'right' or 'top' and 'bottom'
apertures (or D-codes).
Have fun,
Ahne.
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of peter lee
Sent: Friday, April 26, 2002 07:58
To: [log in to unmask]
Subject: [TN] 0402 stencil apperture design
Has anyone used a "D"-shape 0402 land pattern on their
design?
The pad dimensions are 18x19mils (semi-circle on the
other ends) and 16mil spacing between the 2 pads.
What would be the stencil apperture recommendation for
the above design? We've used round pads for 0402s and
15% apperture reduction before.
Rgds,
Peter
__________________________________________________
Do You Yahoo!?
Yahoo! Games - play chess, backgammon, pool and more
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Date: Fri, 26 Apr 2002 13:27:44 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Crepeau, Phil" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Crepeau, Phil" <[log in to unmask]>
Subject: Re: Microvias and rigid-flex in one board shop?
X-To: [log in to unmask]
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
hi,
you might be interested in the picture at http://www.af.mil/photos/May1998/0430peacek.jpg
there might not have been rigid-flex circuits in it, but it is 'flying'. and, i hope we won't have to quibble about 'mx,'being renamed 'peacekeeper'.
phil
-----Original Message-----
From: Earl Moon [mailto:[log in to unmask]]
Sent: Friday, April 26, 2002 12:51 PM
To: [log in to unmask]
Subject: Re: [TN] Microvias and rigid-flex in one board shop?
Terri,
Don't mean to barge in like this but in the "good old" days of wine, roses,
and the MX missile system as line was drawn in the sand, or rigid flex as it
was. The MX never flew because it had a total of 79 layers of rigid flex
circuitry. One supporting board had 22 layers and continually failed.
It delaminated in several ways and areas. TMA analysis revealed delamination
way below expectations due to the acrylic adhesive used then. Later, after
the program was scrapped, folks like Marty Jawitz (anyone remember Marty) at
Litton Guidance Systems came up with a requirement limiting all rigid flex
designs to 11 layers.
Have some pretty ugly pictures from that era. Probably you and others have
answers overcoming the adhesive problem, cold flowing at room temperature
(Tg of about 70 or so F.). Sure like to get updated on what those answers
might be.
MoonMan
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Date: Fri, 26 Apr 2002 15:37:13 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Microvias and rigid-flex in one board shop?
X-To: [log in to unmask]
She's a beauty and doesn't appear to be coming down on friendlies as the MX
often appeared to be. Trident never used one ounce of flex or rigid flex in
any of it's multiple warhead systems. I can't remember a failure from the
date Polaris started it all, or was that the second one after?
Always been a flex advocate since the early '70's. Just gotta know where to
draw the line and know what works under what conditions. Hell, it's the same
old story - a fight for love and glory and justifying one's existence and
the ability to wipe out someone else's.
MoonMan
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Date: Fri, 26 Apr 2002 14:13:48 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Sean Hill <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Sean Hill <[log in to unmask]>
Subject: Re: Microvias and rigid-flex in one board shop?
X-To: "Houston, Terri" <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain
Terri,
Try Cirrex Corp in Santa Clara,CA 408-988-3980
-----Original Message-----
From: Houston, Terri [mailto:[log in to unmask]]
Sent: Friday, April 26, 2002 9:36 AM
To: [log in to unmask]
Subject: [TN] Microvias and rigid-flex in one board shop?
Hi folks,
I'm looking for a board shop with actual experience in building a 14+ layer,
rigid-flex board that has microvias in the rigid sections.
It seems the combination of these two features is hard to find at one
supplier, even though I'm only looking for a small quantity of prototypes.
Any suggestions would be greatly appreciated--even self-marketing would be
accepted (off TechNet, please).
Thanks in advance,
Terri
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Date: Fri, 26 Apr 2002 16:51:16 -0500
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Seth Goodman <[log in to unmask]>
Subject: Re: Philips Signetics SCC 68692 Dual UART
X-To: Dennis Petrosky <[log in to unmask]>
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
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boundary="----=_NextPart_000_000D_01C1ED42.94B55220"
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Hi Dennis,
I haven't used this part since around the date code on your earlier ones,
but this sure has the smell of a timing problem. It could be that Philips
changed the process the die is made on, which can easily change the timing
and/or the driver output impedance. Either of these can lead to setup
violations or bus contention. Assuming that the original designer did his
homework on the timing, I'd look for changes to the timing specs or output
drive capability of the newer chips. Another possibility that is less
palatable is that there was a timing problem all along, but you have managed
to stay just this side of failure until the part changed slightly. This is
harder to find since you have to review the whole timing analysis.
Has anything else on this bus changed, such as bus loading (more memory) or
a change in the decoding scheme? Assuming there is a processor in this
system, has the die revision changed on that? As a final thought, check the
errata sheets on the older UART's. It is possible that Philips fixed some
bugs in the die that your software people originally had to work around and
the workaround is now causing the problem.
Good luck!
Regards,
Seth Goodman
Goodman Associates, LLC
tel 608.833.9933
fax 608.833.9966
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Dennis Petrosky
Sent: Thursday, April 25, 2002 9:54 AM
To: [log in to unmask]
Subject: [TN] Philips Signetics SCC 68692 Dual UART
For the Philips Signetics Dual UART, P/N SCC 68692 has anyone seen the
following problems with newer parts. We don't seem to have problems with
older parts, 1994 date code. We have the problems with newer parts 2000 and
2001 parts. We don't know where the date change actually occurred. The
problems don't happen 100% of the time on the new parts. Temperature seems
to affect it. The problem occurrs more often at higher temperatures.
The problems are:
1. The baud rate is wrong by a factor of 16. If you select 19.2K baud
for example, the part tries for 307K baud.
2. The part drops bits on the output data and requires 3 tries on any
RS232 input to get the correct character. For instance, if you are pressing
a series of 1's on the keyboard, then press 2, it will take 3 presses of 2
before the 2 is actually outputed on the UART. The problem seems to be in
changing bits on the output word from low to high. If a bit is high and is
intended to be high, it will stay high. If a bit is low and is intended to
stay low, it will stay low. If a bit is high and needs to go low, it will
go low on the first key press. If a bit is low and needs to go high, it
will take 3 key presses to go high.
Dennis Petrosky
Circuit Card Manufacturing Engineer
607-763-4745
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<DIV><SPAN class=3D564533021-26042002><FONT face=3DArial size=3D2>Hi=20
Dennis,</FONT></SPAN></DIV>
<DIV><FONT face=3DArial><FONT size=3D2><SPAN =
class=3D564533021-26042002><FONT=20
face=3DArial size=3D2></FONT></SPAN></FONT></FONT> </DIV>
<DIV><SPAN class=3D564533021-26042002><FONT face=3DArial size=3D2>I =
haven't used this=20
part since around the date code on your earlier ones, but this sure has =
the=20
smell of a timing problem. It could be that Philips changed the =
process=20
the die is made on, which can easily change the timing and/or the driver =
output=20
impedance. Either of these can lead to setup violations or bus=20
contention. Assuming that the original designer did his homework =
on the=20
timing, I'd look for changes to the timing specs or output drive =
capability of=20
the newer chips. Another possibility that is less palatable is =
that there=20
was a timing problem all along, but you have managed to stay just this =
side of=20
failure until the part changed slightly. This is harder to find =
since you=20
have to review the whole timing analysis.</FONT></SPAN></DIV>
<DIV><FONT face=3DArial><FONT size=3D2><SPAN =
class=3D564533021-26042002><FONT=20
face=3DArial size=3D2></FONT></SPAN></FONT></FONT> </DIV>
<DIV><SPAN class=3D564533021-26042002><FONT face=3DArial size=3D2>Has =
anything else on=20
this bus changed, such as bus loading (more memory) or a change in the =
decoding=20
scheme? Assuming there is a processor in this system, has the die =
revision=20
changed on that? As a final thought, check the errata sheets on =
the older=20
UART's. It is possible that Philips fixed some bugs in the die =
that your=20
software people originally had to work around and the workaround is now =
causing=20
the problem.</FONT></SPAN></DIV>
<DIV><FONT face=3DArial><FONT size=3D2><SPAN =
class=3D564533021-26042002><FONT=20
face=3DArial size=3D2></FONT></SPAN></FONT></FONT> </DIV>
<DIV><SPAN class=3D564533021-26042002><FONT face=3DArial size=3D2>Good=20
luck!</FONT></SPAN></DIV>
<DIV><FONT face=3DArial><FONT size=3D2><SPAN=20
class=3D564533021-26042002></SPAN></FONT></FONT><SPAN=20
class=3D564533021-26042002><FONT face=3DArial color=3D#0000ff=20
size=3D2></FONT> </DIV>
<DIV><FONT face=3DArial size=3D2>Regards,<BR><BR>Seth Goodman<BR>Goodman =
Associates,=20
LLC<BR>tel 608.833.9933<BR>fax 608.833.9966<BR></FONT></DIV>
<DIV></SPAN> </DIV>
<BLOCKQUOTE=20
style=3D"PADDING-LEFT: 5px; MARGIN-LEFT: 5px; BORDER-LEFT: #0000ff 2px =
solid">
<DIV class=3DOutlookMessageHeader dir=3Dltr align=3Dleft><FONT =
face=3DTahoma=20
size=3D2>-----Original Message-----<BR><B>From:</B> TechNet=20
[mailto:[log in to unmask]]<B>On Behalf Of </B>Dennis =
Petrosky<BR><B>Sent:</B>=20
Thursday, April 25, 2002 9:54 AM<BR><B>To:</B>=20
[log in to unmask]<BR><B>Subject:</B> [TN] Philips Signetics SCC 68692 =
Dual=20
UART<BR><BR></FONT></DIV><BR><FONT face=3Dsans-serif size=3D2>For the =
Philips=20
Signetics Dual UART, P/N SCC 68692 has anyone seen the following =
problems with=20
newer parts. We don't seem to have problems with older parts, =
1994 date=20
code. We have the problems with newer parts 2000 and 2001 parts. =
We don't know where the date change actually occurred. The =
problems don't happen 100% of the time on the new parts. =
Temperature=20
seems to affect it. The problem occurrs more often at higher=20
temperatures.</FONT> <BR><BR><FONT face=3Dsans-serif size=3D2>The =
problems=20
are:</FONT> <BR><FONT face=3Dsans-serif size=3D2>1. The baud =
rate is wrong=20
by a factor of 16. If you select 19.2K baud for example, the =
part tries=20
for 307K baud.</FONT> <BR><BR><FONT face=3Dsans-serif size=3D2>2. =
The part=20
drops bits on the output data and requires 3 tries on any RS232 input =
to get=20
the correct character. For instance, if you are pressing a =
series of 1's=20
on the keyboard, then press 2, it will take 3 presses of 2 before the =
2 is=20
actually outputed on the UART. The problem seems to be in =
changing bits=20
on the output word from low to high. If a bit is high and is =
intended to=20
be high, it will stay high. If a bit is low and is intended to =
stay low,=20
it will stay low. If a bit is high and needs to go low, it will =
go low=20
on the first key press. If a bit is low and needs to go high, it =
will=20
take 3 key presses to go high.</FONT> <BR><BR><BR><BR><FONT =
face=3Dsans-serif=20
size=3D2>Dennis Petrosky<BR>Circuit Card Manufacturing=20
Engineer<BR>607-763-4745</FONT></BLOCKQUOTE></BODY></HTML>
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Date: Fri, 26 Apr 2002 18:18:06 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
David Fish <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: David Fish <[log in to unmask]>
Subject: Re: Immersion Gold Vs Immersion Tin for 0201 landpatterns
X-To: [log in to unmask]
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit
Imm tin at 44 micron!!! Wow, that seems very thick. We expect minimum
thickness of 0.65 microns with a maximum thickness of 1.5 microns.
Dave Fish
----- Original Message -----
From: "Tuan Bui" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Friday, April 26, 2002 11:05 AM
Subject: Re: [TN] Immersion Gold Vs Immersion Tin for 0201 landpatterns
> Hi George,
>
> The Immersion Gold process that the PCB vendor stated that the Immersion
> gold (7-10 micron) over nickel over copper. The Immersion Tin process, as
> you have mentioned, is about 44 micron. It is good to hear that the
> immersion tin process can be easily/inexpensive reworked when its shelf
> live expires.
>
> BTW, thanks for your input.
>
> Tuan Bui
> Proc Dev Eng
> Conexant Systems Inc.
>
>
>
> George Milad
> <[log in to unmask]> To: [log in to unmask]
> Sent by: TechNet cc:
> <[log in to unmask]> Subject: Re: [TN]
Immersion Gold Vs Immersion Tin for 0201 landpatterns
>
>
> 04/26/2002 08:47
> AM
> Please respond to
> "TechNet E-Mail
> Forum."; Please
> respond to Gmilad
>
>
>
>
>
>
> Tuan,
> Could you clarify the "Immersion Gold" process that you are using. Is it
> Immersion gold over copper or it immersion gold over nickel over copper?
>
> Immersion Tin is a viable alternative for your application. However the
> thickness required will much higher than the 7 - 8 uins that you are
> presently using for gold, more like 30 - 40 uins. Tin is realtive
> inexpensive and can be easily reworked if shelf life becomes an issue.
>
> George Milad
> HDI Consulting
> Chairman IPC Plating Committee.
>
> --------------------------------------------------------------------------
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=========================================================================
Date: Sat, 27 Apr 2002 00:22:07 +0200
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"D.Terstegge" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "D.Terstegge" <[log in to unmask]>
Subject: Re: 0402 stencil apperture design
X-To: Roger Stoops <[log in to unmask]>
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The plexus report is published in '98 and is still pretty up-to-date, =
but it doesn't have much info about stencil apertures (but it's still =
interesting).=20
The report has disappeared from the plexus website, but you can still =
download it at http://www.smtinfo.net/docs/tombstoning.pdf
B.T.W. I'd say that even now 0201's are new to the masses, don't you =
think so Roger ?
Daan Terstegge
http://www.smtinfo.net
----- Original Message -----=20
From: Roger Stoops=20
To: [log in to unmask]
Sent: Friday, April 26, 2002 10:10 PM
Subject: Re: [TN] 0402 stencil apperture design
If memory serves me right (and it normally does not), there was an =
article
published some years ago that championed oval pads for 0402s. I want =
to say
somewhere around '92 or '93. (0201s were probably new at that time to =
the
masses.) I want to say that it was Motorola(tm) that did the studies, =
and
oval pads and stencil apertures seemed to solve many manufacturing =
problems
for them. I'll have to rummage through my files one day and find it.
Can not wait until I get to try my hand at some of that itty-bitty =
stuff,
jealous of those that do...
Best Regards,
Roger M. Stoops, CID [log in to unmask]
TRIMBLE NAVIGATION LIMITED
Engineering and Construction Division
5475 Kellenburger Rd.
Dayton, OH 45424-1099 USA
Telephone: 937 233 8921 800 538 7800 ext. 288
Facsimile: 937 233 7511
http://www.trimble.com
-----Original Message-----
From: Ahne Oosterhof [mailto:[log in to unmask]]
Sent: Friday, April 26, 2002 1:54 PM
To: [log in to unmask]
Subject: Re: [TN] 0402 stencil aperture design
Hi Peter,
At Plexus they have published a rather extensive report on the causes =
of
tombstoning. It included some remarks on the incidence of solder =
balls. Both
problem areas are partially caused by pad design on the board and =
aperture
design in stencils. (Some say the most significant factors for =
tombstoning
are pick-and-place accuracy and oven temperature profile.)
To minimize tombstoning the report indicates that pad design has a =
minimal
impact when using 0402-s, but for 0201-s you want to stay close to the
'normal' size for pad design.
To minimize solder balls it is recommended to change stencil apertures =
to
home plates. My personal preference (and that of some of our =
customers) is
to change the aperture to an oval, which has the effect of reducing =
excess
solder in all four corners of the pads. Sometimes in addition the =
overall
size is reduced by 1 or 2 mil.
An additional advantage is that the OVAL is a Gerber shape improving =
data
compactness, data sharing and interpretation reliability and it means =
that
for a single component there are no 'left' and 'right' or 'top' and =
'bottom'
apertures (or D-codes).
Have fun,
Ahne.
-----Original Message-----
From: TechNet [mailto:[log in to unmask]] On Behalf Of peter lee
Sent: Friday, April 26, 2002 07:58
To: [log in to unmask]
Subject: [TN] 0402 stencil apperture design
Has anyone used a "D"-shape 0402 land pattern on their
design?
The pad dimensions are 18x19mils (semi-circle on the
other ends) and 16mil spacing between the 2 pads.
What would be the stencil apperture recommendation for
the above design? We've used round pads for 0402s and
15% apperture reduction before.
Rgds,
Peter
__________________________________________________
Do You Yahoo!?
Yahoo! Games - play chess, backgammon, pool and more
http://games.yahoo.com/
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<DIV>The plexus report is published in '98 and is still pretty =
up-to-date,=20
but it doesn't have much info about stencil apertures (but it's =
still=20
interesting). </DIV>
<DIV>The report has disappeared from the plexus website, but you =
can still=20
download it at <A=20
href=3D"http://www.smtinfo.net/docs/tombstoning.pdf">http://www.smtinfo.n=
et/docs/tombstoning.pdf</A></DIV>
<DIV>B.T.W. I'd say that even now 0201's are new to the =
masses, don't=20
you think so Roger ?</DIV>
<DIV> </DIV>
<DIV>Daan Terstegge</DIV>
<DIV>http://<A href=3D"http://www.smtinfo.net">www.smtinfo.net</A></DIV>
<DIV> </DIV>
<BLOCKQUOTE=20
style=3D"PADDING-RIGHT: 0px; PADDING-LEFT: 5px; MARGIN-LEFT: 5px; =
BORDER-LEFT: #000000 2px solid; MARGIN-RIGHT: 0px">
<DIV style=3D"FONT: 10pt arial">----- Original Message ----- </DIV>
<DIV=20
style=3D"BACKGROUND: #e4e4e4; FONT: 10pt arial; font-color: =
black"><B>From:</B>=20
<A [log in to unmask] =
href=3D"mailto:[log in to unmask]">Roger=20
Stoops</A> </DIV>
<DIV style=3D"FONT: 10pt arial"><B>To:</B> <A [log in to unmask]
href=3D"mailto:[log in to unmask]">[log in to unmask]</A> </DIV>
<DIV style=3D"FONT: 10pt arial"><B>Sent:</B> Friday, April 26, 2002 =
10:10=20
PM</DIV>
<DIV style=3D"FONT: 10pt arial"><B>Subject:</B> Re: [TN] 0402 stencil =
apperture=20
design</DIV>
<DIV><BR></DIV>If memory serves me right (and it normally does not), =
there was=20
an article<BR>published some years ago that championed oval pads for =
0402s. I=20
want to say<BR>somewhere around '92 or '93. (0201s were probably new =
at that=20
time to the<BR>masses.) I want to say that it was Motorola(tm) =
that did=20
the studies, and<BR>oval pads and stencil apertures seemed to solve =
many=20
manufacturing problems<BR>for them. I'll have to rummage through =
my=20
files one day and find it.<BR>Can not wait until I get to try my hand =
at some=20
of that itty-bitty stuff,<BR>jealous of those that do...<BR>Best=20
Regards,<BR><BR>Roger M. Stoops, CID <A=20
=
href=3D"mailto:[log in to unmask]">[log in to unmask]</A><BR>=
TRIMBLE=20
NAVIGATION LIMITED<BR>Engineering and Construction Division<BR>5475=20
Kellenburger Rd.<BR>Dayton, OH =20
45424-1099 USA<BR>Telephone: 937 =
233=20
8921 800 538 =
7800 =20
ext. 288<BR>Facsimile: 937 233 7511<BR><BR><A=20
=
href=3D"http://www.trimble.com">http://www.trimble.com</A><BR><BR><BR><BR=
> -----Original=20
Message-----<BR>From: Ahne Oosterhof=20
[mailto:[log in to unmask]]<BR>Sent: Friday, April 26, 2002 =
1:54=20
PM<BR>To: <A=20
=
href=3D"mailto:[log in to unmask]">[log in to unmask]</A><BR>Subject: &nbs=
p; =20
Re: [TN] 0402 stencil aperture design<BR><BR>Hi Peter,<BR>At Plexus =
they have=20
published a rather extensive report on the causes of<BR>tombstoning. =
It=20
included some remarks on the incidence of solder balls. =
Both<BR>problem areas=20
are partially caused by pad design on the board and aperture<BR>design =
in=20
stencils. (Some say the most significant factors for =
tombstoning<BR>are=20
pick-and-place accuracy and oven temperature profile.)<BR><BR>To =
minimize=20
tombstoning the report indicates that pad design has a =
minimal<BR>impact when=20
using 0402-s, but for 0201-s you want to stay close to the<BR>'normal' =
size=20
for pad design.<BR><BR>To minimize solder balls it is recommended to =
change=20
stencil apertures to<BR>home plates. My personal preference (and that =
of some=20
of our customers) is<BR>to change the aperture to an oval, which has =
the=20
effect of reducing excess<BR>solder in all four corners of the pads. =
Sometimes=20
in addition the overall<BR>size is reduced by 1 or 2 mil.<BR><BR>An =
additional=20
advantage is that the OVAL is a Gerber shape improving =
data<BR>compactness,=20
data sharing and interpretation reliability and it means that<BR>for a =
single=20
component there are no 'left' and 'right' or 'top' and =
'bottom'<BR>apertures=20
(or D-codes).<BR><BR>Have fun,<BR>Ahne.<BR><BR><BR>-----Original=20
Message-----<BR>From: TechNet [mailto:[log in to unmask]] On =
Behalf=20
Of peter lee<BR>Sent: Friday, April 26, 2002=20
07:58<BR>To: <A=20
=
href=3D"mailto:[log in to unmask]">[log in to unmask]</A><BR>Subject: &nbs=
p; =20
[TN] 0402 stencil apperture design<BR><BR>Has anyone used a "D"-shape =
0402=20
land pattern on their<BR>design?<BR><BR>The pad dimensions are =
18x19mils=20
(semi-circle on the<BR>other ends) and 16mil spacing between the 2=20
pads.<BR><BR>What would be the stencil apperture recommendation =
for<BR>the=20
above design? We've used round pads for 0402s and<BR>15% apperture =
reduction=20
=
before.<BR><BR><BR>Rgds,<BR>Peter<BR><BR><BR>____________________________=
______________________<BR>Do=20
You Yahoo!?<BR>Yahoo! Games - play chess, backgammon, pool and =
more<BR><A=20
=
href=3D"http://games.yahoo.com/">http://games.yahoo.com/</A><BR><BR>-----=
-----------------------------------------------------------------------<B=
R>-----<BR>Technet=20
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=
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Date: Fri, 26 Apr 2002 16:19:51 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Tuan Bui <[log in to unmask]>
Subject: Re: Immersion Gold Vs Immersion Tin for 0201 landpatterns
X-To: David Fish <[log in to unmask]>
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
David,
I double checked the Tin thickness and you are right. 44 micron is too
thick. The correct measurement is .7 microns (~ 44 micro inches)
Thanks for catching that.
Tuan
"David Fish"
<[log in to unmask] To: "TechNet E-Mail Forum." <[log in to unmask]>, <[log in to unmask]>
> cc:
Subject: Re: Re: [TN] Immersion Gold Vs Immersion Tin for 0201 landpatterns
04/26/2002 06:18
PM
Imm tin at 44 micron!!! Wow, that seems very thick. We expect minimum
thickness of 0.65 microns with a maximum thickness of 1.5 microns.
Dave Fish
----- Original Message -----
From: "Tuan Bui" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Friday, April 26, 2002 11:05 AM
Subject: Re: [TN] Immersion Gold Vs Immersion Tin for 0201 landpatterns
> Hi George,
>
> The Immersion Gold process that the PCB vendor stated that the Immersion
> gold (7-10 micron) over nickel over copper. The Immersion Tin process, as
> you have mentioned, is about 44 micron. It is good to hear that the
> immersion tin process can be easily/inexpensive reworked when its shelf
> live expires.
>
> BTW, thanks for your input.
>
> Tuan Bui
> Proc Dev Eng
> Conexant Systems Inc.
>
>
>
> George Milad
> <[log in to unmask]> To: [log in to unmask]
> Sent by: TechNet cc:
> <[log in to unmask]> Subject: Re: [TN]
Immersion Gold Vs Immersion Tin for 0201 landpatterns
>
>
> 04/26/2002 08:47
> AM
> Please respond to
> "TechNet E-Mail
> Forum."; Please
> respond to Gmilad
>
>
>
>
>
>
> Tuan,
> Could you clarify the "Immersion Gold" process that you are using. Is it
> Immersion gold over copper or it immersion gold over nickel over copper?
>
> Immersion Tin is a viable alternative for your application. However the
> thickness required will much higher than the 7 - 8 uins that you are
> presently using for gold, more like 30 - 40 uins. Tin is realtive
> inexpensive and can be easily reworked if shelf life becomes an issue.
>
> George Milad
> HDI Consulting
> Chairman IPC Plating Committee.
>
>
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Date: Sat, 27 Apr 2002 16:30:46 +0000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
LINO REBOREDO <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: LINO REBOREDO <[log in to unmask]>
Subject: Re: FAB Question: laminate - 1 ply or 2??
Mime-Version: 1.0
Content-Type: text/plain; charset=iso-8859-1; format=flowed
Dear Pete, I also made myself your question time ago, my relative truth is
that in all cases that you can use 2 plies used it, One ply means that the
ply system resin- reinforce must be in perfect state, no fault is admitted.
I never had meet an adhesion problem using one ply,
but i had meet dielectrical lacks betw. layer and was due to operational
asemblies fault.
at the end is as we say :is not the same the double than the half
regards,
lino
>From: Pete Jones <[log in to unmask]>
>Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, Pete Jones
><[log in to unmask]>
>To: [log in to unmask]
>Subject: [TN] FAB Question: laminate - 1 ply or 2??
>Date: Thu, 25 Apr 2002 09:55:27 -0400
>
>Hello all TechNetters,
>
>What is the difference between using 1 ply of laminate or 2 in fab boards?
>
>Is there a REAL concern that 1 ply will not be sufficient electrical
>insolation? Or has resins now evolved enough to make it safe to use just
>one
>ply?
>
>I deal mostly, but not exclusively, with the military and would like to
>make
>sure of my statement that 1 ply should be sufficient. Can I get reliable
>references anywhere concerning this issue, one way or the other?
>
>Thanks to all participants in this discussion.
>
>Pete
>
>_________________________________________________________________
>Join the world’s largest e-mail service with MSN Hotmail.
>http://www.hotmail.com
>
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Date: Sat, 27 Apr 2002 12:42:24 EDT
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Microvias and rigid-flex in one board shop?
MIME-Version: 1.0
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Hello Terri,
I can build flex with microvias. We are selective though, regarding flex
that is. I would suggest the APLS flex (no adhesive) and if conventional
cover coat is used to terminate after rigid area entry. This area must be no
via zone. The rigid needs to be epoxy (aka FR4) [I used to be a BIG
polyimide guy], don't bond your flex layers together, keep board aspect
ratio below 6.5/1, microvia aspect ratios below .75/1, Silver or Tin finish.
Make the build symmetrical about the vertical centerline. Prior to proto
build have a mock up made for mechanical/sanity check.
If I didn't go to me I would go to Pioneer (Santa Ana, CA, Ken Lee) or
Cosomtronics (Irvine, CA, Dick Berger). Both these folks are HiRel flex
shops and smart people that build excellent flex (my own first hand
experience) BUT I do NOT know their capability of micro via technology. That
is not meant to be derogatory.
I have built micro via flex, it is better to get a micro via shop to build
flex than a flex shop to builds micro via.
Contact me if more detail/opinion is needed.
Boston Brad
781 858 0783
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Content-Type: text/html; charset="US-ASCII"
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<HTML><FONT FACE=arial,helvetica><FONT SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0">Hello Terri,<BR>
<BR>
I can build flex with microvias. We are selective though, regarding flex that is. I would suggest the APLS flex (no adhesive) and if conventional cover coat is used to terminate after rigid area entry. This area must be no via zone. The rigid needs to be epoxy (aka FR4) [I used to be a BIG polyimide guy], don't bond your flex layers together, keep board aspect ratio below 6.5/1, microvia aspect ratios below .75/1, Silver or Tin finish. Make the build symmetrical about the vertical centerline. Prior to proto build have a mock up made for mechanical/sanity check.<BR>
If I didn't go to me I would go to Pioneer (Santa Ana, CA, Ken Lee) or Cosomtronics (Irvine, CA, Dick Berger). Both these folks are HiRel flex shops and smart people that build excellent flex (my own first hand experience) BUT I do NOT know their capability of micro via technology. That is not meant to be derogatory.<BR>
I have built micro via flex, it is better to get a micro via shop to build flex than a flex shop to builds micro via.<BR>
<BR>
Contact me if more detail/opinion is needed.<BR>
<BR>
Boston Brad<BR>
781 858 0783<BR>
<BR>
</FONT></HTML>
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Date: Sat, 27 Apr 2002 12:57:31 EDT
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Microvias and rigid-flex in one board shop?
MIME-Version: 1.0
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Moon,
I meet many people involved in the dreaded "MX flex." It did go through some
extensive "envelope" changes, many of which I was not privy to in that they
were before my time. I was heavily involved in the final end product and can
unequivocally state it is a sound robust design that is indeed "failsafe." I
have worked a great many Defense applications and I say to this day I have
never worked with a more professional group or have more certainty of
performance than the MX; PeaceKeeper.
BB
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<HTML><FONT FACE=arial,helvetica><FONT SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0">Moon,<BR>
<BR>
I meet many people involved in the dreaded "MX flex." It did go through some extensive "envelope" changes, many of which I was not privy to in that they were before my time. I was heavily involved in the final end product and can unequivocally state it is a sound robust design that is indeed "failsafe." I have worked a great many Defense applications and I say to this day I have never worked with a more professional group or have more certainty of performance than the MX; PeaceKeeper.<BR>
<BR>
BB </FONT></HTML>
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Date: Sat, 27 Apr 2002 13:05:53 EDT
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Rick Fudalewski <[log in to unmask]>
Subject: HDIC
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Question
does the term "HDIC" stand for high density integrated circuits?
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<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>Question
<BR>
<BR>does the term "HDIC" stand for high density integrated circuits?</FONT></HTML>
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Date: Sat, 27 Apr 2002 12:02:03 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Microvias and rigid-flex in one board shop?
X-To: [log in to unmask]
saunders,
As you say, you were not there in the early days. However, all the folks
were very professional. They just didn't have the technology early on to get
the project to market as soon as they would have wished. Obviously you do
and that's good for us all.
MoonMan
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Date: Sat, 27 Apr 2002 13:29:34 EDT
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Via Plug
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Hello John,
Via plug is one of the fastest growing requests of board buyers/users today.
Mainly in the arena of electrical interconnection in the CSP or sub .8mm BGA
substrates. Thermagon is a very good thermal dielectric (www.thermagon.com)
and their "in-situ" hole fill may be what your looking for, although it is
best used to bond PCBs to alum or copper heat plates. It can also be readily
used as the dielectric system for single, double or multilayer boards. It is
conventional E-glass with a modified epoxy that has 10x betterment of thermal
transfer properties. We use a high silver content epoxy hole fill supplied
by three different suppliers. These are all great materials but will not do
a thermal transfer job very well. If it is a through PCB thermal transfer
you can't beat the performance of an additional plated through hole combined
with copper planes (large and or small). The challenge is where does the
heat go from there and how. That is an assembly issue and volume has
everything to do with appropriate configuration. I've done quite a bit of
that send a reply to continue the thread.
Boston Brad
--part1_51.1d2ad0a3.29fc39fe_boundary
Content-Type: text/html; charset="US-ASCII"
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<HTML><FONT FACE=arial,helvetica><FONT SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0">Hello John,<BR>
<BR>
Via plug is one of the fastest growing requests of board buyers/users today. Mainly in the arena of electrical interconnection in the CSP or sub .8mm BGA substrates. Thermagon is a very good thermal dielectric (www.thermagon.com) and their "in-situ" hole fill may be what your looking for, although it is best used to bond PCBs to alum or copper heat plates. It can also be readily used as the dielectric system for single, double or multilayer boards. It is conventional E-glass with a modified epoxy that has 10x betterment of thermal transfer properties. We use a high silver content epoxy hole fill supplied by three different suppliers. These are all great materials but will not do a thermal transfer job very well. If it is a through PCB thermal transfer you can't beat the performance of an additional plated through hole combined with copper planes (large and or small). The challenge is where does the heat go from there and how. That is!
an assembly issue and volume has everything to do with appropriate configuration. I've done quite a bit of that send a reply to continue the thread. <BR>
<BR>
Boston Brad </FONT></HTML>
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Date: Sat, 27 Apr 2002 13:42:39 EDT
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: HDIC
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High Denity InterConnects
> Question
>
> does the term "HDIC" stand for high density integrated circuits?
--part1_15d.d0ed3b1.29fc3d0f_boundary
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<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>High Denity InterConnects<BR>
<BR>
<BR>
<BLOCKQUOTE TYPE=CITE style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">Question<BR>
<BR>
does the term "HDIC" stand for high density integrated circuits?</BLOCKQUOTE><BR>
<BR>
</FONT></HTML>
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Date: Sat, 27 Apr 2002 12:48:12 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Via Plug
One of the best places for the heat to go is a cold wall.
MoonMan
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Date: Mon, 29 Apr 2002 12:14:43 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
fullname <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: fullname <[log in to unmask]>
Organization: DSO National Laboratories
Subject: Looking for Happy Holden
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I would like to have Happy Holden's contact especially email address.
Your reply would be appreciated.
Regards - Wee Mei
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Date: Mon, 29 Apr 2002 13:39:38 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Via Plug
X-To: "Mcmaster, Michael" <[log in to unmask]>
MIME-Version: 1.0
Content-type: text/plain; charset=us-ascii
Michael,
My thermal engineer assures me that the K value for copper is between 150
and 200 W/mK, but even so, your point about replacing CB100 (now CB101, by
the way) with additional copper plating is a valid one, and offers much
simpler, quicker and less costly PCB fabrication.
The only caveat I would add is, make sure the ductility for your additional
copper plating thickness is enough to avoid cracking the barrels under
temperature cycling, especially if using FR4.
Peter
"Mcmaster, Michael" <[log in to unmask]> 26/04/2002 11:58 PM
Sent by: TechNet <[log in to unmask]>
Please respond to "TechNet E-Mail Forum."; Please respond to "Mcmaster,
Michael"
To: [log in to unmask]
cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST Aero/ST Group)
Subject: Re: [TN] Via Plug
John
The DuPont CB-100 will increase the amount of heat that can be conducted
through the barrel. My experience with it that most people overestimate
what it can do. I've done calculations that show for a 0.020" drilled hole
with 0.001" copper barrel, adding CB-100 only increases the amount of heat
by less than 5%. The reason is the CB-100 has a thermal conductivity of
5.23
W/mK vs 395 W/mK for copper. Even though CB-100 makes up the majority of
the cross sectional area, it only adds a little to the "thermal" cross
section.
I always recommend that potential users of this technology run the numbers
themselves and balance the potential cost increase with the improved
performance.
> ----------
> From: John Foster[SMTP:[log in to unmask]]
> Reply To: TechNet E-Mail Forum.;John Foster
> Sent: Tuesday, April 23, 2002 12:06 PM
> To: [log in to unmask]
> Subject: [TN] Via Plug
>
> Hello, I am new to this listserver. I must say that it is very
> informative. I wish I had known of it long ago.
>
> I have a question about via plugging. Right now
> our board vendor is doing our via plugs with
> I guess with a standard epoxy. We are trying
> to find a solution that would give us a much
> better thermal performance.
>
> We are looking at silver epoxy and this
> material from Dupont. Does anyone know of
> some material that would give us a really good
> thermal performance. We are in a commercial
> environment. So the material does not have to
> meet industrial specs.
>
> Any input on this matter would be greatly '
> appreciated.
>
> Thank You
>
> John Foster
>
>
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Date: Mon, 29 Apr 2002 10:00:05 +0100
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"FOX, Ian (York Rd)" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "FOX, Ian (York Rd)" <[log in to unmask]>
Subject: Re: Via Plug
X-To: "[log in to unmask]" <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
It's a very poor Cu alloy with a thermal conductivity that low, you're
talking BeCu at that level. 395 is about right for high purity material
Ian Fox
TRW AS
-----Original Message-----
From: [log in to unmask] [mailto:[log in to unmask]]
Sent: 29 April 2002 06:40
To: [log in to unmask]
Subject: Re: [TN] Via Plug
Michael,
My thermal engineer assures me that the K value for copper is between 150
and 200 W/mK, but even so, your point about replacing CB100 (now CB101, by
the way) with additional copper plating is a valid one, and offers much
simpler, quicker and less costly PCB fabrication.
The only caveat I would add is, make sure the ductility for your additional
copper plating thickness is enough to avoid cracking the barrels under
temperature cycling, especially if using FR4.
Peter
"Mcmaster, Michael" <[log in to unmask]> 26/04/2002 11:58 PM
Sent by: TechNet <[log in to unmask]>
Please respond to "TechNet E-Mail Forum."; Please respond to "Mcmaster,
Michael"
To: [log in to unmask]
cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST Aero/ST Group)
Subject: Re: [TN] Via Plug
John
The DuPont CB-100 will increase the amount of heat that can be conducted
through the barrel. My experience with it that most people overestimate
what it can do. I've done calculations that show for a 0.020" drilled hole
with 0.001" copper barrel, adding CB-100 only increases the amount of heat
by less than 5%. The reason is the CB-100 has a thermal conductivity of
5.23
W/mK vs 395 W/mK for copper. Even though CB-100 makes up the majority of
the cross sectional area, it only adds a little to the "thermal" cross
section.
I always recommend that potential users of this technology run the numbers
themselves and balance the potential cost increase with the improved
performance.
> ----------
> From: John Foster[SMTP:[log in to unmask]]
> Reply To: TechNet E-Mail Forum.;John Foster
> Sent: Tuesday, April 23, 2002 12:06 PM
> To: [log in to unmask]
> Subject: [TN] Via Plug
>
> Hello, I am new to this listserver. I must say that it is very
> informative. I wish I had known of it long ago.
>
> I have a question about via plugging. Right now
> our board vendor is doing our via plugs with
> I guess with a standard epoxy. We are trying
> to find a solution that would give us a much
> better thermal performance.
>
> We are looking at silver epoxy and this
> material from Dupont. Does anyone know of
> some material that would give us a really good
> thermal performance. We are in a commercial
> environment. So the material does not have to
> meet industrial specs.
>
> Any input on this matter would be greatly '
> appreciated.
>
> Thank You
>
> John Foster
>
>
--------------------------------------------------------------------------
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Date: Mon, 29 Apr 2002 06:06:08 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Looking for Happy Holden
X-To: fullname <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit
Check over at the CircuiTree magazine forum. He's on all the time.
Earl
----- Original Message -----
From: "fullname" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Monday, April 29, 2002 12:14 AM
Subject: [TN] Looking for Happy Holden
> I would like to have Happy Holden's contact especially email address.
> Your reply would be appreciated.
>
> Regards - Wee Mei
>
> --------------------------------------------------------------------------
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Date: Sun, 1 Apr 2001 03:37:24 +1000
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
chris johnston <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: chris johnston <[log in to unmask]>
Subject: Re: Looking for Happy Holden
X-To: fullname <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
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Sorry, don't know any happy holden, cannot help.
-----Original Message-----
From: fullname <[log in to unmask]>
To: [log in to unmask] <[log in to unmask]>
Date: Monday, April 29, 2002 3:09 PM
Subject: [TN] Looking for Happy Holden
>I would like to have Happy Holden's contact especially email address.
>Your reply would be appreciated.
>
>Regards - Wee Mei
>
>---------------------------------------------------------------------------
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>---------------------------------------------------------------------------
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>
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Date: Mon, 29 Apr 2002 08:00:36 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Dieselberg, Ron" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Dieselberg, Ron" <[log in to unmask]>
Subject: Re: HDIC
X-To: "[log in to unmask]" <[log in to unmask]>
MIME-Version: 1.0
Content-Type: multipart/alternative;
boundary="----_=_NextPart_001_01C1EF75.79147340"
This message is in MIME format. Since your mail reader does not understand
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------_=_NextPart_001_01C1EF75.79147340
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charset="iso-8859-1"
According to acronymfinder.com that is the only listing, Rick.
Ron Dieselberg
Trainer/Auditor
CMC ELECTRONICS
CINCINNATI
[log in to unmask]
-----Original Message-----
From: Rick Fudalewski [mailto:[log in to unmask]]
Sent: Saturday, April 27, 2002 13:06 PM
To: [log in to unmask]
Subject: [TN] HDIC
Question
does the term "HDIC" stand for high density integrated circuits?
------_=_NextPart_001_01C1EF75.79147340
Content-Type: text/html;
charset="iso-8859-1"
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META HTTP-EQUIV="Content-Type" CONTENT="text/html; charset=iso-8859-1">
<META content="MSHTML 5.50.4522.1800" name=GENERATOR></HEAD>
<BODY>
<DIV><SPAN class=530404311-29042002><FONT face=Arial color=#0000ff>According to
acronymfinder.com that is the only listing, Rick.</FONT></SPAN></DIV>
<DIV> </DIV>
<P><FONT face=Arial size=2>Ron Dieselberg</FONT> <BR><FONT face=Arial
size=2>Trainer/Auditor</FONT> <BR><FONT face=Arial size=2>CMC ELECTRONICS</FONT>
<BR><FONT face=Arial size=2>CINCINNATI</FONT> <BR><FONT face=Arial
size=2>[log in to unmask]</FONT> </P>
<DIV> </DIV>
<BLOCKQUOTE>
<DIV class=OutlookMessageHeader><FONT face="Times New Roman"
size=2>-----Original Message-----<BR><B>From:</B> Rick Fudalewski
[mailto:[log in to unmask]]<BR><B>Sent:</B> Saturday, April 27, 2002 13:06
PM<BR><B>To:</B> [log in to unmask]<BR><B>Subject:</B> [TN]
HDIC<BR><BR></FONT></DIV><FONT face=arial,helvetica><FONT size=2>Question
<BR><BR>does the term "HDIC" stand for high density integrated
circuits?</FONT> </FONT></BLOCKQUOTE></BODY></HTML>
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Date: Mon, 29 Apr 2002 08:35:58 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Sherif Refaat <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Sherif Refaat <[log in to unmask]>
Subject: Re: Looking for Happy Holden
X-To: fullname <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
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His office telephone number is (203) 937 8622
Sherif Refaat,
----- Original Message -----
From: "fullname" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Monday, April 29, 2002 12:14 AM
Subject: [TN] Looking for Happy Holden
> I would like to have Happy Holden's contact especially email address.
> Your reply would be appreciated.
>
> Regards - Wee Mei
>
> --------------------------------------------------------------------------
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Date: Mon, 29 Apr 2002 09:40:09 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Tempea, Ioan" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Tempea, Ioan" <[log in to unmask]>
Subject: Re: Flip-flop panels
MIME-Version: 1.0
Content-Type: text/plain
Now I got all mixed up.
I'm mainly talking about multilayer boards. Basically small piggy backs, but
MLBs still!
Is it doable or not?
And, of course, thanks for the input, Dennis, Jac, Robert and Eddie.
Ioan
> -----Original Message-----
> From: Eddie Rocha [SMTP:[log in to unmask]]
> Sent: Wednesday, April 24, 2002 6:45 PM
> To: [log in to unmask]
> Subject: Re: [TN] Flip-flop panels
>
> Flip flopping multilayer bds can get complicated and is not
> recommended. It cannot be done if the layer stack-up is not
> symmetrical.
> thanks,
>
> --------------------------------------------------------------------------
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Date: Mon, 29 Apr 2002 09:35:54 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Sauer, Steven T." <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Sauer, Steven T." <[log in to unmask]>
Subject: Re: Looking for Happy Holden
X-To: fullname <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Good Morning Wee Mei,
I took the following directly from a recent article in CircuiTree Magazine:
Happy Holden is manager of advanced technologies for Westwood Associates
(West Haven, CT). He is responsible for next-generation printed circuit
manufacturing technologies, advanced design tools, and design consulting.
Prior to joining Westwood, he was a consultant with TechLead Corporation,
and had been at Hewlett-Packard for over 27 years. Holden formally managed
Hewlett Packard's application organizations in the Far East and holds
degrees in Chemical Engineering and Computer Science. If you have questions,
he can be contacted via e-mail at [log in to unmask]
-----Original Message-----
From: fullname [mailto:[log in to unmask]]
Sent: Monday, April 29, 2002 12:15 AM
To: [log in to unmask]
Subject: [TN] Looking for Happy Holden
I would like to have Happy Holden's contact especially email address.
Your reply would be appreciated.
Regards - Wee Mei
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Date: Mon, 29 Apr 2002 12:21:19 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Tempea, Ioan" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Tempea, Ioan" <[log in to unmask]>
Subject: Re: Flip-flop panels
MIME-Version: 1.0
Content-Type: text/plain
You are right Charlie, the board house must be involved.
Since my original purpose was to assess the feasability, I think I had my
answers.
The starting point that a manufacturing man like myself needed is there.
Thanks all,
Ioan
> -----Original Message-----
> From: Charlie McMahon [SMTP:[log in to unmask]]
> Sent: Monday, April 29, 2002 10:28 AM
> To: Tempea, Ioan
> Subject: Re: [TN] Flip-flop panels
>
> Joan:
>
> May I add to the discussion that you should not be flipping multi-layers.
> Primary reason is it only adds more cost in PCB fabrication due to lower
> yields caused by plating difficiencies.
> If you want to enhance productivity and increase your margin, consider
> co-operative engineering early on with your board supplier and assembler.
> As a board and assembly supplier myself, I have offered same to my clients
> and it can pay serious dividends in reducing problems increasing profit.
>
> I represent board shops in Canada that would be happy to assist you in
> this regard. It is, in my view, the superior strategy to implement.
> If you would, like I will provide contacts should you wish to investigate.
>
> Charlie McMahon
>
>
>
> Tempea, Ioan wrote:
>
>
> Now I got all mixed up.
>
> I'm mainly talking about multilayer boards. Basically small piggy
> backs, but
> MLBs still!
>
> Is it doable or not?
>
> And, of course, thanks for the input, Dennis, Jac, Robert and Eddie.
>
> Ioan
>
>
> -----Original Message-----
> From: Eddie Rocha [ SMTP:[log in to unmask]
> <mailto:SMTP:[log in to unmask]>]
> Sent: Wednesday, April 24, 2002 6:45 PM
> To: [log in to unmask] <mailto:[log in to unmask]>
> Subject: Re: [TN] Flip-flop panels
>
> Flip flopping multilayer bds can get complicated and is not
> recommended. It cannot be done if the layer stack-up is not
> symmetrical.
> thanks,
>
>
> --------------------------------------------------------------------------
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Date: Mon, 29 Apr 2002 09:21:19 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Frank Kimmey <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Frank Kimmey <[log in to unmask]>
Subject: Re: Flip-flop panels
X-To: "Tempea, Ioan" <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Hi Ioan,
It is doable.
You just have to make sure of a few things first.
1. Board stack-up is symmetrical
2. Step and repeat allows even number of images
(copper balancing)
3. Blind or buried vias add complexity (orders of magnitude)
4. KISS is best. The simpler the better.
I have requested flip image panels to reduce costs, warpage and
process times on many PCBs throughout the years. It works, but
you should spend a little more time in verification and probably
only use with simpler MLBs.
Hope this helped,
FNK
Frank N Kimmey, C.I.D.+
Senior PCB Designer
Powerwave Technologies
PH. 916-941-3159
Fax 916-941-3195
-----Original Message-----
From: Tempea, Ioan [mailto:[log in to unmask]]
Sent: Monday, April 29, 2002 6:40 AM
To: [log in to unmask]
Subject: Re: [TN] Flip-flop panels
Now I got all mixed up.
I'm mainly talking about multilayer boards. Basically small piggy backs, but
MLBs still!
Is it doable or not?
And, of course, thanks for the input, Dennis, Jac, Robert and Eddie.
Ioan
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Date: Mon, 29 Apr 2002 11:26:26 -0500
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: "Robert B. Denbo" <[log in to unmask]>
Subject: Re: Flip-flop panels
X-To: "Tempea, Ioan" <[log in to unmask]>
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
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Ioan:
As long as dielectric spacing and copper weights are symmetric around the
centerline of the panel it is doable.
Robert B. Denbo
Engineering Manager
Midwest Printed Circuit Services, Inc.
http://www.midwestpcb.com
mailto:[log in to unmask]
847.740.4120
847.740.4187 Fax
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Tempea, Ioan
Sent: Monday, April 29, 2002 8:40 AM
To: [log in to unmask]
Subject: Re: [TN] Flip-flop panels
Now I got all mixed up.
I'm mainly talking about multilayer boards. Basically small piggy backs, but
MLBs still!
Is it doable or not?
And, of course, thanks for the input, Dennis, Jac, Robert and Eddie.
Ioan
> -----Original Message-----
> From: Eddie Rocha [SMTP:[log in to unmask]]
> Sent: Wednesday, April 24, 2002 6:45 PM
> To: [log in to unmask]
> Subject: Re: [TN] Flip-flop panels
>
> Flip flopping multilayer bds can get complicated and is not
> recommended. It cannot be done if the layer stack-up is not
> symmetrical.
> thanks,
>
> --------------------------------------------------------------------------
> -------
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Date: Mon, 29 Apr 2002 10:25:59 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Dwight Mattix <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Dwight Mattix <[log in to unmask]>
Subject: Re: Via Plug
X-To: John Foster <[log in to unmask]>
In-Reply-To: <006901c1ebbd$f36abed0$550200c0@jfoster2>
Mime-Version: 1.0
Content-Type: text/plain; charset="us-ascii"; format=flowed
At 11:29 AM 4/24/2002 -0700, John Foster wrote:
>Thanks Jim
>
>Did you do this extra plating selectively. Or did you just overplate the
>whole PCB.
We have a lot of applications where we spec thermal vias to be selectively
plated to a minimum of 3 mils annular copper.
The fabricator drills the thermal vias and selectively plates to 2
mils. Then they drill and (plate the rest of the board to 1 mil (adding to
thermal via copper as well).
It's way more effective at heat transfer than any conductive epoxy we've
tried. This approach is also very effective at controlling solder wicking
to the bottom of the board -- we'll use it sometimes when we don't have a
thermal problem but just want to control solder flow into unplugged fields
of gnd vias (saves masking backside).
Dwight
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Date: Mon, 29 Apr 2002 13:28:19 -0400
Reply-To: [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Tom Moore <[log in to unmask]>
Subject: end joint width vs. side joint length
MIME-version: 1.0
Content-type: text/plain; charset=iso-8859-1
Content-transfer-encoding: 7BIT
We are a small, primarily captive, board assembly house that recently
brought our outsourced SMT assemblies in-house. We rely heavily on IPC
documentation in developing our acceptance criteria for Class 2 assemblies.
Have run into a problem with the idea of side joint length vs. end joint
width. Section 12.2.5.4 of 610C states that the minimum side joint length
is equal to the lead width or 75% of the lead length, whichever is less. I
would interpret this to mean that an acceptable solder joint does not
necessarily have to reach the toe of the component. However the preceding
section, end joint width-12.2.5.3, seems to indicate that not only does
solder need to contact the toe, it must also extend along 50% of the width
of the toe. Is there a conflict or am I not interpreting the spec correctly?
Thanks for your help.
Tom Moore
Quality Assurance Manager
Electro Plasma, Inc.
PH 419-255-5197
FAX 419-838-6745
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Date: Mon, 29 Apr 2002 11:48:59 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Mcmaster, Michael" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Mcmaster, Michael" <[log in to unmask]>
Subject: Re: Chemistry of discoloration?
X-To: Jana Carraway <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain
Oxidation, oxidation, oxidation!
I don't mean to oversimplify but that is predominately what is occurring.
I've seen samples where a strip of Kapton tape is placed on the board before
reflow. The section under the tape doesn't darken while the rest does.
> ----------
> From: Jana Carraway[SMTP:[log in to unmask]]
> Reply To: TechNet E-Mail Forum.;Jana Carraway
> Sent: Thursday, April 11, 2002 2:04 PM
> To: [log in to unmask]
> Subject: Re: [TN] Chemistry of discoloration?
>
> Rudy, you can even use "free radical initiation"! There must be some
> formulations folks out there who can divulge a bit more about the
> reactions
> without giving away formulation secrets! Dr. Roos, you out there???
>
> Thanks for the info Rudy,
> Jana Carraway
> MSEI
>
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Rudy Sedlak
> Sent: Thursday, April 11, 2002 12:11 PM
> To: [log in to unmask]
> Subject: Re: [TN] Chemistry of discoloration?
>
>
> Jana:
>
> You have asked a BIG question.
>
> There really is no known absolute answer.
>
> Organics tend to discolor, if they have any sort of reactivity left in
> them,
> and often, under the right circumstances even if they do not have any
> reactivity left in them.
>
> The general rule is they turn dark(er). The reactions are many, and
> clearly
> going to be dependent on the base material. Discoloration is driven by
> heat,
> and often exposure to sunlight.
>
> Not to get too technical, but polymers (laminate, and soldermask, for
> example) only rarely really react fully, and there is almost always some
> unreacted polymer (called monomer when it is totally unreacted, and
> oligomer
> when it is partially reacted) lurking in the matrix. When this contacts
> air,
> water, and heat and UV, all sorts of unexpected things happen. In fact,
> these very polymers often have added "preservatives" to prevent these
> post-polymerization reactions from occurring.
>
> The bottom line is (as if this really has ANY significanse in our
> industry)
> that this discoloration rarely affects the physical properties of the
> polymer. I think a great English playwright described this situation
> centuries ago..."Much ado about nothing"?
>
> Rudy Sedlak
> RD Chemical Company
>
> --------------------------------------------------------------------------
> --
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Date: Mon, 29 Apr 2002 15:18:00 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Marsico, James" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Marsico, James" <[log in to unmask]>
Subject: Re: Via Plug
X-To: Dwight Mattix <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Dwight, just out of curiosity, why not plate ALL of the vias with 3 mils of
copper. Wouldn't this be cheaper than drilling, plating, drilling and
plating again?
Jim Marsico
Senior Engineer
Production Engineering
EDO Electronics Systems Group
[log in to unmask] <mailto:[log in to unmask]>
631-595-5879
-----Original Message-----
From: Dwight Mattix [SMTP:[log in to unmask]]
Sent: Monday, April 29, 2002 1:26 PM
To: [log in to unmask]
Subject: Re: [TN] Via Plug
At 11:29 AM 4/24/2002 -0700, John Foster wrote:
>Thanks Jim
>
>Did you do this extra plating selectively. Or did you just
overplate the
>whole PCB.
We have a lot of applications where we spec thermal vias to be
selectively
plated to a minimum of 3 mils annular copper.
The fabricator drills the thermal vias and selectively plates to 2
mils. Then they drill and (plate the rest of the board to 1 mil
(adding to
thermal via copper as well).
It's way more effective at heat transfer than any conductive epoxy
we've
tried. This approach is also very effective at controlling solder
wicking
to the bottom of the board -- we'll use it sometimes when we don't
have a
thermal problem but just want to control solder flow into unplugged
fields
of gnd vias (saves masking backside).
Dwight
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Date: Mon, 29 Apr 2002 15:41:13 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Jim Keating <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Jim Keating <[log in to unmask]>
Subject: Re: Removal of Cured Nomenclature Ink
X-To: "Furrow, Robert Gordon (Bob)" <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit
Bob,
Sorry for the late response to this posting. If you haven't already reworked the boards might I suggest
laser removal. This will work for certain applications and we have had success multiple times. If
interested please cantact me via TechNet or at (603) 882-9944.
Regards
Jim Keating
"Furrow, Robert Gordon (Bob)" wrote:
> Hi TechNet,
>
> I have been asked what chemical(s) would be required to remove cured
> nomenclature ink (also known as silkscreen) from a bare board without
> damaging the board itself. I am assuming it is an epoxy ink, but I do not
> know the exact formulation. Any input is appreciated. I should know the
> exact formulation of the applied nomenclature ink tomorrow, but thought that
> maybe there is a generic answer.
>
> Thanks,
> Robert Furrow
> Printed Wiring Board Engineer
> Supply Chain Networks
> Lucent Technologies
> 978-960-3224 [log in to unmask]
>
> ---------------------------------------------------------------------------------
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> ---------------------------------------------------------------------------------
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Date: Mon, 29 Apr 2002 15:54:23 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Jack Crawford <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Jack Crawford <[log in to unmask]>
Subject: Proposed lifting of component date code restrictions
X-To: [log in to unmask]
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properly handle MIME multipart messages.
--=_2D70D107.40214376
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IPC has become aware that the National Electronics Distributors Association=
(NEDA) has posted a white paper discussing the proposed lifting of date =
code restrictions and they have requested comments from end users as well =
as component suppliers and distributors. The paper can be viewed at =
http://www.nedassoc.org/whitedat.html.
Comments can be provided to me on or off net; we'll compile them and =
forward to NEDA. If you comment to NEDA directly [log in to unmask], please =
cc: me on your reply [log in to unmask]
Cordially
Jack
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
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APEX 2003 - the industry's premier trade show in Electronics
Manufacturing, March 31-April 2, 2003, Anaheim, California.
More information on website www.goapex.org
--------
Jack Crawford, IPC Director of Assembly Standards and Technology
2215 Sanders Road, Northbrook IL 60062-6135
[log in to unmask]
847-790-5393
fax 847-504-2393
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<DIV><FONT size=3D1>IPC has become aware that t</FONT><FONT size=3D1>he =
National=20
Electronics Distributors Association (NEDA) has posted a white paper =
discussing=20
the proposed lifting of date code restrictions and they have requested =
comments=20
from end users as well as component suppliers and distributors. The paper =
can be=20
viewed at <A=20
href=3D"http://www.nedassoc.org/whitedat.html">http://www.nedassoc.org/whit=
edat.html</A>.</FONT></DIV>
<DIV> </DIV>
<DIV><FONT size=3D1>Comments can be provided to me on or off net; we'll =
compile=20
them and forward to NEDA. If you comment to NEDA directly <A=20
href=3D"mailto:[log in to unmask],">[log in to unmask],</A> please cc: =
me on=20
your reply <A=20
href=3D"mailto:[log in to unmask]">[log in to unmask]</A>.<BR></FONT></=
DIV>
<DIV><FONT size=3D1>Cordially</FONT></DIV>
<DIV><FONT size=3D1>Jack</FONT></DIV>
<DIV> </DIV>
<DIV><FONT size=3D1>=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
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>APEX 2003 - the=20
industry's premier trade show in Electronics<BR>Manufacturing, March =
31-April 2,=20
2003, Anaheim, California.<BR>More information on website <A=20
href=3D"http://www.goapex.org">www.goapex.org</A><BR>--------<BR>Jack =
Crawford,=20
IPC Director of Assembly Standards and Technology<BR>2215 Sanders Road,=20
Northbrook IL 60062-6135<BR><A=20
href=3D"mailto:[log in to unmask]">[log in to unmask]</A> <BR>847-790-5393<BR>fax=
=20
847-504-2393</DIV></FONT></BODY></HTML>
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Date: Mon, 29 Apr 2002 16:49:17 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Via Plug
Don't mean to but in, but what the hell. Just think how much surface copper
would be plated and how much resist would have to be applied and how much
plating overhang would be involved even with several resist layers applied,
etc..
MoonMan
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Date: Mon, 29 Apr 2002 19:05:47 EDT
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Proposed lifting of component date code restrictions
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I guess my first question is; If the datecodes currently mean different
things depending on the manufacturer, why not standardize what datecodes
really mean rather than get rid of them?
The paper talks about all the advances that have been made understanding root
causes concerning solderability issues, improved storage and handling
methods, etc., then why do I continue to get moisture sensitive components
from distributors in un-sealed packaging? But that's another issue...
A recent issue here at my facility underscores the importance of a datecode
on the part. We build an assembly for a customer that uses three 240-pin QFP
DSP's from a well known manufacturer. So far, we've built-up over 200
assemblies for our customer. We shipped the assemblies to our customer and
they integrated them into the higher level assembly, and discovered they
don't work...not communicating at all with the rest of the system.
Numerous phone calls to the manufacturer trying to find out what the problem
could be resulted in "Nothing has changed with the part, the die hasn't
changed, nothing..."
Funny thing was our first pre-production shipment of the assemblies worked
fine!!
After looking a little closer, the first lot of assemblies contained DSP's
that had a datecode that was 2000 or earlier, everything that's failing are
later...but still, according to the device manufacturer; "Nothing has
changed..."
If there wasn't a datecode on the part, we wouldn't know what we could put on
the assemblies and work. There is a lot of effort being expended to try and
isolate what the problem really is (with no help from the device supplier),
but for now we need to find parts that work so that it doesn't shut down
production, the only solid way (for now) is to find parts within a certain
date code.
Now I'm faced with the possible task of reworking 200 assemblies, each with
three 240-pin QFP's, with a early datecode part...fun stuff I know.
-Steve Gregory-
> IPC has become aware that the National Electronics Distributors Association
> (NEDA) has posted a white paper discussing the proposed lifting of date
> code restrictions and they have requested comments from end users as well
> as component suppliers and distributors. The paper can be viewed at <A HREF="http://www.nedassoc.org/whitedat.html">
> http://www.nedassoc.org/whitedat.html</A>.
>
> Comments can be provided to me on or off net; we'll compile them and
> forward to NEDA. If you comment to NEDA directly <A HREF="mailto:[log in to unmask],">[log in to unmask],</A> please
> cc: me on your reply <A HREF="mailto:[log in to unmask]">[log in to unmask]</A>.
>
> Cordially
> Jack
>
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<HTML><FONT FACE=arial,helvetica><FONT SIZE=2>I guess my first question is; If the datecodes currently mean different things depending on the manufacturer, why not standardize what datecodes really mean rather than get rid of them?<BR>
<BR>
The paper talks about all the advances that have been made understanding root causes concerning solderability issues, improved storage and handling methods, etc., then why do I continue to get moisture sensitive components from distributors in un-sealed packaging? But that's another issue...<BR>
<BR>
A recent issue here at my facility underscores the importance of a datecode on the part. We build an assembly for a customer that uses three 240-pin QFP DSP's from a well known manufacturer. So far, we've built-up over 200 assemblies for our customer. We shipped the assemblies to our customer and they integrated them into the higher level assembly, and discovered they don't work...not communicating at all with the rest of the system.<BR>
<BR>
Numerous phone calls to the manufacturer trying to find out what the problem could be resulted in "Nothing has changed with the part, the die hasn't changed, nothing..."<BR>
Funny thing was our first pre-production shipment of the assemblies worked fine!! <BR>
<BR>
After looking a little closer, the first lot of assemblies contained DSP's that had a datecode that was 2000 or earlier, everything that's failing are later...but still, according to the device manufacturer; "Nothing has changed..."<BR>
<BR>
If there wasn't a datecode on the part, we wouldn't know what we could put on the assemblies and work. There is a lot of effort being expended to try and isolate what the problem really is (with no help from the device supplier), but for now we need to find parts that work so that it doesn't shut down production, the only solid way (for now) is to find parts within a certain date code.<BR>
<BR>
Now I'm faced with the possible task of reworking 200 assemblies, each with three 240-pin QFP's, with a early datecode part...fun stuff I know.<BR>
<BR>
-Steve Gregory-<BR>
<BR>
<BR>
</FONT><FONT COLOR="#000000" style="BACKGROUND-COLOR: #ffffff" SIZE=1 FAMILY="SANSSERIF" FACE="Arial" LANG="0"><BLOCKQUOTE TYPE=CITE style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">IPC has become aware that the National Electronics Distributors Association (NEDA) has posted a white paper discussing the proposed lifting of date code restrictions and they have requested comments from end users as well as component suppliers and distributors. The paper can be viewed at <A HREF="http://www.nedassoc.org/whitedat.html">http://www.nedassoc.org/whitedat.html</A>.</FONT><FONT COLOR="#000000" style="BACKGROUND-COLOR: #ffffff" SIZE=3 FAMILY="SANSSERIF" FACE="Arial" LANG="0"><BR>
<BR>
</FONT><FONT COLOR="#000000" style="BACKGROUND-COLOR: #ffffff" SIZE=1 FAMILY="SANSSERIF" FACE="Arial" LANG="0">Comments can be provided to me on or off net; we'll compile them and forward to NEDA. If you comment to NEDA directly <A HREF="mailto:[log in to unmask],">[log in to unmask],</A> please cc: me on your reply <A HREF="mailto:[log in to unmask]">[log in to unmask]</A>.<BR>
</FONT><FONT COLOR="#000000" style="BACKGROUND-COLOR: #ffffff" SIZE=3 FAMILY="SANSSERIF" FACE="Arial" LANG="0"><BR>
</FONT><FONT COLOR="#000000" style="BACKGROUND-COLOR: #ffffff" SIZE=1 FAMILY="SANSSERIF" FACE="Arial" LANG="0">Cordially</FONT><FONT COLOR="#000000" style="BACKGROUND-COLOR: #ffffff" SIZE=3 FAMILY="SANSSERIF" FACE="Arial" LANG="0"><BR>
</FONT><FONT COLOR="#000000" style="BACKGROUND-COLOR: #ffffff" SIZE=1 FAMILY="SANSSERIF" FACE="Arial" LANG="0">Jack</FONT><FONT COLOR="#000000" style="BACKGROUND-COLOR: #ffffff" SIZE=3 FAMILY="SANSSERIF" FACE="Arial" LANG="0"><BR>
</BLOCKQUOTE><BR>
</FONT><FONT COLOR="#000000" style="BACKGROUND-COLOR: #ffffff" SIZE=2 FAMILY="SANSSERIF" FACE="Arial" LANG="0"><BR>
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Date: Tue, 30 Apr 2002 07:58:35 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
fullname <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: fullname <[log in to unmask]>
Organization: DSO National Laboratories
Subject: Re: Looking for Happy Holden
X-To: "Sauer, Steven T." <[log in to unmask]>
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Thank you so much for your help.
Regards - Wee Mei
"Sauer, Steven T." wrote:
> Good Morning Wee Mei,
> I took the following directly from a recent article in CircuiTree Magazine:
> Happy Holden is manager of advanced technologies for Westwood Associates
> (West Haven, CT). He is responsible for next-generation printed circuit
> manufacturing technologies, advanced design tools, and design consulting.
> Prior to joining Westwood, he was a consultant with TechLead Corporation,
> and had been at Hewlett-Packard for over 27 years. Holden formally managed
> Hewlett Packard's application organizations in the Far East and holds
> degrees in Chemical Engineering and Computer Science. If you have questions,
> he can be contacted via e-mail at [log in to unmask]
>
> -----Original Message-----
> From: fullname [mailto:[log in to unmask]]
> Sent: Monday, April 29, 2002 12:15 AM
> To: [log in to unmask]
> Subject: [TN] Looking for Happy Holden
>
> I would like to have Happy Holden's contact especially email address.
> Your reply would be appreciated.
>
> Regards - Wee Mei
>
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Date: Tue, 30 Apr 2002 08:00:32 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
fullname <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: fullname <[log in to unmask]>
Organization: DSO National Laboratories
Subject: Re: Looking for Happy Holden
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Thanks for the information, Moonman.
Regards - Wee Mei
Earl Moon wrote:
> Check over at the CircuiTree magazine forum. He's on all the time.
>
> Earl
>
> ----- Original Message -----
> From: "fullname" <[log in to unmask]>
> To: <[log in to unmask]>
> Sent: Monday, April 29, 2002 12:14 AM
> Subject: [TN] Looking for Happy Holden
>
> > I would like to have Happy Holden's contact especially email address.
> > Your reply would be appreciated.
> >
> > Regards - Wee Mei
> >
> > --------------------------------------------------------------------------
> -------
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Date: Mon, 29 Apr 2002 17:32:34 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
David Douthit <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: David Douthit <[log in to unmask]>
Subject: Re: Proposed lifting of component date code restrictions
X-To: Jack Crawford <[log in to unmask]>
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Jack,
I agree with Steve's comments. The divergence between the commercial
and high reliability electronics is a very serious issue.
Any proposal that effects configuration control must be carefully
weighed. Trying to save money no matter what the cost is a
very easy trap to step into.
Standardizing the date code process is needed.
Use of date codes is needed for "life time" buys of COTS when
obsolescence problems are present.
Configuration control issues can also cause problems with commercial
OEMs.
Unless tracking methods are in place part failures by lot would be
difficult to isolate in higher assemblies.
This could create a much larger recall condition.
Just some comments.
David A. Douthit
Manager
LoCan LLC
Jack Crawford wrote:
> IPC has become aware that the National Electronics Distributors
> Association (NEDA) has posted a white paper discussing the proposed
> lifting of date code restrictions and they have requested comments
> from end users as well as component suppliers and distributors. The
> paper can be viewed at http://www.nedassoc.org/whitedat.html. Comments
> can be provided to me on or off net; we'll compile them and forward to
> NEDA. If you comment to NEDA directly [log in to unmask], please cc: me
> on your reply
> [log in to unmask] ==========================================
>
> APEX 2003 - the industry's premier trade show in Electronics
> Manufacturing, March 31-April 2, 2003, Anaheim, California.
> More information on website www.goapex.org
> --------
> Jack Crawford, IPC Director of Assembly Standards and Technology
> 2215 Sanders Road, Northbrook IL 60062-6135
> [log in to unmask]
> 847-790-5393
> fax 847-504-2393
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Jack,
<p>I agree with Steve's comments. The divergence between the commercial
and high reliability electronics is a very serious issue.
<br>Any proposal that effects configuration control must be carefully weighed.
Trying to save money no matter what the cost is a
<br>very easy trap to step into.
<p>Standardizing the date code process is needed.
<br>Use of date codes is needed for "life time" buys of COTS when obsolescence
problems are present.
<p>Configuration control issues can also cause problems with commercial
OEMs.
<br>Unless tracking methods are in place part failures by lot would be
difficult to isolate in higher assemblies.
<br>This could create a much larger recall condition.
<p>Just some comments.
<p>David A. Douthit
<br>Manager
<br>LoCan LLC
<p>Jack Crawford wrote:
<blockquote TYPE=CITE> <font size=-2>IPC has become aware that the
National Electronics Distributors Association (NEDA) has posted a white
paper discussing the proposed lifting of date code restrictions and they
have requested comments from end users as well as component suppliers and
distributors. The paper can be viewed at <a href="http://www.nedassoc.org/whitedat.html">http://www.nedassoc.org/whitedat.html</a>.</font> <font size=-2>Comments
can be provided to me on or off net; we'll compile them and forward to
NEDA. If you comment to NEDA directly <a href="mailto:[log in to unmask],">[log in to unmask],</a>
please cc: me on your reply <a href="mailto:[log in to unmask]">[log in to unmask]</a>.</font><font size=-2>Cordially</font><font size=-2>Jack</font> <font size=-2>==========================================</font>
<br><font size=-2>APEX 2003 - the industry's premier trade show in Electronics</font>
<br><font size=-2>Manufacturing, March 31-April 2, 2003, Anaheim, California.</font>
<br><font size=-2>More information on website <a href="http://www.goapex.org">www.goapex.org</a></font>
<br><font size=-2>--------</font>
<br><font size=-2>Jack Crawford, IPC Director of Assembly Standards and
Technology</font>
<br><font size=-2>2215 Sanders Road, Northbrook IL 60062-6135</font>
<br><font size=-2><a href="mailto:[log in to unmask]">[log in to unmask]</a></font>
<br><font size=-2>847-790-5393</font>
<br><font size=-2>fax 847-504-2393</font></blockquote>
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Date: Tue, 30 Apr 2002 08:40:29 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Via Plug
X-To: Earl Moon <[log in to unmask]>
MIME-Version: 1.0
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I just did a calculation for some of our boards that use this via plug
material for enhancing thermal transfer between chips and thermal planes.
The calculation was to see by how much I would have to increase hole
plating thickness by in order to completely replace the epoxy in terms of
thermal conductivity.
I'm talking about a 24 mils diameter hole, plated initially to 1/2 oz
copper minimum and filled with epoxy. The board is 63 mils thick. Can you
guess what the increase is? ..... It's actually only 0.2 oz or 0.28 mils,
according to our thermal engineer. So why go to all the trouble and expense
of filling holes if the only purpose is thermal - a fairly small increase
in plating thickness is all that's needed.
Peter
Earl Moon <[log in to unmask]> 30/04/2002 05:49 AM
Sent by: TechNet <[log in to unmask]>
Please respond to "TechNet E-Mail Forum."; Please respond to Earl Moon
To: [log in to unmask]
cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST Aero/ST Group)
Subject: Re: [TN] Via Plug
Don't mean to but in, but what the hell. Just think how much surface copper
would be plated and how much resist would have to be applied and how much
plating overhang would be involved even with several resist layers applied,
etc..
MoonMan
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Date: Mon, 29 Apr 2002 19:53:45 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Praveen Kumar <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Praveen Kumar <[log in to unmask]>
Subject: Mechanical Strength of Solder Joints
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Hi All,
I am looking for a technical paper that details the mechanical strength of solder joints, BGAs in particular . In addition, are there any specifications in this regard?
I would really appreciate it if i could obtain a soft copy of the same.
Thanks and have a nice day.
Praveen
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Date: Tue, 30 Apr 2002 13:57:37 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
fullname <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: fullname <[log in to unmask]>
Organization: DSO National Laboratories
Subject: Re: Proposed lifting of component date code restrictions
X-To: [log in to unmask]
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--------------2D0D0406916B255643800C8C
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I agree with Steve strongly.
Without any date code, it is mission impossible to trace which batch of
the components failed.
Regards - Wee Mei
[log in to unmask] wrote:
> I guess my first question is; If the datecodes currently mean
> different things depending on the manufacturer, why not standardize
> what datecodes really mean rather than get rid of them?
>
> The paper talks about all the advances that have been made
> understanding root causes concerning solderability issues, improved
> storage and handling methods, etc., then why do I continue to get
> moisture sensitive components from distributors in un-sealed
> packaging? But that's another issue...
>
> A recent issue here at my facility underscores the importance of a
> datecode on the part. We build an assembly for a customer that uses
> three 240-pin QFP DSP's from a well known manufacturer. So far, we've
> built-up over 200 assemblies for our customer. We shipped the
> assemblies to our customer and they integrated them into the higher
> level assembly, and discovered they don't work...not communicating at
> all with the rest of the system.
>
> Numerous phone calls to the manufacturer trying to find out what the
> problem could be resulted in "Nothing has changed with the part, the
> die hasn't changed, nothing..."
> Funny thing was our first pre-production shipment of the assemblies
> worked fine!!
>
> After looking a little closer, the first lot of assemblies contained
> DSP's that had a datecode that was 2000 or earlier, everything that's
> failing are later...but still, according to the device manufacturer;
> "Nothing has changed..."
>
> If there wasn't a datecode on the part, we wouldn't know what we could
> put on the assemblies and work. There is a lot of effort being
> expended to try and isolate what the problem really is (with no help
> from the device supplier), but for now we need to find parts that work
> so that it doesn't shut down production, the only solid way (for now)
> is to find parts within a certain date code.
>
> Now I'm faced with the possible task of reworking 200 assemblies, each
> with three 240-pin QFP's, with a early datecode part...fun stuff I
> know.
>
> -Steve Gregory-
>
>
>
>> IPC has become aware that the National Electronics Distributors
>> Association (NEDA) has posted a white paper discussing the proposed
>> lifting of date code restrictions and they have requested comments
>> from end users as well as component suppliers and distributors. The
>> paper can be viewed at http://www.nedassoc.org/whitedat.html.
>>
>> Comments can be provided to me on or off net; we'll compile them and
>> forward to NEDA. If you comment to NEDA directly [log in to unmask],
>> please cc: me on your reply [log in to unmask]
>>
>> Cordially
>> Jack
>
>
>
--------------2D0D0406916B255643800C8C
Content-Type: text/html; charset=us-ascii
Content-Transfer-Encoding: 7bit
<!doctype html public "-//w3c//dtd html 4.0 transitional//en">
<html>
<font face="Arial,Helvetica"><font size=-1>I agree with Steve strongly.</font></font><font face="Arial,Helvetica"><font size=-1></font></font>
<p><font face="Arial,Helvetica"><font size=-1>Without any date code, it
is mission impossible to trace which batch of the components failed.</font></font><font face="Arial,Helvetica"><font size=-1></font></font>
<p><font face="Arial,Helvetica"><font size=-1>Regards - Wee Mei</font></font>
<p>[log in to unmask] wrote:
<blockquote TYPE=CITE><font face="arial,helvetica"><font size=-1>I guess
my first question is; If the datecodes currently mean different things
depending on the manufacturer, why not standardize what datecodes really
mean rather than get rid of them?</font></font>
<p><font face="arial,helvetica"><font size=-1>The paper talks about all
the advances that have been made understanding root causes concerning solderability
issues, improved storage and handling methods, etc., then why do I continue
to get moisture sensitive components from distributors in un-sealed packaging?
But that's another issue...</font></font>
<p><font face="arial,helvetica"><font size=-1>A recent issue here at my
facility underscores the importance of a datecode on the part. We build
an assembly for a customer that uses three 240-pin QFP DSP's from a well
known manufacturer. So far, we've built-up over 200 assemblies for our
customer. We shipped the assemblies to our customer and they integrated
them into the higher level assembly, and discovered they don't work...not
communicating at all with the rest of the system.</font></font>
<p><font face="arial,helvetica"><font size=-1>Numerous phone calls to the
manufacturer trying to find out what the problem could be resulted in "Nothing
has changed with the part, the die hasn't changed, nothing..."</font></font>
<br><font face="arial,helvetica"><font size=-1>Funny thing was our first
pre-production shipment of the assemblies worked fine!!</font></font>
<p><font face="arial,helvetica"><font size=-1>After looking a little closer,
the first lot of assemblies contained DSP's that had a datecode that was
2000 or earlier, everything that's failing are later...but still, according
to the device manufacturer; "Nothing has changed..."</font></font>
<p><font face="arial,helvetica"><font size=-1>If there wasn't a datecode
on the part, we wouldn't know what we could put on the assemblies and work.
There is a lot of effort being expended to try and isolate what the problem
really is (with no help from the device supplier), but for now we need
to find parts that work so that it doesn't shut down production, the only
solid way (for now) is to find parts within a certain date code.</font></font>
<p><font face="arial,helvetica"><font size=-1>Now I'm faced with the possible
task of reworking 200 assemblies, each with three 240-pin QFP's, with a
early datecode part...fun stuff I know.</font></font>
<p><font face="arial,helvetica"><font size=-1>-Steve Gregory-</font></font>
<br>
<br>
<blockquote TYPE=CITE style="BORDER-LEFT: #0000ff 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: 0px; PADDING-LEFT: 5px"><font face="Arial"><font color="#000000"><font size=-2>IPC
has become aware that the National Electronics Distributors Association
(NEDA) has posted a white paper discussing the proposed lifting of date
code restrictions and they have requested comments from end users as well
as component suppliers and distributors. The paper can be viewed at <a href="http://www.nedassoc.org/whitedat.html">http://www.nedassoc.org/whitedat.html</a>.</font></font></font>
<p><font face="Arial"><font color="#000000"><font size=-2>Comments can
be provided to me on or off net; we'll compile them and forward to NEDA.
If you comment to NEDA directly <a href="mailto:[log in to unmask],">[log in to unmask],</a>
please cc: me on your reply <a href="mailto:[log in to unmask]">[log in to unmask]</a>.</font></font></font>
<p><font face="Arial"><font color="#000000"><font size=-2>Cordially</font></font></font>
<br><font face="Arial"><font color="#000000"><font size=-2>Jack</font></font></font></blockquote>
<br> </blockquote>
</html>
--------------2D0D0406916B255643800C8C--
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Date: Tue, 30 Apr 2002 11:02:03 +0300
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Brian Ellis <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Brian Ellis <[log in to unmask]>
Subject: Re: Proposed lifting of component date code restrictions
X-To: Jack Crawford <[log in to unmask]>
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Jack
Although I'm not directly concerned, I read this paper and come to the
direct conclusion that the semiconductor industry are trying to weasel
out of their responsibilities.
"Twenty years ago, solderability problems were much more common than
today and certain metallurgical problems worsened over time, to the
extent that quality or reliability could have been compromised." These
guys are saying that the solderability of semiconductor packages - of
ALL types - will remain perfect: "The three year rule was adopted for
commercial procurement but is now irrelevant because of the
technological advances that the industry has made in the intervening
years.". I strongly dispute this assertion. It may be true that the
solderability of components has generally improved for fresh components
but it is not true that it will remain so for more than three years. Do
you know of any bare board fab shop that will guarantee the
solderability of all their products indefinitely?
The way I see this is that more emphasis will need to be placed on
goods-in testing of semiconductors for solderability and, perhaps, other
criteria, by the OEM, increasing his overheads, while the semiconductor
manufacturers rub their hands all the way to the bank, having weaseled
themselves out of their normal quality responsibilities.
On the other hand, I can see the difficulties that may be enegndered by
purchasers specifying dates. The easiest way of overcoming the problem,
IMHO, is for the semiconductor blokes to implement a substantial
surcharge on date-specific orders. This would have the double advantage
of encouraging assemblers not to specify dates except where they
consider it essential, for any reason, and it would cover the cost of
the extra hassle at the other end. Notwithstanding, I believe that if
the suppliers ship old packages, they should be prepared to cover the
extra cost to the assemblers if they do not meet full expectations of
quality, including solderability, cleanability, moisture absorption,
etc. This may also encourage them to ensure that very old inventory is
systematically replaced, because the cost of such guarantees would
probably exceed the value of most products.
Just some thoughts...
Best regards,
Brian
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Date: Tue, 30 Apr 2002 17:19:15 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
zhang shoukai <[log in to unmask]>
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Organization: huawei technologies
Subject: The effect to printing from pas vs soldermask height
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Date: Tue, 30 Apr 2002 17:26:35 +0800
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Re: Proposed lifting of component date code restrictions
X-To: David Douthit <[log in to unmask]>
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Steve and David,
The paper doe not propose doign away with date codes. As stated in the
paper, manufacturers will continue to put date codes on parts. What they
ARE trying to do away with is customers demanding components younger than a
certain date code in order to avoid solderability issues due to ageing. The
paper is trying to make the point that in today's mature industry,
solderability issues have been addressed with advances in manufacturing
technology, handling and storage procedures, so the need to specify date
codes as well when ordering parts is not necessary (or should not be
necessary, especially for commercial manufacture). Basically, it seems,
distributors are fed up with having to sort through their stock to select
parts with specifically required date codes, when, they say, all the other
date codes are just as good. The paper is an attempt to highlight the
unnecessary sugar this puts in the petrol that drives a slick supply
system.
Having strictly marked the comprehension test like a good teacher, I'll add
my 2 cents worth. I'm in the Aerospace sector, so the paper does not
strictly relate to my area of business. However, I have had enough
experience, as Steve has, of components from particular date code batches
going sour. If this is a general problem, then the distributors and
manufacturers should be aware and remove faulty batches from the supply
chain stock, but one can never tell. So there are circumstances where being
able to specify particular date codes that are, or are not, suitable is a
necessary option to a purchasing department.
Further, although most of the industry is mature, some of it is not. There
are still firms that do not have, or cannot/will not afford the expense of
putting in expensive handling and storage facilities and procedures. These
companies, it may be argued, should be the first to be put against the wall
when the revolution comes, but nevertheless they're out here. This is not
directly relevant to the paper, as the authors will take the stand that
improper handling and storage that gives rise to solderability issues is
not the problem of the OEM's/distributors. It will be up to the companies
to ensure their handling and storage complies with recommendations given.
The paper does include a number of assumptions about the industry that may
be overlooking genuine problems that could appear if the paper's proposal
is introduced.
I'm taking the paper's contents more as a plea for realism, rather than a
hard plan to ban the stating of date codes as a requirement. It does, after
all, mention get-out clauses, such as contractual requirements that are
placed on a purchaser to only buy parts of specific date codes, so I don't
see it as anything to get too excited about.
So many words for 2 cents - shows what they're probably worth, eh?
Peter
David Douthit <[log in to unmask]> 30/04/2002 08:32 AM
Sent by: TechNet <[log in to unmask]>
Please respond to "TechNet E-Mail Forum."; Please respond to David Douthit
To: [log in to unmask]
cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST Aero/ST Group)
Subject: Re: [TN] Proposed lifting of component date
code restrictions
Jack,
I agree with Steve's comments. The divergence between the commercial and
high reliability electronics is a very serious issue.
Any proposal that effects configuration control must be carefully weighed.
Trying to save money no matter what the cost is a
very easy trap to step into.
Standardizing the date code process is needed.
Use of date codes is needed for "life time" buys of COTS when obsolescence
problems are present.
Configuration control issues can also cause problems with commercial OEMs.
Unless tracking methods are in place part failures by lot would be
difficult to isolate in higher assemblies.
This could create a much larger recall condition.
Just some comments.
David A. Douthit
Manager
LoCan LLC
Jack Crawford wrote:
IPC has become aware that the National Electronics Distributors
Association (NEDA) has posted a white paper discussing the proposed
lifting of date code restrictions and they have requested comments
from end users as well as component suppliers and distributors. The
paper can be viewed at http://www.nedassoc.org/whitedat.html. Comments
can be provided to me on or off net; we'll compile them and forward to
NEDA. If you comment to NEDA directly [log in to unmask], please cc: me
on your reply [log in to unmask]
==========================================
APEX 2003 - the industry's premier trade show in Electronics
Manufacturing, March 31-April 2, 2003, Anaheim, California.
More information on website www.goapex.org
--------
Jack Crawford, IPC Director of Assembly Standards and Technology
2215 Sanders Road, Northbrook IL 60062-6135
[log in to unmask]
847-790-5393
fax 847-504-2393
[This e-mail is confidential and may also be privileged. If you are not the
intended recipient, please delete it and notify us immediately; you should
not copy or use it for any purpose, nor disclose its contents to any other
person. Thank you.]
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Date: Tue, 30 Apr 2002 06:44:01 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Proposed lifting of component date code restrictions
X-To: fullname <[log in to unmask]>
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Traceability went out the window with cots. Used to maintain =
traceability to the second metallization layer. If a pilot crashed, =
his/her remains seldom recoverable but components were at times.
Earl
By the way, if you're out on the great American highways and byways, =
you'll notice almost as many trucks/truckers/f------, etc. Hell, they =
get paid 50 cents a mile and make nearly 50K a year. Whoopie shit, where =
do I sign up - truckmasters I think it is.
----- Original Message -----=20
From: fullname=20
To: [log in to unmask]
Sent: Tuesday, April 30, 2002 1:57 AM
Subject: Re: [TN] Proposed lifting of component date code restrictions
I agree with Steve strongly.=20
Without any date code, it is mission impossible to trace which batch =
of the components failed.=20
Regards - Wee Mei=20
[log in to unmask] wrote:=20
I guess my first question is; If the datecodes currently mean =
different things depending on the manufacturer, why not standardize what =
datecodes really mean rather than get rid of them?=20
The paper talks about all the advances that have been made =
understanding root causes concerning solderability issues, improved =
storage and handling methods, etc., then why do I continue to get =
moisture sensitive components from distributors in un-sealed packaging? =
But that's another issue...=20
A recent issue here at my facility underscores the importance of a =
datecode on the part. We build an assembly for a customer that uses =
three 240-pin QFP DSP's from a well known manufacturer. So far, we've =
built-up over 200 assemblies for our customer. We shipped the assemblies =
to our customer and they integrated them into the higher level assembly, =
and discovered they don't work...not communicating at all with the rest =
of the system.=20
Numerous phone calls to the manufacturer trying to find out what the =
problem could be resulted in "Nothing has changed with the part, the die =
hasn't changed, nothing..."=20
Funny thing was our first pre-production shipment of the assemblies =
worked fine!!=20
After looking a little closer, the first lot of assemblies contained =
DSP's that had a datecode that was 2000 or earlier, everything that's =
failing are later...but still, according to the device manufacturer; =
"Nothing has changed..."=20
If there wasn't a datecode on the part, we wouldn't know what we =
could put on the assemblies and work. There is a lot of effort being =
expended to try and isolate what the problem really is (with no help =
from the device supplier), but for now we need to find parts that work =
so that it doesn't shut down production, the only solid way (for now) is =
to find parts within a certain date code.=20
Now I'm faced with the possible task of reworking 200 assemblies, =
each with three 240-pin QFP's, with a early datecode part...fun stuff I =
know.=20
-Steve Gregory-=20
=20
=20
IPC has become aware that the National Electronics Distributors =
Association (NEDA) has posted a white paper discussing the proposed =
lifting of date code restrictions and they have requested comments from =
end users as well as component suppliers and distributors. The paper can =
be viewed at http://www.nedassoc.org/whitedat.html.=20
Comments can be provided to me on or off net; we'll compile them =
and forward to NEDA. If you comment to NEDA directly [log in to unmask], =
please cc: me on your reply [log in to unmask]
Cordially=20
Jack
=20
------=_NextPart_000_0046_01C1F012.69EC0E80
Content-Type: text/html;
charset="iso-8859-1"
Content-Transfer-Encoding: quoted-printable
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META http-equiv=3DContent-Type content=3D"text/html; =
charset=3Diso-8859-1">
<META content=3D"MSHTML 6.00.2715.400" name=3DGENERATOR>
<STYLE></STYLE>
</HEAD>
<BODY bgColor=3D#ffffff>
<DIV><FONT face=3DArial size=3D2>Traceability went out the window with =
cots. Used to=20
maintain traceability to the second metallization layer. If a pilot =
crashed,=20
his/her remains seldom recoverable but components were at =
times.</FONT></DIV>
<DIV><FONT face=3DArial size=3D2></FONT> </DIV>
<DIV><FONT face=3DArial size=3D2>Earl</FONT></DIV>
<DIV><FONT face=3DArial size=3D2></FONT> </DIV>
<DIV><FONT face=3DArial size=3D2>By the way, if you're out on the great =
American=20
highways and byways, you'll notice almost as many =
trucks/truckers/f------, etc.=20
Hell, they get paid 50 cents a mile and make nearly 50K a year. Whoopie =
shit,=20
where do I sign up - truckmasters I think it is.</FONT></DIV>
<BLOCKQUOTE dir=3Dltr=20
style=3D"PADDING-RIGHT: 0px; PADDING-LEFT: 5px; MARGIN-LEFT: 5px; =
BORDER-LEFT: #000000 2px solid; MARGIN-RIGHT: 0px">
<DIV style=3D"FONT: 10pt arial">----- Original Message ----- </DIV>
<DIV=20
style=3D"BACKGROUND: #e4e4e4; FONT: 10pt arial; font-color: =
black"><B>From:</B>=20
<A [log in to unmask] =
href=3D"mailto:[log in to unmask]">fullname</A>=20
</DIV>
<DIV style=3D"FONT: 10pt arial"><B>To:</B> <A [log in to unmask]
href=3D"mailto:[log in to unmask]">[log in to unmask]</A> </DIV>
<DIV style=3D"FONT: 10pt arial"><B>Sent:</B> Tuesday, April 30, 2002 =
1:57=20
AM</DIV>
<DIV style=3D"FONT: 10pt arial"><B>Subject:</B> Re: [TN] Proposed =
lifting of=20
component date code restrictions</DIV>
<DIV><BR></DIV><FONT face=3DArial,Helvetica><FONT size=3D-1>I agree =
with Steve=20
strongly.</FONT></FONT><FONT face=3DArial,Helvetica><FONT =
size=3D-1></FONT></FONT>=20
<P><FONT face=3DArial,Helvetica><FONT size=3D-1>Without any date code, =
it is=20
mission impossible to trace which batch of the components=20
failed.</FONT></FONT><FONT face=3DArial,Helvetica><FONT =
size=3D-1></FONT></FONT>=20
<P><FONT face=3DArial,Helvetica><FONT size=3D-1>Regards - Wee =
Mei</FONT></FONT>=20
<P><A href=3D"mailto:[log in to unmask]">[log in to unmask]</A> wrote:=20
<BLOCKQUOTE TYPE=3D"CITE"><FONT face=3Darial,helvetica><FONT =
size=3D-1>I guess my=20
first question is; If the datecodes currently mean different things=20
depending on the manufacturer, why not standardize what datecodes =
really=20
mean rather than get rid of them?</FONT></FONT>=20
<P><FONT face=3Darial,helvetica><FONT size=3D-1>The paper talks =
about all the=20
advances that have been made understanding root causes concerning=20
solderability issues, improved storage and handling methods, etc., =
then why=20
do I continue to get moisture sensitive components from distributors =
in=20
un-sealed packaging? But that's another issue...</FONT></FONT>=20
<P><FONT face=3Darial,helvetica><FONT size=3D-1>A recent issue here =
at my=20
facility underscores the importance of a datecode on the part. We =
build an=20
assembly for a customer that uses three 240-pin QFP DSP's from a =
well known=20
manufacturer. So far, we've built-up over 200 assemblies for our =
customer.=20
We shipped the assemblies to our customer and they integrated them =
into the=20
higher level assembly, and discovered they don't work...not =
communicating at=20
all with the rest of the system.</FONT></FONT>=20
<P><FONT face=3Darial,helvetica><FONT size=3D-1>Numerous phone calls =
to the=20
manufacturer trying to find out what the problem could be resulted =
in=20
"Nothing has changed with the part, the die hasn't changed,=20
nothing..."</FONT></FONT> <BR><FONT face=3Darial,helvetica><FONT =
size=3D-1>Funny=20
thing was our first pre-production shipment of the assemblies worked =
fine!!</FONT></FONT>=20
<P><FONT face=3Darial,helvetica><FONT size=3D-1>After looking a =
little closer,=20
the first lot of assemblies contained DSP's that had a datecode that =
was=20
2000 or earlier, everything that's failing are later...but still, =
according=20
to the device manufacturer; "Nothing has changed..."</FONT></FONT>=20
<P><FONT face=3Darial,helvetica><FONT size=3D-1>If there wasn't a =
datecode on=20
the part, we wouldn't know what we could put on the assemblies and =
work.=20
There is a lot of effort being expended to try and isolate what the =
problem=20
really is (with no help from the device supplier), but for now we =
need to=20
find parts that work so that it doesn't shut down production, the =
only solid=20
way (for now) is to find parts within a certain date =
code.</FONT></FONT>=20
<P><FONT face=3Darial,helvetica><FONT size=3D-1>Now I'm faced with =
the possible=20
task of reworking 200 assemblies, each with three 240-pin QFP's, =
with a=20
early datecode part...fun stuff I know.</FONT></FONT>=20
<P><FONT face=3Darial,helvetica><FONT size=3D-1>-Steve =
Gregory-</FONT></FONT>=20
<BR> <BR> =20
<BLOCKQUOTE=20
style=3D"PADDING-LEFT: 5px; MARGIN-LEFT: 5px; BORDER-LEFT: #0000ff =
2px solid; MARGIN-RIGHT: 0px"=20
TYPE=3D"CITE"><FONT face=3DArial><FONT color=3D#000000><FONT =
size=3D-2>IPC has=20
become aware that the National Electronics Distributors =
Association (NEDA)=20
has posted a white paper discussing the proposed lifting of date =
code=20
restrictions and they have requested comments from end users as =
well as=20
component suppliers and distributors. The paper can be viewed at =
<A=20
=
href=3D"http://www.nedassoc.org/whitedat.html">http://www.nedassoc.org/wh=
itedat.html</A>.</FONT></FONT></FONT>=20
<P><FONT face=3DArial><FONT color=3D#000000><FONT =
size=3D-2>Comments can be=20
provided to me on or off net; we'll compile them and forward to =
NEDA. If=20
you comment to NEDA directly <A=20
href=3D"mailto:[log in to unmask],">[log in to unmask],</A> please =
cc: me on=20
your reply <A=20
=
href=3D"mailto:[log in to unmask]">[log in to unmask]</A>.</FONT></FO=
NT></FONT>=20
<P><FONT face=3DArial><FONT color=3D#000000><FONT=20
size=3D-2>Cordially</FONT></FONT></FONT> <BR><FONT =
face=3DArial><FONT=20
color=3D#000000><FONT=20
=
size=3D-2>Jack</FONT></FONT></FONT></P></BLOCKQUOTE><BR> </BLOCKQUOT=
E></BLOCKQUOTE></BODY></HTML>
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Date: Tue, 30 Apr 2002 05:57:17 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Proposed lifting of component date code restrictions
Pardon my ettiquiteee. This post should not have happened. I keep forgetting
I can reply from my outlook thing.
MoonMan
Actually, the first part about costs should apply, not the truck driving
stuff though I'll see you, little girl in your bright red convertible, down
the road soon if the economy gets worse.
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Date: Tue, 30 Apr 2002 05:58:58 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: The effect to printing from pas vs soldermask height
X-To: [log in to unmask]
Never had a problem with thousands of OSP/OCC boards non solder mask defined.
MoonMan
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Date: Tue, 30 Apr 2002 06:01:46 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Via Plug
X-To: [log in to unmask]
Peter,
As you say, no big change. Always used holes, especially on board edges say
1/4" wide copper strips, as heat pipes for convection and conduction to a
cold wall. Also used mounting "studs" elsewhere when castings used so heat
could be conducted to the casting from various hot areas in various board
locations.
Earl
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Date: Tue, 30 Apr 2002 06:13:17 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Bloomquist, Ken" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Bloomquist, Ken" <[log in to unmask]>
Subject: Re: Proposed lifting of component date code restrictions
MIME-Version: 1.0
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I wonder how long it would take the component manufacturers to start marking
date codes again if a problem was found within a part and they either had to
test everything they had to sort out the problem and throw everything away
and start over? I agree that having the suppliers sort for date codes
because of assumed solderability problems is a problem but there really
needs to be a date code.
KennyB
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<DIV><FONT color=#0000ff face=Arial size=2><SPAN class=889570813-30042002>I
wonder how long it would take the component manufacturers to start marking date
codes again if a problem was found within a part and they either had to test
everything they had to sort out the problem and throw everything away and start
over? I agree that having the suppliers sort for date codes because of
assumed solderability problems is a problem but there really needs to be a date
code.</SPAN></FONT></DIV>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN
class=889570813-30042002></SPAN></FONT> </DIV>
<DIV><FONT color=#0000ff face=Arial size=2><SPAN
class=889570813-30042002>KennyB</SPAN></FONT></DIV></BODY></HTML>
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Date: Tue, 30 Apr 2002 08:45:18 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Kathy Kuhlow <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Kathy Kuhlow <[log in to unmask]>
Subject: Re: Proposed lifting of component date code restrictions
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There are many instances in everyone's career where we sorted by or found =
problems with date codes. Many times that was the only sort criteria. =
Just got bit again from a broker for a very old part, just finished our =
450 PC rework. =20
It also makes me very concerned having been in serious medical device =
assembly. Now the proposal would allow what ever date code out and lose =
that traceability for the next generation of pacemakers and various other =
life support systems or military applications like a shuttle. The =
manufacturer's may know more about handling, processing, etc but the =
distributors don't know nor do the brokers. =20
Not one manufacturer out there is always providing 100% quality, there are =
problems. The only thing that can make this a possibility in my mind =
would be if the manufacturers are going to support all parts when an issue =
comes up and the financial burden to remove all from inventory instead of =
a specific batch. =20
Don't let them lose the date code that we all have come to depend on.
Kathy =20
--=_207DDF1A.7C1D70F4
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<BODY style="MARGIN-TOP: 2px; FONT: 10pt MS Sans Serif; MARGIN-LEFT: 2px">
<DIV>There are many instances in everyone's career where we sorted by or found
problems with date codes. Many times that was the only sort
criteria. Just got bit again from a broker for a very old part, just
finished our 450 PC rework. </DIV>
<DIV> </DIV>
<DIV>It also makes me very concerned having been in serious medical device
assembly. Now the proposal would allow what ever date code out and lose
that traceability for the next generation of pacemakers and various other life
support systems or military applications like a shuttle. The
manufacturer's may know more about handling, processing, etc but the
distributors don't know nor do the brokers. </DIV>
<DIV> </DIV>
<DIV>Not one manufacturer out there is always providing 100% quality, there are
problems. The only thing that can make this a possibility in my mind would
be if the manufacturers are going to support all parts when an issue comes up
and the financial burden to remove all from inventory instead of a specific
batch. </DIV>
<DIV> </DIV>
<DIV>Don't let them lose the date code that we all have come to depend on.</DIV>
<DIV> </DIV>
<DIV>Kathy </DIV></BODY></HTML>
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Date: Tue, 30 Apr 2002 07:34:32 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Crepeau, Phil" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Crepeau, Phil" <[log in to unmask]>
Subject: Re: Proposed lifting of component date code restrictions
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hi,
why doesn't neda encourage their members to offer two levels of pricing... one for orders that include date code requirements and one for orders that don't? the distributors can present the risks/benefits to their customers. i guess i'm too jaded to think that the distributors have anyone's interest at heart other than theirs. i suppose that eventually we will be told that it will be in our interest to eliminate date code requirements altogether.
phil
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<DIV><FONT face=Arial color=#0000ff size=2><SPAN
class=510362814-30042002>hi,</SPAN></FONT></DIV>
<DIV><FONT face=Arial color=#0000ff size=2><SPAN
class=510362814-30042002></SPAN></FONT> </DIV>
<DIV><FONT face=Arial color=#0000ff size=2><SPAN class=510362814-30042002>why
doesn't neda encourage their members to offer two levels of pricing... one for
orders that include date code requirements and one for orders that don't?
the distributors can present the risks/benefits to their customers. i
guess i'm too jaded to think that the distributors have anyone's interest at
heart other than theirs. i suppose that eventually we will be told that it
will be in our interest to eliminate date code requirements
altogether.</SPAN></FONT></DIV>
<DIV><FONT face=Arial color=#0000ff size=2><SPAN
class=510362814-30042002></SPAN></FONT> </DIV>
<DIV><FONT face=Arial color=#0000ff size=2><SPAN
class=510362814-30042002>phil</SPAN></FONT><FONT face=arial,helvetica><FONT
lang=0 style="BACKGROUND-COLOR: #ffffff" face=Arial color=#000000 size=2
FAMILY="SANSSERIF"><BR></DIV></FONT></FONT></BODY></HTML>
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Date: Tue, 30 Apr 2002 11:42:03 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
bbarr <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: bbarr <[log in to unmask]>
Subject: Re: Proposed lifting of component date code restrictions
X-To: Jack Crawford <[log in to unmask]>
In-Reply-To: <[log in to unmask]>
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Please everyone, before there is mass hysteria, go back and reread the
paper. Nobody is proposing doing away with date codes! Just the practice of
ordering specific date codes unless there is a good reason for it.
Bob
=======================
Robert Barr
Manufacturing Engineering
Formation, Inc.
Voice: 856-234-5020 x3035
Fax: 856-234-6679
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Jack Crawford
Sent: Monday, April 29, 2002 4:54 PM
To: [log in to unmask]
Subject: [TN] Proposed lifting of component date code restrictions
IPC has become aware that the National Electronics Distributors
Association (NEDA) has posted a white paper discussing the proposed lifting
of date code restrictions and they have requested comments from end users as
well as component suppliers and distributors. The paper can be viewed at
http://www.nedassoc.org/whitedat.html.
Comments can be provided to me on or off net; we'll compile them and
forward to NEDA. If you comment to NEDA directly [log in to unmask], please
cc: me on your reply [log in to unmask]
Cordially
Jack
==========================================
APEX 2003 - the industry's premier trade show in Electronics
Manufacturing, March 31-April 2, 2003, Anaheim, California.
More information on website www.goapex.org
--------
Jack Crawford, IPC Director of Assembly Standards and Technology
2215 Sanders Road, Northbrook IL 60062-6135
[log in to unmask]
847-790-5393
fax 847-504-2393
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<META content=3D"MSHTML 6.00.2600.0" name=3DGENERATOR></HEAD>
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<DIV><SPAN class=3D420073915-30042002><FONT face=3DArial size=3D2>Please =
everyone,=20
before there is mass hysteria, go back and reread the paper. Nobody is =
proposing=20
doing away with date codes! Just the practice of ordering specific date =
codes=20
unless there is a good reason for it.</FONT></SPAN></DIV>
<DIV> </DIV>
<P><FONT =
size=3D2>Bob<BR><BR>=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D<BR>Robert=20
Barr<BR>Manufacturing Engineering<BR>Formation, Inc.<BR>Voice: =
856-234-5020=20
x3035<BR>Fax: 856-234-6679 </FONT></P>
<BLOCKQUOTE dir=3Dltr=20
style=3D"PADDING-LEFT: 5px; MARGIN-LEFT: 5px; BORDER-LEFT: #000000 2px =
solid; MARGIN-RIGHT: 0px">
<DIV class=3DOutlookMessageHeader dir=3Dltr align=3Dleft><FONT =
face=3DTahoma=20
size=3D2>-----Original Message-----<BR><B>From:</B> TechNet=20
[mailto:[log in to unmask]]<B>On Behalf Of </B>Jack =
Crawford<BR><B>Sent:</B>=20
Monday, April 29, 2002 4:54 PM<BR><B>To:</B>=20
[log in to unmask]<BR><B>Subject:</B> [TN] Proposed lifting of component =
date=20
code restrictions<BR><BR></FONT></DIV>
<DIV><FONT size=3D1>IPC has become aware that t</FONT><FONT =
size=3D1>he National=20
Electronics Distributors Association (NEDA) has posted a white paper=20
discussing the proposed lifting of date code restrictions and they =
have=20
requested comments from end users as well as component suppliers and=20
distributors. The paper can be viewed at <A=20
=
href=3D"http://www.nedassoc.org/whitedat.html">http://www.nedassoc.org/wh=
itedat.html</A>.</FONT></DIV>
<DIV> </DIV>
<DIV><FONT size=3D1>Comments can be provided to me on or off net; =
we'll compile=20
them and forward to NEDA. If you comment to NEDA directly <A=20
href=3D"mailto:[log in to unmask],">[log in to unmask],</A> please =
cc: me on=20
your reply <A=20
=
href=3D"mailto:[log in to unmask]">[log in to unmask]</A>.<BR></FONT>=
</DIV>
<DIV><FONT size=3D1>Cordially</FONT></DIV>
<DIV><FONT size=3D1>Jack</FONT></DIV>
<DIV> </DIV>
<DIV><FONT =
size=3D1>=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D<BR>APEX =
2003 -=20
the industry's premier trade show in Electronics<BR>Manufacturing, =
March=20
31-April 2, 2003, Anaheim, California.<BR>More information on website =
<A=20
href=3D"http://www.goapex.org">www.goapex.org</A><BR>--------<BR>Jack =
Crawford,=20
IPC Director of Assembly Standards and Technology<BR>2215 Sanders =
Road,=20
Northbrook IL 60062-6135<BR><A=20
href=3D"mailto:[log in to unmask]">[log in to unmask]</A> =
<BR>847-790-5393<BR>fax=20
847-504-2393</DIV></BLOCKQUOTE></FONT></BODY></HTML>
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Date: Tue, 30 Apr 2002 11:03:44 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Mel Parrish <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Mel Parrish <[log in to unmask]>
Subject: Re: Proposed lifting of component date code restrictions
X-To: Kathy Kuhlow <[log in to unmask]>
In-Reply-To: <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="US-ASCII"
Content-Transfer-Encoding: 7bit
Just for grins, how many have run into variation in component materials and
processes such as a different die source, adhesives, process profiles, cure,
etc. within a specific date code?
Scary, isn't it.
Mel Parrish
Soldering Technology International
102 Tribble Drive
Madison, AL 35758
256 705 5530
256 705 5538 Fax
[log in to unmask]
www.solderingtech.com
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Kathy Kuhlow
Sent: Tuesday, April 30, 2002 8:45 AM
To: [log in to unmask]
Subject: Re: [TN] Proposed lifting of component date code restrictions
There are many instances in everyone's career where we sorted by or found
problems with date codes. Many times that was the only sort criteria. Just
got bit again from a broker for a very old part, just finished our 450 PC
rework.
It also makes me very concerned having been in serious medical device
assembly. Now the proposal would allow what ever date code out and lose
that traceability for the next generation of pacemakers and various other
life support systems or military applications like a shuttle. The
manufacturer's may know more about handling, processing, etc but the
distributors don't know nor do the brokers.
Not one manufacturer out there is always providing 100% quality, there are
problems. The only thing that can make this a possibility in my mind would
be if the manufacturers are going to support all parts when an issue comes
up and the financial burden to remove all from inventory instead of a
specific batch.
Don't let them lose the date code that we all have come to depend on.
Kathy
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Date: Tue, 30 Apr 2002 11:05:54 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Jack Crawford <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Jack Crawford <[log in to unmask]>
Subject: TPCA Show 2002 and Forum
X-To: [log in to unmask], [log in to unmask]
X-cc: David Bergman <[log in to unmask]>,
Mary Tunk <[log in to unmask]>
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The following message is posted at the request of David Bergman, IPC VP =
Standards, Technology and International Relations. IPC is secretariate for =
World Electronics Circuit Council (WECC). More info on IPC website, =
search on WECC; here are a couple of shortcuts http://www.ipc.org/html/june=
99edit.htm and http://www.ipc.org/html/apr00edit.htm=20
Please contact Mary Tunk to receive the call for papers (attachments are =
stripped off the forum msgs) and let me know if you have questions.
Cordially
Jack
#############
Dear Colleagues,
Subject: WECC Member Booth Stand in WECC Corner at TPCA Show 2002
We are going to have TPCA Show 2002 at Taipei World Trade Center (TWTC) =
Exhibition Hall 1 and 2 from Oct 31. to Nov. 2, 2002. We warmly invite =
you all the WECC member associations to the third TPCA Show this year. =
Also, I would like to know if your association wishes to have a booth =
stand at TPCA Show 2002 in the WECC corner. If your association would =
like to have more booth, or wishes to have a new space, please let me know =
as soon as possible. [log in to unmask]
Besides, please see the call for paper of TPCA Show 2002 Forum and help us =
to forward that to your members.
Thanks for your kind attention. We are looking forward to seeing you in =
TPCA Show Taipei.
Best regards,
Kevin Wang
TPCA
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Date: Tue, 30 Apr 2002 11:27:07 -0500
Reply-To: "[log in to unmask]" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Kari Rambo <[log in to unmask]>
Organization: Altron Inc
Subject: Re: Proposed lifting of component date code restrictions
MIME-Version: 1.0
Content-Type: text/plain; charset="us-ascii"
Content-Transfer-Encoding: 7bit
The paper is not suggesting that date codes be eliminated; only that
restrictions not be put on components with respect to date codes. For
example, many companies have policies stating if the date code indicates
components are more than a year old, the component must be rejected. The
white paper suggests that because of the advances in manufacturing and
storing the components, they don't "get old" anymore, and that the date
code doesn't really indicate the age of the component anyway (since the
coding is not standardized). For these reasons, it is suggested that date
code restrictions should not be placed on components.
I don't believe the paper is implying that traceability could also be
eliminated.
(If it is, they're nuts).
kjr
-----Original Message-----
From: Bloomquist, Ken [SMTP:[log in to unmask]]
Sent: Tuesday, April 30, 2002 8:13 AM
To: [log in to unmask]
Subject: Re: [TN] Proposed lifting of component date code restrictions
I wonder how long it would take the component manufacturers to start
marking
date codes again if a problem was found within a part and they either had
to
test everything they had to sort out the problem and throw everything away
and start over? I agree that having the suppliers sort for date codes
because of assumed solderability problems is a problem but there really
needs to be a date code.
KennyB
<< File: ATT00007.html >>
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Date: Tue, 30 Apr 2002 11:46:49 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
[log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Dave Hillman <[log in to unmask]>
Subject: Re: Proposed lifting of component date code restrictions
X-To: [log in to unmask]
MIME-Version: 1.0
Content-type: text/plain; charset="us-ascii"
Hi Jack! Just a comment echoing the TechNet chorus - a component date code
is a tracking number which serves a multitude of purposes of which
solderability aspects are just one specific issue. I am also quite
skeptical of the white paper viewpoint of solderability being a "well
understood" and "controlled" topic - if that were the case then why are
there so many participants in the JSTD-002 committee involving the IPC,
EIA, and JEDEC associations? Heavens knows I would like to work on other
issues than solderability but I believe the white paper is offering a very,
very skewed viewpoint of solderability issues within the electronic
assembly industry.
Dave Hillman
JSTD 002A CoChairman
[log in to unmask]
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Date: Tue, 30 Apr 2002 13:11:54 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Guy Ramsey <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Guy Ramsey <[log in to unmask]>
Subject: Re: Proposed lifting of component date code restrictions
X-To: bbarr <[log in to unmask]>
In-Reply-To: <[log in to unmask]>
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The proposal would relieve semi-conductor manufactures and distrubutors from
keeping track of date codes once they were "in the supply chain". This
would make it more difficult and expensive to get semiconductors
manufactured before or after a specific date for any reason . . . I can
think of many.
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of bbarr
Sent: Tuesday, April 30, 2002 11:42 AM
To: [log in to unmask]
Subject: Re: [TN] Proposed lifting of component date code restrictions
Please everyone, before there is mass hysteria, go back and reread the
paper. Nobody is proposing doing away with date codes! Just the practice of
ordering specific date codes unless there is a good reason for it.
Bob
=======================
Robert Barr
Manufacturing Engineering
Formation, Inc.
Voice: 856-234-5020 x3035
Fax: 856-234-6679
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Jack Crawford
Sent: Monday, April 29, 2002 4:54 PM
To: [log in to unmask]
Subject: [TN] Proposed lifting of component date code restrictions
IPC has become aware that the National Electronics Distributors
Association (NEDA) has posted a white paper discussing the proposed lifting
of date code restrictions and they have requested comments from end users as
well as component suppliers and distributors. The paper can be viewed at
http://www.nedassoc.org/whitedat.html.
Comments can be provided to me on or off net; we'll compile them and
forward to NEDA. If you comment to NEDA directly [log in to unmask], please
cc: me on your reply [log in to unmask]
Cordially
Jack
==========================================
APEX 2003 - the industry's premier trade show in Electronics
Manufacturing, March 31-April 2, 2003, Anaheim, California.
More information on website www.goapex.org
--------
Jack Crawford, IPC Director of Assembly Standards and Technology
2215 Sanders Road, Northbrook IL 60062-6135
[log in to unmask]
847-790-5393
fax 847-504-2393
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<META content=3D"text/html; charset=3Dwindows-1252" =
http-equiv=3DContent-Type>
<META content=3D"MSHTML 5.00.3105.105" name=3DGENERATOR></HEAD>
<BODY style=3D"FONT: 8pt MS Sans Serif; MARGIN-LEFT: 2px; MARGIN-TOP: =
2px">
<DIV><FONT size=3D1><SPAN class=3D203100117-30042002>The proposal would =
relieve=20
semi-conductor manufactures and distrubutors from keeping track of date =
codes=20
once they were "in the supply chain". This would make it more =
difficult=20
and expensive to get semiconductors manufactured before or after a =
specific date=20
for any reason . . . I can think of many. </SPAN></FONT></DIV>
<BLOCKQUOTE dir=3Dltr=20
style=3D"BORDER-LEFT: #000000 2px solid; MARGIN-LEFT: 5px; MARGIN-RIGHT: =
0px; PADDING-LEFT: 5px">
<DIV class=3DOutlookMessageHeader><FONT face=3D"Times New Roman"=20
size=3D2>-----Original Message-----<BR><B>From:</B> TechNet=20
[mailto:[log in to unmask]]<B>On Behalf Of</B> bbarr<BR><B>Sent:</B> =
Tuesday,=20
April 30, 2002 11:42 AM<BR><B>To:</B> =
[log in to unmask]<BR><B>Subject:</B> Re:=20
[TN] Proposed lifting of component date code =
restrictions<BR><BR></DIV></FONT>
<DIV><SPAN class=3D420073915-30042002><FONT face=3DArial =
size=3D2>Please everyone,=20
before there is mass hysteria, go back and reread the paper. Nobody is =
proposing doing away with date codes! Just the practice of ordering =
specific=20
date codes unless there is a good reason for it.</FONT></SPAN></DIV>
<DIV> </DIV>
<P><FONT =
size=3D2>Bob<BR><BR>=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D<BR>Robert=20
Barr<BR>Manufacturing Engineering<BR>Formation, Inc.<BR>Voice: =
856-234-5020=20
x3035<BR>Fax: 856-234-6679 </FONT></P>
<BLOCKQUOTE dir=3Dltr=20
style=3D"BORDER-LEFT: #000000 2px solid; MARGIN-LEFT: 5px; =
MARGIN-RIGHT: 0px; PADDING-LEFT: 5px">
<DIV align=3Dleft class=3DOutlookMessageHeader dir=3Dltr><FONT =
face=3DTahoma=20
size=3D2>-----Original Message-----<BR><B>From:</B> TechNet=20
[mailto:[log in to unmask]]<B>On Behalf Of </B>Jack =
Crawford<BR><B>Sent:</B>=20
Monday, April 29, 2002 4:54 PM<BR><B>To:</B>=20
[log in to unmask]<BR><B>Subject:</B> [TN] Proposed lifting of =
component date=20
code restrictions<BR><BR></FONT></DIV>
<DIV><FONT size=3D1>IPC has become aware that t</FONT><FONT =
size=3D1>he National=20
Electronics Distributors Association (NEDA) has posted a white paper =
discussing the proposed lifting of date code restrictions and they =
have=20
requested comments from end users as well as component suppliers and =
distributors. The paper can be viewed at <A=20
=
href=3D"http://www.nedassoc.org/whitedat.html">http://www.nedassoc.org/wh=
itedat.html</A>.</FONT></DIV>
<DIV> </DIV>
<DIV><FONT size=3D1>Comments can be provided to me on or off net; =
we'll=20
compile them and forward to NEDA. If you comment to NEDA =
directly <A=20
=
href=3D"mailto:[log in to unmask],">[log in to unmask],</A> please =
cc: me=20
on your reply <A=20
=
href=3D"mailto:[log in to unmask]">[log in to unmask]</A>.<BR></FONT>=
</DIV>
<DIV><FONT size=3D1>Cordially</FONT></DIV>
<DIV><FONT size=3D1>Jack</FONT></DIV>
<DIV> </DIV>
<DIV><FONT =
size=3D1>=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D<BR>APEX =
2003 -=20
the industry's premier trade show in Electronics<BR>Manufacturing, =
March=20
31-April 2, 2003, Anaheim, California.<BR>More information on =
website <A=20
=
href=3D"http://www.goapex.org">www.goapex.org</A><BR>--------<BR>Jack=20
Crawford, IPC Director of Assembly Standards and Technology<BR>2215 =
Sanders=20
Road, Northbrook IL 60062-6135<BR><A=20
href=3D"mailto:[log in to unmask]">[log in to unmask]</A> =
<BR>847-790-5393<BR>fax=20
847-504-2393</DIV></BLOCKQUOTE></BLOCKQUOTE></FONT></BODY></HTML>
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Date: Tue, 30 Apr 2002 14:04:13 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Proposed lifting of component date code restrictions
X-To: Mel Parrish <[log in to unmask]>
MIME-Version: 1.0
Content-Type: text/plain; charset="iso-8859-1"
Content-Transfer-Encoding: 7bit
Many times and more so recently. Sorry, no grins here.
MoonMan
----- Original Message -----
From: "Mel Parrish" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Tuesday, April 30, 2002 12:03 PM
Subject: Re: [TN] Proposed lifting of component date code restrictions
> Just for grins, how many have run into variation in component materials
and
> processes such as a different die source, adhesives, process profiles,
cure,
> etc. within a specific date code?
> Scary, isn't it.
>
> Mel Parrish
> Soldering Technology International
> 102 Tribble Drive
> Madison, AL 35758
> 256 705 5530
> 256 705 5538 Fax
> [log in to unmask]
> www.solderingtech.com
>
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Kathy Kuhlow
> Sent: Tuesday, April 30, 2002 8:45 AM
> To: [log in to unmask]
> Subject: Re: [TN] Proposed lifting of component date code restrictions
>
>
> There are many instances in everyone's career where we sorted by or found
> problems with date codes. Many times that was the only sort criteria.
Just
> got bit again from a broker for a very old part, just finished our 450 PC
> rework.
>
> It also makes me very concerned having been in serious medical device
> assembly. Now the proposal would allow what ever date code out and lose
> that traceability for the next generation of pacemakers and various other
> life support systems or military applications like a shuttle. The
> manufacturer's may know more about handling, processing, etc but the
> distributors don't know nor do the brokers.
>
> Not one manufacturer out there is always providing 100% quality, there are
> problems. The only thing that can make this a possibility in my mind
would
> be if the manufacturers are going to support all parts when an issue comes
> up and the financial burden to remove all from inventory instead of a
> specific batch.
>
> Don't let them lose the date code that we all have come to depend on.
>
> Kathy
>
> --------------------------------------------------------------------------
-------
> Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
> To unsubscribe, send a message to [log in to unmask] with following text in
> the BODY (NOT the subject field): SIGNOFF Technet
> To temporarily halt delivery of Technet send e-mail to [log in to unmask]:
SET Technet NOMAIL
> To receive ONE mailing per day of all the posts: send e-mail to
[log in to unmask]: SET Technet Digest
> Search the archives of previous posts at: http://listserv.ipc.org/archives
> Please visit IPC web site http://www.ipc.org/html/forum.htm for additional
> information, or contact Keach Sasamori at [log in to unmask] or 847-509-9700
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Date: Tue, 30 Apr 2002 13:09:00 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Mel Parrish <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Mel Parrish <[log in to unmask]>
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Looking for a fine pitch board fab resource for matte Sn.
Appreciate any information you may have and I'm available offline.
Mel Parrish
Soldering Technology International
102 Tribble Drive
Madison, AL 35758
256 705 5530
256 705 5538 Fax
[log in to unmask]
www.solderingtech.com
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Date: Tue, 30 Apr 2002 14:16:43 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
James TerVeen <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: James TerVeen <[log in to unmask]>
Subject: Re: Proposed lifting of component date code restrictions
X-To: bbarr <[log in to unmask]>
MIME-Version: 1.0
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Bob, I do agree with you. The way I read this white paper is they want to
eliminate the use on date codes when ordering a part. They say nothing
about eliminating the date code. Your take on this document is right on.
Jim
bbarr
<bbarr@FORMATI To: [log in to unmask]
ON.COM> cc:
Sent by: Subject: Re: [TN] Proposed lifting of
TechNet component date code restrictions
<[log in to unmask]
RG>
04/30/02 11:42
AM
Please respond
to "TechNet
E-Mail
Forum.";
Please respond
to bbarr
Please everyone, before there is mass hysteria, go back and reread the
paper. Nobody is proposing doing away with date codes! Just the practice of
ordering specific date codes unless there is a good reason for it.
Bob
=======================
Robert Barr
Manufacturing Engineering
Formation, Inc.
Voice: 856-234-5020 x3035
Fax: 856-234-6679
-----Original Message-----
From: TechNet [mailto:[log in to unmask]]On Behalf Of Jack Crawford
Sent: Monday, April 29, 2002 4:54 PM
To: [log in to unmask]
Subject: [TN] Proposed lifting of component date code restrictions
IPC has become aware that the National Electronics Distributors
Association (NEDA) has posted a white paper discussing the proposed
lifting of date code restrictions and they have requested comments from
end users as well as component suppliers and distributors. The paper can
be viewed at http://www.nedassoc.org/whitedat.html.
Comments can be provided to me on or off net; we'll compile them and
forward to NEDA. If you comment to NEDA directly [log in to unmask], please
cc: me on your reply [log in to unmask]
Cordially
Jack
==========================================
APEX 2003 - the industry's premier trade show in Electronics
Manufacturing, March 31-April 2, 2003, Anaheim, California.
More information on website www.goapex.org
--------
Jack Crawford, IPC Director of Assembly Standards and Technology
2215 Sanders Road, Northbrook IL 60062-6135
[log in to unmask]
847-790-5393
fax 847-504-2393
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Date: Tue, 30 Apr 2002 13:29:43 -0500
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
[log in to unmask]
Sender: TechNet <[log in to unmask]>
From: Richard Carruth <[log in to unmask]>
Subject: Proposed lifting of component date code restrictions
Mime-Version: 1.0
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If manufacturers continue to provide date codes for their products but
distributors discontinue tracking and segregation by date codes the result will
be, mixed date code lots sent to the customer. In many cases assembly houses
that use raw components must capture suspect material by date code. In the event
of field failures or customer defects resulting in corrective action
requirements it is usually imperative to know the problem parts date code to
cover effectivity. I feel that the date codes application should be
standardized. I have also seen where we needed to specifically order certain
date codes because the later date code product did not function properly for the
application.
On the topic of old components verses new components. I have personally seen
some pretty old, nasty components from brokers that appeared to have been
previously used and some that were so oxidized that the leads were nearly black.
So the solderability of 3 or more year old components is a concern. Date codes
need to be standardized and tracked to ensure product quality and
accountability.
Regards,
Richard Carruth
Quality Engineer
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Date: Tue, 30 Apr 2002 21:55:25 +0200
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Gaby Bogdan <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Gaby Bogdan <[log in to unmask]>
Subject: Re: Proposed lifting of component date code restrictions
X-To: David Douthit <[log in to unmask]>
MIME-version: 1.0
Content-type: multipart/alternative;
boundary="Boundary_(ID_vke/nhduJ4clxWR29vd4hw)"
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Also, all components??
Today I dealt with a very trivial connector, solderability problems on specific batch, identified by date code.
Advances, technology, et caetera... how much time would it have taken without the date code?
Gaby
----- Original Message -----
From: David Douthit
To: [log in to unmask]
Sent: Tuesday, April 30, 2002 2:32 AM
Subject: Re: [TN] Proposed lifting of component date code restrictions
Jack,
I agree with Steve's comments. The divergence between the commercial and high reliability electronics is a very serious issue.
Any proposal that effects configuration control must be carefully weighed. Trying to save money no matter what the cost is a
very easy trap to step into.
Standardizing the date code process is needed.
Use of date codes is needed for "life time" buys of COTS when obsolescence problems are present.
Configuration control issues can also cause problems with commercial OEMs.
Unless tracking methods are in place part failures by lot would be difficult to isolate in higher assemblies.
This could create a much larger recall condition.
Just some comments.
David A. Douthit
Manager
LoCan LLC
Jack Crawford wrote:
IPC has become aware that the National Electronics Distributors Association (NEDA) has posted a white paper discussing the proposed lifting of date code restrictions and they have requested comments from end users as well as component suppliers and distributors. The paper can be viewed at http://www.nedassoc.org/whitedat.html. Comments can be provided to me on or off net; we'll compile them and forward to NEDA. If you comment to NEDA directly [log in to unmask], please cc: me on your reply [log in to unmask] ==========================================
APEX 2003 - the industry's premier trade show in Electronics
Manufacturing, March 31-April 2, 2003, Anaheim, California.
More information on website www.goapex.org
--------
Jack Crawford, IPC Director of Assembly Standards and Technology
2215 Sanders Road, Northbrook IL 60062-6135
[log in to unmask]
847-790-5393
fax 847-504-2393
--Boundary_(ID_vke/nhduJ4clxWR29vd4hw)
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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
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<META content="MSHTML 5.50.4207.2601" name=GENERATOR>
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<BODY style="MARGIN-TOP: 2px; FONT: 8pt MS Sans Serif; MARGIN-LEFT: 2px"
bgColor=#ffffff>
<DIV><FONT face=Arial size=2>Also, all components??</FONT></DIV>
<DIV><FONT face=Arial size=2>Today I dealt with a very trivial connector,
solderability problems on specific batch, identified by date code.</FONT></DIV>
<DIV><FONT face=Arial size=2>Advances, technology, et caetera... how much time
would it have taken without the date code?</FONT></DIV>
<DIV><FONT face=Arial size=2>Gaby</FONT></DIV>
<BLOCKQUOTE dir=ltr
style="PADDING-RIGHT: 0px; PADDING-LEFT: 5px; MARGIN-LEFT: 5px; BORDER-LEFT: #000000 2px solid; MARGIN-RIGHT: 0px">
<DIV style="FONT: 10pt arial">----- Original Message ----- </DIV>
<DIV
style="BACKGROUND: #e4e4e4; FONT: 10pt arial; font-color: black"><B>From:</B>
<A [log in to unmask] href="mailto:[log in to unmask]">David Douthit</A>
</DIV>
<DIV style="FONT: 10pt arial"><B>To:</B> <A [log in to unmask]
href="mailto:[log in to unmask]">[log in to unmask]</A> </DIV>
<DIV style="FONT: 10pt arial"><B>Sent:</B> Tuesday, April 30, 2002 2:32
AM</DIV>
<DIV style="FONT: 10pt arial"><B>Subject:</B> Re: [TN] Proposed lifting of
component date code restrictions</DIV>
<DIV><BR></DIV>Jack,
<P>I agree with Steve's comments. The divergence between the commercial
and high reliability electronics is a very serious issue. <BR>Any proposal
that effects configuration control must be carefully weighed. Trying to save
money no matter what the cost is a <BR>very easy trap to step into.
<P>Standardizing the date code process is needed. <BR>Use of date codes is
needed for "life time" buys of COTS when obsolescence problems are present.
<P>Configuration control issues can also cause problems with commercial OEMs.
<BR>Unless tracking methods are in place part failures by lot would be
difficult to isolate in higher assemblies. <BR>This could create a much larger
recall condition.
<P>Just some comments.
<P>David A. Douthit <BR>Manager <BR>LoCan LLC
<P>Jack Crawford wrote:
<BLOCKQUOTE TYPE="CITE"> <FONT size=-2>IPC has become aware that the
National Electronics Distributors Association (NEDA) has posted a white
paper discussing the proposed lifting of date code restrictions and they
have requested comments from end users as well as component suppliers and
distributors. The paper can be viewed at <A
href="http://www.nedassoc.org/whitedat.html">http://www.nedassoc.org/whitedat.html</A>.</FONT> <FONT
size=-2>Comments can be provided to me on or off net; we'll compile them and
forward to NEDA. If you comment to NEDA directly <A
href="mailto:[log in to unmask],">[log in to unmask],</A> please cc: me on
your reply <A
href="mailto:[log in to unmask]">[log in to unmask]</A>.</FONT><FONT
size=-2>Cordially</FONT><FONT size=-2>Jack</FONT> <FONT
size=-2>==========================================</FONT> <BR><FONT
size=-2>APEX 2003 - the industry's premier trade show in Electronics</FONT>
<BR><FONT size=-2>Manufacturing, March 31-April 2, 2003, Anaheim,
California.</FONT> <BR><FONT size=-2>More information on website <A
href="http://www.goapex.org">www.goapex.org</A></FONT> <BR><FONT
size=-2>--------</FONT> <BR><FONT size=-2>Jack Crawford, IPC Director of
Assembly Standards and Technology</FONT> <BR><FONT size=-2>2215 Sanders
Road, Northbrook IL 60062-6135</FONT> <BR><FONT size=-2><A
href="mailto:[log in to unmask]">[log in to unmask]</A></FONT> <BR><FONT
size=-2>847-790-5393</FONT> <BR><FONT size=-2>fax
847-504-2393</FONT></BLOCKQUOTE></BLOCKQUOTE></BODY></HTML>
--Boundary_(ID_vke/nhduJ4clxWR29vd4hw)--
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Date: Tue, 30 Apr 2002 15:43:35 -0400
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
Earl Moon <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: Earl Moon <[log in to unmask]>
Subject: Re: Proposed lifting of component date code restrictions
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always had a hard time with distributors and certs. no traceability possible
often. no test data concerning solderability or whatever. customers partly
to blame as price drives the whole thing with no recourse.
moonman
----- Original Message -----
From: "Richard Carruth" <[log in to unmask]>
To: <[log in to unmask]>
Sent: Tuesday, April 30, 2002 2:29 PM
Subject: [TN] Proposed lifting of component date code restrictions
> If manufacturers continue to provide date codes for their products but
> distributors discontinue tracking and segregation by date codes the result
will
> be, mixed date code lots sent to the customer. In many cases assembly
houses
> that use raw components must capture suspect material by date code. In the
event
> of field failures or customer defects resulting in corrective action
> requirements it is usually imperative to know the problem parts date code
to
> cover effectivity. I feel that the date codes application should be
> standardized. I have also seen where we needed to specifically order
certain
> date codes because the later date code product did not function properly
for the
> application.
>
> On the topic of old components verses new components. I have personally
seen
> some pretty old, nasty components from brokers that appeared to have been
> previously used and some that were so oxidized that the leads were nearly
black.
> So the solderability of 3 or more year old components is a concern. Date
codes
> need to be standardized and tracked to ensure product quality and
> accountability.
>
> Regards,
>
> Richard Carruth
> Quality Engineer
>
> --------------------------------------------------------------------------
-------
> Technet Mail List provided as a free service by IPC using LISTSERV 1.8d
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Date: Tue, 30 Apr 2002 15:21:58 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
"Mcmaster, Michael" <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: "Mcmaster, Michael" <[log in to unmask]>
Subject: Re: Via Plug
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Peter
That's exactly what I was getting at. Most of our applications for CB-100
are for filled vias that need to be plated over to provide a solderable
surface and/or prevent solder from running out the bottom end of the via.
> ----------
> From: [log in to unmask][SMTP:[log in to unmask]]
> Reply To: TechNet E-Mail Forum.;[log in to unmask]
> Sent: Monday, April 29, 2002 5:40 PM
> To: [log in to unmask]
> Subject: Re: [TN] Via Plug
>
> I just did a calculation for some of our boards that use this via plug
> material for enhancing thermal transfer between chips and thermal planes.
> The calculation was to see by how much I would have to increase hole
> plating thickness by in order to completely replace the epoxy in terms of
> thermal conductivity.
>
> I'm talking about a 24 mils diameter hole, plated initially to 1/2 oz
> copper minimum and filled with epoxy. The board is 63 mils thick. Can you
> guess what the increase is? ..... It's actually only 0.2 oz or 0.28 mils,
> according to our thermal engineer. So why go to all the trouble and
> expense
> of filling holes if the only purpose is thermal - a fairly small increase
> in plating thickness is all that's needed.
>
> Peter
>
>
>
> Earl Moon <[log in to unmask]> 30/04/2002 05:49 AM
> Sent by: TechNet <[log in to unmask]>
>
> Please respond to "TechNet E-Mail Forum."; Please respond to Earl Moon
>
> To: [log in to unmask]
> cc: (bcc: DUNCAN Peter/Asst Prin Engr/ST Aero/ST Group)
> Subject: Re: [TN] Via Plug
>
>
>
>
>
>
>
>
> Don't mean to but in, but what the hell. Just think how much surface
> copper
> would be plated and how much resist would have to be applied and how much
> plating overhang would be involved even with several resist layers
> applied,
> etc..
>
> MoonMan
>
> --------------------------------------------------------------------------
> -------
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Date: Tue, 30 Apr 2002 19:29:48 EDT
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: Vacuum sealing equipment...
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Hi All!
Our McDry dessicant cabinets have just been over-populated recently due to
having to open vendor-sealed packages looking for certain DATECODE
parts...(hmmm, this subject seems familiar for some odd reason...)
Anyhoo, we've got a regular thermal sealer here, but we have now seen the
need for a vacuum sealer...
A vacuum sealer just gives me a warm and fuzzy feeling knowing that air has
been sucked out of the packaging with a dessicant packed in there with the
parts, sealed off from the outside world as we know it, and they're slowly
suffocating, slowly.. slowly..slowly. The moisture being steadily drained
from their lifeless and uncaring souls...HA!HA!HA!HA!HA!
Ahem, 'scuse me. Kinda' got carried away there, didn't I? Didn't mean
to...really...my job isn't getting to me, it really isn't...honest.
I did a search and got a gazillion hits for vacuum sealers, do any of you
have one that you can recommend and like, to help me from having to make too
many decisions?
'preciate it!!!
-Steve Gregory-
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Date: Tue, 30 Apr 2002 17:02:00 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
David Douthit <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: David Douthit <[log in to unmask]>
Subject: Re: Proposed lifting of component date code restrictions
X-To: Mel Parrish <[log in to unmask]>
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Mel,
Careful, configuration control is a very touchy subject!!!
David A. Douthit
Manager
LoCan LLC
Mel Parrish wrote:
> Just for grins, how many have run into variation in component materials and
> processes such as a different die source, adhesives, process profiles, cure,
> etc. within a specific date code?
> Scary, isn't it.
>
> Mel Parrish
> Soldering Technology International
> 102 Tribble Drive
> Madison, AL 35758
> 256 705 5530
> 256 705 5538 Fax
> [log in to unmask]
> www.solderingtech.com
>
> -----Original Message-----
> From: TechNet [mailto:[log in to unmask]]On Behalf Of Kathy Kuhlow
> Sent: Tuesday, April 30, 2002 8:45 AM
> To: [log in to unmask]
> Subject: Re: [TN] Proposed lifting of component date code restrictions
>
> There are many instances in everyone's career where we sorted by or found
> problems with date codes. Many times that was the only sort criteria. Just
> got bit again from a broker for a very old part, just finished our 450 PC
> rework.
>
> It also makes me very concerned having been in serious medical device
> assembly. Now the proposal would allow what ever date code out and lose
> that traceability for the next generation of pacemakers and various other
> life support systems or military applications like a shuttle. The
> manufacturer's may know more about handling, processing, etc but the
> distributors don't know nor do the brokers.
>
> Not one manufacturer out there is always providing 100% quality, there are
> problems. The only thing that can make this a possibility in my mind would
> be if the manufacturers are going to support all parts when an issue comes
> up and the financial burden to remove all from inventory instead of a
> specific batch.
>
> Don't let them lose the date code that we all have come to depend on.
>
> Kathy
>
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Date: Tue, 30 Apr 2002 17:10:13 -0700
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>,
David Douthit <[log in to unmask]>
Sender: TechNet <[log in to unmask]>
From: David Douthit <[log in to unmask]>
Subject: Re: Proposed lifting of component date code restrictions
X-To: [log in to unmask]
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boundary="------------6250E4B547CBBED67430FC62"
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Dave,
Thank you for this; I believe the white paper is offering a very,
very skewed viewpoint of solderability issues within the electronic
assembly industry.
Self serving papers are all over the place. Some, such as this one, can create
massive problems if followed. Unfortunalty certain management types
(particularly in the current business climate) will grab anything that looks good.
This wastes time that we can ill afford.
David A. Douthit
Manager
LoCan LLC
Dave Hillman wrote:
> Hi Jack! Just a comment echoing the TechNet chorus - a component date code
> is a tracking number which serves a multitude of purposes of which
> solderability aspects are just one specific issue. I am also quite
> skeptical of the white paper viewpoint of solderability being a "well
> understood" and "controlled" topic - if that were the case then why are
> there so many participants in the JSTD-002 committee involving the IPC,
> EIA, and JEDEC associations? Heavens knows I would like to work on other
> issues than solderability but I believe the white paper is offering a very,
> very skewed viewpoint of solderability issues within the electronic
> assembly industry.
>
> Dave Hillman
> JSTD 002A CoChairman
> [log in to unmask]
>
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<html>
Dave,
<p>Thank you for this; <i>I believe the white paper is offering a very,</i>
<br><i>very skewed viewpoint of solderability issues within the electronic</i>
<br><i>assembly industry.</i><i></i>
<p>Self serving papers are all over the place. Some, such as this one,
can create
<br>massive problems if followed. Unfortunalty certain management types
<br>(particularly in the current business climate) will grab anything that
looks good.
<br>This wastes time that we can ill afford.
<p>David A. Douthit
<br>Manager
<br>LoCan LLC
<br>
<br>
<p>Dave Hillman wrote:
<blockquote TYPE=CITE>Hi Jack! Just a comment echoing the TechNet chorus
- a component date code
<br>is a tracking number which serves a multitude of purposes of which
<br>solderability aspects are just one specific issue. I am also quite
<br>skeptical of the white paper viewpoint of solderability being a "well
<br>understood" and "controlled" topic - if that were the case then why
are
<br>there so many participants in the JSTD-002 committee involving the
IPC,
<br>EIA, and JEDEC associations? Heavens knows I would like to work on
other
<br>issues than solderability but I believe the white paper is offering
a very,
<br>very skewed viewpoint of solderability issues within the electronic
<br>assembly industry.
<p>Dave Hillman
<br>JSTD 002A CoChairman
<br>[log in to unmask]
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Date: Tue, 30 Apr 2002 23:14:12 EDT
Reply-To: "TechNet E-Mail Forum." <[log in to unmask]>, [log in to unmask]
Sender: TechNet <[log in to unmask]>
From: [log in to unmask]
Subject: A "NEDA" Oriented label...
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Was given a image of a label on packaging that's out there as we speak, as
something that would be more wide-spread if NEDA has their way...go to:
http://www.stevezeva.homestead.com
and look at NEDA label.jpg...
Really helps, doesn't it?
-Steve Gregory-
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